Category Archives: Wafer Level Packaging

January 24, 2012 – Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique. The method also can be applied to detect voids in TSVs during processing, they claim.

The initial focus of their work was to develop metrology for detecting voids after temporary wafer bonding of 3D wafers, which remains challenging because development of interface particles and voids can impact subsequent wafer thinning processes, as well as overall wafer thinning and tool performance.

To address this, PVA Tepla and imec developed an automated foup-to-foup, wafer-level process based on 200MHz SAM using Tepla

frederic-raynalFrederic Raynal, CTO, Alchimer

Looking at 2014, we see challenges and innovations in both the front-end semiconductor and 3D TSV markets.

In the front end, we are seeing a focus on further scaling to smaller nodes. For logic, TSMC has just announced it is ready for 16nm node, and Intel is ramping to 14nm. Industry experts question whether shrinking to 10nm will be feasible from a technology perspective. For example, at 10nm, most of the layers in copper interconnection must be between 2 and 4nm thick, which poses challenges for the technologies used in volume manufacturing. Controlling the thickness of single as well as dual damascene layers requires new technologies, such as electrografting, which is much more controllable and able to meet emerging requirements. We strongly believe that new technologies will need to be introduced for logic at the 10nm node and memory at the 16nm node, with ramp occurring at the 10nm node for the industry to maintain the path of Moore’s law.

We also expect to see 3D TSVs ramping to production in 2014. This is another area where innovation is needed that can meet demanding performance requirements while controlling costs, since cost is currently holding back widespread adoption of 3D-ICs. High-aspect-ratio (HAR) vias are a good candidate for new technology like electrografting, which is cost competitive compared with electrochemical deposition, chemical vapor deposition or physical vapor deposition, and delivers higher performance. For example, 40:1 aspect-ratio capabilities were recently demonstrated for electrografted barrier and seed layers, and 20:1 aspect ratio for fill processes.

It is widely expected that both the front-end and packaging areas of the semiconductor industry are poised for growth in 2014. Continued technology innovations will be a key driver in both areas in order to meet emerging performance requirements while successfully controlling cost and overcoming current roadblocks.

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January 18, 2013 – Ziptronix Inc. says it has signed a licensing agreement with Novati Technologies Inc. for the use of its patented direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond).

Novati, the former SVTC facility in Austin which was acquired and relaunched by Tezzaron Semiconductor last fall, will use the technology for 3D stacking services and test. Tezzaron itself recently licensed Ziptronix’s DBI and ZiBond patents for use in 3D memory.

"Adding Ziptronix 3D process technologies to Novati’s existing wafer fabrication and testing facilities enables Novati to become the first open-platform, full-line foundry in the world offering 3D stacking services and test to all its customers," stated Dave Anderson, CEO of Novati Technologies. "We believe 3D is the new cutting edge of product development and we intend to continue our heritage as a contract R&D and lab-to-fab production facility enabling customers to cost-effectively prototype and test both 2.5D interposer and 3D designs with true, 3D integration and TSV interconnect."

"With our DBI, which contains interconnect at the bond interface, Novati can now provide technologically advanced services in many different markets at a lower cost and better performance compared to competing technologies also attempting 3D integration," added Ziptronix CEO Dan Donabedian.

January 11, 2012 – GlobalFoundries says it plans to build a $2 billion R&D facility at its Fab 8 campus in Saratoga County, NY. The new Technology Development Center (TDC) will span more than 500,000 sq. ft of "flexible space" for various technology development and manufacturing activities, including cleanroom and lab space. Construction is planned to begin in early 2013 and completed in late 2014.

The TDC will focus on a variety of semiconductor development and manufacturing work "to support the transition to new technology nodes," and development of "innovative capabilities to deliver value to customers beyond the traditional approach of shrinking transistors," according to the company. Broadly speaking, the TEC is planned to be a collaborative space to develop "end-to-end solutions covering the full spectrum of silicon technology," from EUV lithography photomasks to new interconnect and packaging technologies enabling 3D chip stacking, "and everything in between."

"As the industry shifts from the PC era to a market focused on mobile devices, we have seen increasingly strong interest from customers in migrating to advanced nodes on an accelerated schedule," stated GlobalFoundries CEO Ajit Manocha. "To help facilitate this migration, we are making significant investments in strengthening our technology leadership, including growing our workforce and adding new capabilities to make Fab 8 the hub of our global technology operations." Toward that end, "the new TDC will help us bridge between the lab and the fab by taking research conducted with partners and further developing the technologies to make them ready for volume manufacturing," he added

Other regional New York State leaders chimed in with appreciation and optimism for the project’s synergy with the local and regional economy. "New York has become the world’s hub for advanced semiconductor research and now, the Technology Development Center will further help ensure the innovations developed in New York, in collaboration with our research institutions, are manufactured in New York," said Governor Andrew M. Cuomo. "New York State’s public investments to develop CNSE as a hub of innovation coupled with the private investments of GLOBALFOUNDRIES are prime examples of best practices for public-private partnerships linking research, innovation and production that have made New York a globally recognized center of innovation," added Charles W. Wessner, director of the National Academies’ Innovation Program.

GlobalFoundries began developing its Fab 8 project in the summer of mid-2009; today its campus includes approximately 2 million sq. ft of development. The company has continued to make investments in manufacturing production as well as technology development, including work underway on 20nm and 14nm technology nodes.

Jim Mello, Vice President, Sales and Marketing, Entrepix, Inc.

The global economic difficulties are impacting the semiconductor industry more now than ever because the world has become increasingly interconnected and more consumer driven. The financial crisis in Europe, the "fiscal cliff" in the US and the slow down in China’s growth have made it more difficult for any one catalyst to push the markets in a positive direction. Ultimately, the semiconductor industry is caught up in this environment and its outlook continues to be mixed, which points towards a flat 2013. While smart phones and tablets will continue to drive the markets for communication chips, CMOS image sensors and many other types of sensors, the semiconductor industry will not be able to overcome the stagnation of the PC market. The momentum for more powerful, smaller and faster portable devices will dominate the PC market, continuing to drive smaller system packaging technologies and less power consumption while creating more functionality and memory capacity. Technology investments will continue for the advanced nodes and leading edge packaging development, but until the confidence of the economy comes back, the capacity investments will be selective based on individual markets. 

One of the biggest challenges for the industry is that 80 percent of the devices used for portable and mobile applications are currently manufactured on 200mm or smaller wafers. How this plays out going forward could change who the dominant players will be and therefore could drive consolidation. As the communications market advances, design wins play a large role in the uncertainty. The secondary equipment market provides ongoing opportunities throughout the entire market, especially during periods of economic difficulty, and is extremely well positioned to capitalize on the continued strength of the 200mm market. Remanufactured equipment continues to demonstrate its viability within the industry, often being sold with guaranteed reliability and shorter lead times that allow for capacity investments that can accommodate changes in short term demand. Additional value-add can be found in the secondary market from a subset of suppliers who are specialized in specific processes. These vendors provide process development and fully qualified processes to customers to accelerate the manufacturing ramp and further enhance the cost of ownership benefits of refurbished equipment.

By Ardy Johnson, Vice President of Marketing and Product Management, Rudolph Technologies, Inc.

Advanced packaging is in the early stages of a dynamic growth phase. Demand for equipment and related tools in the 3DIC and wafer-level packaging area is forecasted to grow from approximately $370 million in 2010 to over $2.5 billion by 2016. Advanced packaging requirements are driving the evolution of back end manufacturing to become more similar to the front end where the need to tie the entire process together with effective process control has long been established. Rudolph, with a long history in both the front end and back end, is participating fully in this evolution with a “total solution” approach, as exemplified by our recent entry into the back end photolithography market.

Ideally, a photolithography solution for advanced packaging begins with a reduction stepper that is uniquely capable of meeting current and future requirements of advanced packaging processes: greater depth of focus to handle the thicker resists required by exaggerated wafer topography; flexible automation and specialized handling for warped wafers, reconstituted wafers, and large panels; on-the-fly focusing at every exposure to ensure maximum image quality; and an on-board reticle library and fast-change reticle wheel for increased productivity. But the full power of the total solution derives from integrating the stepper with a suite of inspection and metrology tools and process control software: an inspection tool for CD overlay measurements; APC software for closed loop, run to run control; and a yield management system to provide fab-wide, automated, real-time process control feedback.

Fleet management provides another example of the use of automated data collection and analysis to increase equipment uptime, improve yield, and reduce production costs. It monitors the output and operational parameters of inspection and metrology tools performing similar tasks to detect statistical excursions that indicate tool health and stability. One important benefit of fleet management is the ability to improve tool matching-based actual performance.

As backend processes continue to evolve, incorporating the next generation packaging technologies needed to reduce size and increase functionality is a necessity, and manufacturers will derive increasing value from an integrated, total solution approach.

By Arthur W. Zafiropoulo, Chairman and CEO, Ultratech, Inc.

After all the speculation, discussions and debates, the transition to 450-mm wafers will happen.  As an equipment manufacturer, it is not enough to simply survive, but it is imperative to thrive in the transition to 450mm. While driven by all the major semiconductor companies, the transition to 450-mm wafers will have a compounding effect on equipment manufacturers’ R&D investments. By combining the technology challenges and the wafer diameter change, companies in the equipment industry will require a strong balance sheet to be successful.

Smart companies know that success lies in the ability to be bold and aggressive in R&D and remain conservative on the balance sheet. Success is also determined by a company’s efforts to prepare for the future by investing and developing the right technologies and supporting capabilities. By developing innovative technologies that address the critical issues around the transition and adoption, companies can play an enabling role for 450mm. At Ultratech, we have prepared for the transition to 450mm in our design concepts for our laser spike anneal (LSA) and advanced packaging systems. Both of these products offer the lowest technical risks due their scanning and step and repeat processes. We have added a new inspection technology targeted at device, wafer stress and pattern overlay, which will quickly identify yield and device performance issues.

To provide our customers with competitive advantages, Ultratech introduced seven advanced technology products in 2012 and each one serves a different market. With our LSA technology already proven to reduce stress on the wafer, we introduced two dual-beam laser systems that are built on the Unity Platform™, and are easily scalable for 450-mm applications. We believe the 450-mm LSA systems will provide the industry with new process capabilities that did not previously exist, and the first system will be delivered to the G450 Consortium at the end of 2013.

Also, Ultratech has developed a new technology, Superfast 3G, based on patented coherent gradient sensing technology (CGS) for inspection using a fundamental stress measurement technique to analyze deformation on a microscale over the entire wafer. The system has the flexibility to be implemented anywhere in the production line―front-, middle- and back-end-of-line―to address stress issues confronting leading-edge device manufacturers. 

The development of innovative technologies that solve the critical issues for the transition and adoption of 450-mm manufacturing will be the defining factor for whether a company merely survives or thrives. Ultratech is a company that is thriving.

At the recent Georgia Tech-hosted International Interposer Conference, Matt Nowak of Qualcomm and Nagesh Vordharalli of Altera both pointed to the necessity for interposer costs to reach 1$ per 100mm2 for them to see wide acceptance in the high-volume mobile arena. For Nowak, the standard interposer would be something like ~200mm2 and cost $2. The question that was posed but unanswered was: "Who will make such a $2 interposer?"

Less than a month later, this question began to be answered as several speakers at the year-ending RTI ASIP conference (Architectures for Semiconductor Integration and Packaging) began to lift the veil on silicon interposer pricing.

Sesh Ramaswami, managing director at Applied Materials, showed a cost analysis which resulted in 300mm interposer wafer costs of $500-$650 / wafer. His cost analysis showed the major cost contributors are damascene processing (22%), front pad and backside bumping (20%), and TSV creation (14%).

Ramaswami noted that the dual damascene costs have been optimized for front-end processing, so there is little chance of cost reduction there; whereas cost of backside bump could be lowered by replacing polymer dielectric with oxide, and the cost of TSV formation can be addressed by increasing etch rate, ECD (plating) rate, and increasing PVD step coverage.

Since one can produce ~286 200mm2 die on a 300mm wafer, at $575 (his midpoint cost) per wafer, this results in a $2 200mm2 silicon interposer.

Lionel Cadix, packaging analyst of Yole D

December 19, 2012 – Singapore’s Institute of Microelectronics (IME), a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR), has launched a new multiproject wafer service (MPW) for 2.5D through-silicon interposers, to provide a cost-effective platform for R&D prototyping and proof-of-concept in the technology.

The 2.5D interposer MPW service, supported by IME’s 3D through-silicon via (TSV) engineering line, includes the following modules:

  • Leveraging industry standard Electronic Design Automation (EDA) tools to perform 2.5D TSI design, extraction and verification;

  • TSV with critical dimension (CD), e.g. 10-50

December 17, 2012 – Tezzaron Semiconductor has licensed patents regarding Ziptronix’s direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), for use in 3D memory.

Bob Patti, CTO of Tezzaron, pointed to "a direct and robust synergy" between his company’s FaStack 3D technology and Ziptronix’s technologies, calling them "a formidable team." (The two companies have been partnering on 3D ICs since 2005.) This deal broadens Tezzaron’s capabilities in producing advanced 3D memories and extends the scope of 3D and 2.5D devices it can assemble for customers. "With this suite of powerful technologies, we offer a truly ‘one-stop’ solution for both 3D and 2.5D," he said.

Traditional die stacking requires die thinning and thinned-die handling and development of reliable interconnect processes. Ziptronix DBI combines proprietary wafer-level low-temperature oxide bonding and interconnection. It creates extremely strong low-stress bonds, allowing wafers to be processed and thinned after bonding, eliminating the need to handle thinned wafers and/or dies. Interconnect density and alignment accuracy are high, and the device profile is kept low, Ziptronix notes. The process is compatible with damascene interconnect processing, and various test and repair strategies.

DBI was originally used for backside imaging (BSI) sensors, where Ziptronix claims it delivers cost savings of up to 80% over copper thermo-compression bonding. Earlier this year the company helped a memory manufacturer use the new technology in place of standard die stacking, enabling wafer-level stacking to increase memory density and significantly reduce packaging costs. At the time the company had hinted more licensing deals outside the image sensor space were in the pipeline.

"With our DBI, which contains interconnect at the bond interface, Tezzaron can provide a technologically superior product in the memory market at a lower cost and better performance compared to competitors also attempting 3D integration of advanced memory devices," stated Ziptronix CEO Dan Donabedian. "Tezzaron stands alone today in its adoption of the most advanced interconnection technology and therefore will lead the industry in technology areas only imagined just a few short years ago."