Category Archives: Wafer Level Packaging

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM). They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction and improves manufacturability. The new architecture also enables the use of a novel “staircase” bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75 nm, 64 cells per string and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional sub-20nm 2D NAND, it can provide 1 Tb of memory if further scaled to 25nm feature sizes. At that size the Macronix device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density.

A previously proposed 3D vertical gate NAND architecture.

An overview of the proposed architectural layout that is said to be an improvement.

 

A cross-sectional views of the new device.

 

TEM electron microscope views of the staircase bitline contacts.

RRAM synapses mimic the brain


September 20, 2012

Neuromorphic, or brain-like, electronic systems that mimic cognitive functions are the focus of research because of their potential for complex tasks such as pattern-recognition. Papers presented at the International Electron Devices Meeting in 2011 described studies using programmable phase-change memory (PCM) synapses in neuromorphic systems to carry out a function called spike-timing-dependent plasticity (STDP). STDP is an electronic analog of a brain mechanism for learning and memory, so an electronic system that accurately performs STDP can be said to be “learning.”

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP. The 1-Kb RRAM array has a simple crosspoint structure and possibly can be scaled to 4F (the theoretical minimum size for a crosspoint array). The work shows the feasibility of using neuromorphic architecture for high-speed pattern recognition.

 

 

Photo of CMOS neuron circuit with 1kB RRAM array as synapse

 

 

Schematic structure of the proposed system. Input spikes come from the left into the RRAM array. (The inset shows the user interface of a computer simulator.)  The ten input images in the neuromorphic system are learned by edge weighting, and during the learning process ‘5’ in node 4 is represented clearly.

 

In this comparison of artificial brain projects, Gwangju Institute of Science and Technology’s neuromorphic device is compared to other reported devices.

Flash memory lifetimes are limited by use, because repeated program/erase (P/E) cycles degrade the tunnel oxide which insulates flash memory cells. In principle, heating the oxide will repair the damage but thermal annealing has been impractical because flash memories can’t tolerate the high temperatures and long baking times required.

At the upcoming International Electron Devices Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed. They modified the wordline from a single-ended to a double-ended structure, which enabled current to be passed through the gate to generate Joule heating. High temperatures (>800° C) thus were generated only in immediate proximity to the gate. The devices demonstrated record-setting endurance of >100 million P/E cycles with excellent data retention. Interestingly, the researchers also saw that the heating enabled faster erasing, which is thought to be temperature-independent.

 

The schematic image above shows the structure of the diode-strapped wordline. A PN diode can be formed directly on top of the wordline, and local interconnect can be used to connect to the metal heat plates.

The 58th annual International Electron Devices Meeting (IEDM) will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.

Highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel’s unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM’s demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to vanishingly small sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.

“The IEDM can be a crystal ball looking into the future of technology evolution. Leading-edge technologies and novel devices reported at the conference will shine light on the industrial mainstream in the next three-to-five years,” said Tzu-Ning Fang, IEDM 2012 Publicity Chair and Senior Member, Technical Staff, at Spansion, Inc. “This year’s program shows a tremendous amount of work being done in emerging technologies, including novel materials such as molybdenum sulfide, new structures, 3D NAND memories, wider use of III-V materials, MRAM, nanowires and more.”

Besides the IEDM technical program, attendees will enjoy evening panel sessions, Short Courses, award presentations and other events, as follows:

90-Minute Tutorials — Saturday, Dec. 8

Back by popular demand for the second year, the IEDM will hold 90-minute tutorial sessions on emerging topics presented by experts in the fields. They are meant to bridge the gap between established textbook-level knowledge and the leading-edge research as presented during the conference. The tutorial sessions will be presented in parallel in two time slots. Advance registration is required.

2:45-4 p.m.

High Mobility Channel CMOS Transistors – Beyond Silicon by Shinichi Takagi, University of Tokyo

Fundamentals of GaN Based High Frequency Power Electronics by Tomas Palacios, M.I.T.

Spintronics for Embedded Non-Volatile Electronics by Tetsuo Endoh/Tohoku University and Arijit Roychowdhury/Intel

4:30-6:00

2D semiconductors – Fundamental Science and Device Physics by Ali Javey, University of California, Berkeley

Scaling Challenges of Analog Electronics at 32nm and Beyond by Mustafa Badaroglu/IMEC and Bram Nauta/University of Twente

Beyond Charge-Based Computing by Kaushik Roy, Purdue University

Short Courses — Sunday, Dec. 9

The IEDM offers two day-long short courses on Sunday, prior to the technical sessions. They provide the opportunity to learn about emerging areas and important developments, and to benefit from direct contact with expert lecturers. Advance registration is required. This year’s courses are:

Emerging Technologies for Post-14nm CMOS

Circuit and Technology Interaction

Plenary Presentations — Monday, Dec. 10

IEDM 2012 will open on Monday, Dec. 10 at 9 a.m. with three plenary talks:

Flexible Bio-Integrated Electronics by John A. Rogers, University of Illinois

State of the Art and Future Prospects in Display Technologies by Joo-Tae Moon, Senior VP, Director R&D Center, Samsung Display Company

Ultimate Transistor and Memory Technologies: Core of a Sustainable Society by Luc Van den hove, CEO and President IMEC

Emerging Technologies Session — Tuesday morning, Dec. 11

This year’s Emerging Technologies session is on the topic Spintronics: Magnetic Materials and Device Applications, organized by Stefan De Gendt of IMEC. Invited speakers from academia and industry will discuss the challenges, prospects and recent advances in spin-based technology, devices and systems. Following the discovery of the giant magnetoresistance (GMR) effect more than a decade ago, this field has witnessed a veritable revolution encompassing materials and physical phenomena. Electronic devices based on spin transport are expected to play a major role in future information and communication technologies, as spintronic devices will use the spin degree of freedom to store, transport and process information. Papers in this session are:

Spin Transport in Graphene: Fundamental Concepts and Practical Implications by Abdelmadjid Anane et al, Unité Mixte de Physique CNRS/Thales

Thermal Spin Transport and Applications by S. Y. Huang et al, Johns Hopkins/National Tsing Hua University/Academia Sinica

Progress of STT-MRAM Technology and the Effect on Normally-Off Computing Systems, by H. Yoda et al, Toshiba

 Spin Transport in Metal and Oxide Devices at the Nanoscale, by Subir Parui et al, Zernike Institute for Advanced Materials

Error Immunity Techniques for Nanomagnetic Logic, Brian Lambson et al, University of California, Berkeley/Lawrence Berkeley National Lab

Boolean and Non-Boolean Computation With Spin Devices, Mrigank Sharad et al, Purdue University

Luncheon Presentation — Tuesday, Dec. 11

The IEDM Luncheon presentation will be given by Ajit Manocha, CEO of GLOBALFOUNDRIES, Inc., on the topic Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!

Evening Panel Sessions — Tuesday evening, Dec. 11

The IEDM will offer attendees two evening panel discussions. Audience participation is encouraged, with the goal of fostering an open and vigorous exchange of ideas. The panel topics are:

"Will Future Non-Volatile-Memory Contenders Disrupt NAND?" moderated by Al Fazio, Intel

 “The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?” moderated by Suresh Venkatesan, GLOBALFOUNDRIES.

Entrepreneurs Lunch — Wednesday noon, Dec. 12

New for 2012 is an entrepreneurs lunch. The speaker will be Weili Dai, cofounder of Marvell Technology Group and Vice President and General Manager of Marvell’s Communications and Consumer Business. One of the most successful women entrepreneurs in the world, she was named No. 89 on the Forbes list of “The World’s 100 Most Powerful Women” earlier this year.

Further information

For registration and other information, interested persons should visit the IEDM 2012 home page at www.ieee-iedm.org.

Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.

"Our expertise, experience and infrastructure in 2.5D/3D IC process-integration, thin-wafer-handling, and assembly flow provide a compelling value proposition for advanced materials manufacturers to test their products and overcome key technical barriers in the commercialization of 2.5D/3D IC technology,” said Prof. Dim-Lee Kwong, Executive Director of IME. “IME is in a strong position to enable materials development that is increasingly critical to ramping advanced packaging technologies to high volume manufacturing.”

The Interconnect and Packaging Program (IPP) at IME focuses on strategic research areas in the research and development of 3DIC and TSV technologies, including: 3D stacking with chip-to-wafer (C2W) and wafer-to-wafer (W2W) bonding technologies, embedded wafer level packaging, integrated passive device (IPD) with Si or polymer substrate, MEMS packaging, electrical, thermal, mechanical design, materials, process and reliability.

Due to the temperature-hermeticity-sensitivity of the MEMS/MOEMS devices and the thermal-stress effects of the 3D stacked dies, there is a critical need for lower wafer bonding temperatures of below 200°C. At IME, the current R&D focus on low-temperature processes includes: Wafer-to-wafer bonding of hermetic sealed MEMS/MOEMS devices, and chip-to-wafer bonding of 3D stacking with TSV technology and microbump interconnects.

3D research at IME is also focused on TSV formation, including:

•           Dielectric isolation materials and processes

•           High-speed via architectures and filling methods

•           Electrical design and characterization of Si-interposer

•           Global/local design and modeling of interconnects of Cu/ultra low-k large chips

•           Microbump interconnection design, materials, assembly processes and reliability

“IME has strong background technologies of microelectronics, especially in IC packaging technologies, and Hitachi Chemical has many kinds of material for the electronics. I believe this joint research between IME and Hitachi Chemical will contribute greatly to the progress in advanced 3D IC packaging technologies.” said Shun-ichiro Uchimura, Vice President and CTO of Hitachi Chemical.”

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September 6, 2012 – Rudolph Technologies says it has received an order for its MetaPulse G metrology system from "a premier global industry research center in Asia" for its advanced packaging process development activities.

The unidentified group will use the system, which shipped in August, for thin-film metrology performed in development and control of advanced wafer-level packaging processes that use metal structures, such as redirect layers (RDL) and under bump metallization (UBM) to route signals from the chip to the package.

"In addition to providing the fast and accurate measurements of thickness, density and roughness, its small spot size and ability to measure structures directly on product wafers allow users to see pattern dependent variations that are not detectable with monitor wafers," according to Tim Kryman, Rudolph

September 4, 2012 – Ultra Tec Manufacturing has released a new endpoint detection module for its ASAP-1 IPS selected area preparation system, for improving electronic package decapsulation and sample preparation.

The patent-pending hardware/software enhancement to the ASAP-1 IPS provides the capability to quantify and act upon the capacitive and/or resistive properties of electronic device and packaging materials, in order to enhance the sample preparation process. Such "controlled microsurgery" with interactive endpinting opens the door for improved resolution in various microscopy techniques (SQUID, INSB thermography/lock-in, thermal laser stimulus) without fully exposing the die topside or by stopping a few microns before target on silicon from the backside.

Ultra tec’s ASAP-1 IPS is a digital sample preparation system for the decapsulation, thinning and polishing of packaged and wafer-level devices. The new endpoint module will be available for demos at the upcoming International Symposium for Testing and Failure Analysis (ISTFA) conference in Phoenix, AZ, Nov. 11-15).

A 4

September 4, 2012 — Wafer probe card maker FormFactor, Livermore, CA, has agreed to acquire fellow probe card supplier MicroProbe, San Jose, CA, for $100M in cash and $16.8M in stock. The deal, subject to customary conditions, is expected to close by the end of this year.

MicroProbe generated $87.3M in revenue for its fiscal 2011 (ended Dec. 31), with 46% Y/Y growth and a non-GAAP EBITDA profit margin of 20%.

The combined entity will, according to the companies, be the industry-leading supplier of advanced system-on-chip (SOC) probe cards, with technology leadership in both memory and SOC probe card markets. The entity also will see "improved and immediately accretive financial performance" by the beginning of 2013, they claim.

FormFactor was unseated as the longtime top nonmemory probe card supplier in VLSI Research rankings earlier this year; it now ranks second with $162M in 2011 sales, with Microprobe listed fourth. Combined they would rival Japan’s Micronics ($242M) which assumed the top spot. VLSI projects probe card sales will be flat in 2012 but overall growing steadily over the next five years, reaching $1.5B by 2016.

"This merger is a transformational event for FormFactor," stated FormFactor CEO Tom St. Dennis. "The combined company will have the technology and resources to address semiconductor test requirements across the entire advanced probe card space."

"This merger enables our world-class teams to accelerate innovation in wafer test across our customer base and provides compelling opportunities for our combined employees," explained Mike Slessor, CEO of MicroProbe, who will become SVP and executive officer of the combined companies.

"Together, we are in position to focus on delivering leading wafer probe solutions to meet the needs and roadmaps of logic and memory semiconductor device manufacturers," added FormFactor chairman Carl Everett.