Category Archives: Wafer Level Packaging

August 9, 2012 — Heavy monsoons moving through the Philippines are causing floods in and around Manila, the capital. Days of flooding have caused at least 19 deaths, according to CNN, and nearly 2 million people are being affected.

The Philippines is a small but growing area for microelectronics manufacturing and packaging facilities. Amkor (AMKR) has over 1.3 million square feet of manufacturing space there, and On Semiconductor (ONNN) operates 2 manufacturing campuses in the Philippines and 1 design center.

The flooding has had no effect on Amkor’s Philippines operations, said the company’s corporate communications representative, noting that some minor transportation issues were the full extent of the impact in their area.

The Philippines is also home to the Bruce Institute of Technology (BIT) microelectronics and storage system training institute for the Philippines, founded by BiTMICRO.

Already, Toshiba Group has said it will make a donation equivalent to 10 million yen to assist relief efforts in the region. Toshiba Information Equipment Philippines, Inc. (TIP), a Toshiba group company in the Philippines, is located in Laguna province, where a large number of evacuation centers have been set up. TIP has delivered about 2,000 bags of relief supplies, containing rice, canned food, water, etc., to evacuees in vicinal community.

As the results of the natural disaster become known for the microelectronics manufacturing industry, we will publish updates on specific companies

August 8, 2012 — Tektronix Component Solutions, a custom microelectronics services provider, tapped supply chain aggregator MOSIS to help its customers develop complete, high-performance ASICs with lower early-stage ASIC development costs.

They will implement multi-project wafer runs for device prototyping and package development early in the design cycle. This avoids developing a complete mask set for each ASIC prior to first silicon tape-out. Collaborating early in the design also can improve time-to-packaged-device by designing for the package, external interconnects, and performance.

Also read: ASIC design starts evolve into 3 SoC types

The partnership helps customers especially with low-volume, high-performance devices, said Tom Buzak, president of Tektronix Component Solutions, such as aerospace and defense contractors, medical OEMs, and high-speed communications developers. Tektronix Component Solutions and MOSIS are accredited Trusted Suppliers for aerospace and defense electronics.

Tektronix Component Solutions offers high-performance ASIC design on the front end and turnkey IC packaging services on the back end. Tektronix Component Solutions and MOSIS are experienced working with high-speed ASICs on silicon-germanium (SiGe) processes and other specialty semiconductors.

MOSIS is a low-cost prototyping and small-volume production service for VLSI circuit development.

Tektronix Component Solutions is a microelectronics services provider offering custom design, prototyping, manufacturing, and test services to equipment manufacturers. Tektronix Component Solutions can be found on the Web at component-solutions.tektronix.com.

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August 2, 2012 — The ConFab, Solid State Technology’s invitation-only event for the semiconductor industry, took place in June, with presenters from top companies and analyst firms. If you couldn’t be there, check out all the coverage from the event — reports, presentations, video interviews and more — via the links below.

Presentations and analysis

A virtual IDM concept can unite foundries, fabless companies, and packaging houses

The ConFab 2012 opened in Las Vegas with a keynote address from John Chen, PhD, VP of technology and foundry operations at Nvidia Corporation.

@ The ConFab: How to prevail over silicon cycles

At The ConFab’s opening session, “The Economic Outlook for the Semiconductor Industry,” capex was a major point of interest. Jackie Sturm of Intel, Dan Hutcheson of VLSIresearch, and Jim Feldhan of Semico all touched on it, with Hutcheson expanding on the idea of capex trends.

@ The ConFab: Semiconductor industry experts look to the future

The ConFab’s sessions opened with “The Economic Outlook for the Semiconductor Industry,” featuring Jackie Sturm of Intel, Dan Hutcheson of VLSIresearch, and Jim Feldhan of Semico.

 

Legacy fab issues @ The ConFab 2012

Older production facilities face equipment obsolescence; skills obsolescence; scarce availability of parts, software, and support; and equipment capability extension and tool re-use. At the ConFab 2012 Executive Roundtable, representatives from Sematech/ISMI, IDMs, OEMs, equipment dealers, and others.

 

ISMI addresses tool obsolescence

Speaking at The ConFab 2012, Sanjay Rajguru, director of ISMI, pointed out that more than half the current fab capacity today comes from facilities that are more than ten years old, which is creating a problem with equipment obsolescence.

@ The ConFab: Supply chain or supply web for 3D packaging?

With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session, “Advanced Packaging and Progress in 3D Integration,” focused heavily on this dynamic.

 

3D/2.5D packaging technologies @ The ConFab

As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue “Advanced Packaging and Progress in 3D Integration,” a session focused on the higher I/O density and other performance benefits of 3D packaging.

 

The ConFab: Chasing price, power, and performance

At The ConFab 2012, fabless companies and foundries have a common goal: reduce power, increase performance and reduce price (not necessarily in that order).

Semiconductors in the smart society: Next-generation connectivity @ The ConFab

Day 2 of The ConFab opened in Las Vegas with Ali Sebt, CEO of Renesas Electronics America, delivering “Smart Society, the Sensing Era and Signal Chain.”

 

The ConFab: Turning the technology knobs for system scaling

Chip scaling will go on for the foreseeable future, enabling new product with more compute power, more memory, faster on-chip communication. That was one of the conclusions put forth by imec’s An Steegen, speaking on technology trends at The ConFab 2012.

Big data and today’s semiconductor industry
Upon arriving at The ConFab’s venue, The Encore at The Wynn, Solid State Technology chief editor Pete Singer had an impromptu discussion about how the semiconductor industry has changed over the years, around smartphones and “big data,” with colleagues. Over 90% of the world’s data has been created in the last two years. What is big data? According to IBM, every day, we create 2.5 quintillion bytes of data.

ConFab interviews

G450 Consortium’s Tom Jefferson on 450mm timeline

Tom Jefferson, G450 Consortium, shares an update on 450mm wafers for semiconductor manufacturing. The consortium is adding staff and ramping its silicon supply, and getting ready for equipment selection.

Bill Tobey on EUV lithography

Bill Tobey, president of ACT International Consulting, speaks about the evolution of extreme ultra violet (EUV) lithography at The ConFab 2012.

Amkor’s Ron Huemoeller on 3D packaging readiness

Ron Huemoeller of Amkor presented in the Advanced Packaging session of Solid State Technology’s The ConFab. He speaks with editor-in-chief Pete Singer.

ISMI’s Bill Ross on managing legacy fabs and supply obsolescence

Bill Ross, ISMI, is moderating a session today at The ConFab 2012 on managing legacy semiconductor fabs and dealing with tool and materials obsolescence at 200mm and smaller. He speaks with Pete Singer about coping with these changes.

Ali Sebt advocates switch from On/Off to smart sensing

Ali Sebt, CEO of Renesas Electronics America, keynoted Day 2 of Solid State Technology’s The ConFab 2012. Here, he discusses the role of inexpensive sensors and microcontrollers in energy savings, in a video interview.

Dai Nippon Printing’s Naoya Hayashi on mask readiness

Naoya Hayashi, research fellow for electronic device operations at Dai Nippon Printing, speaks with Solid State Technology chief editor Pete Singer during The ConFab 2012. Hayashi presented “NGL Mask Readiness” in The ConFab’s session on technology trends.

Semico’s Jim Feldhan on SSDs and semiconductor trends

Jim Feldhan of Semico speaks with Solid State Technology editor-in-chief Pete Singer about expectations for the semiconductor industry and solid-state drives.

Nvidia’s John Chen on semiconductor industry success

John Chen of Nvidia gave the opening keynote address of The ConFab 2012, presenting the concept of a “virtual IDM” comprising fabless companies, semiconductor foundries, and packaging houses working seamlessly together.

VLSI Research’s Dan Hutcheson on silicon cycles

Dan Hutcheson, VLSI Research Inc. spoke with Solid State Technology editor-in-chief Pete Singer at The ConFab 2012. Hutcheson presented on the cyclical nature of the semiconductor industry.

Visit the ConFab’s website here.

August 1, 2012 – PRNewswire — FlipChip International (FCI), wafer-level packaging and flip chip bumping provider, named Weng Kay Lui as Asian sales director. Weng Kay Lui, based in Shanghai, will bring FCI

July 27, 2012 – BUSINESS WIRE — EMCORE Corporation (Nasdaq:EMKR), compound semiconductor-based components and subsystems supplier to fiber optic and solar power markets, will replace multiple legacy manufacturing systems in its compound semiconductor fab and back-end packaging operations with the Camstar Enterprise Platform from Camstar Systems Inc.

The enterprise management toolkit includes manufacturing execution systems (MES), quality management, statistical process control (SPC) and other management systems. EMCORE expects the Camstar product to simplify system complexities inherent in its sophisticated wafer and cell processing and assembly, test, and panel manufacturing operations. The aim is faster time to market on customized products that meet exacting requirements, as well as continuously improved operations, said Brad Clevenger, VP and GM, EMCORE. EMCORE has 7 locations globally and approximately 1000 employees.

“With Camstar we can replace a multitude of disparate applications with a single, flexible platform,” said Mike Brown, VP of Information Technology for EMCORE. “We will simplify the IT architecture and reduce support efforts, while improving our flexibility and responsiveness to change.”

EMCORE Corporation offers a broad portfolio of compound semiconductor-based products for the fiber optics and solar power markets. For further information about EMCORE, visit http://www.emcore.com.

Camstar Systems Inc. provides software solutions that advance product quality in the manufacturing industry. For more information, please visit www.camstar.com.

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July 25, 2012 — STATS ChipPAC Ltd. (SGX-ST:STATSChP), a leading semiconductor test and advanced packaging service provider, appointed Gary Tanner as a member to its Board of Directors. Tanner brings experience from Zarlink Semiconductor, Intel (INTC), Texas Instruments (TI, TXN), and other semiconductor companies.

Tanner served as director, CEO and president of Zarlink Semiconductor Inc. (2007-2011) until it was acquired by Microsemi Corporation in October 2011. Before joining Zarlink, he was VP of operations of Legerity Inc. Tanner also held various management positions during 9 years at Intel, and held fab management roles at National Semiconductor, Texas Instruments, and NCR Corporation.

STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com.

Visit the Advanced Packaging Channel of Solid State Technology, and sign up for our Advanced Packaging News e-newsletter!

July 13, 2012 — At SEMICON West 2012, this week in San Francisco, CA, the working groups of the International Technology Roadmap for Semiconductors (ITRS) held 3 sessions (TechXPOTs) outlining 2012 updates to the roadmap. Check out the updates to the front-end, scaling roadmap working groups here.

The ITRS undergoes major revisions on odd-numbered years. 2012 being an even-numbered year, very little change occurred to the Overall Roadmap Technology Characteristics (ORTC). However, within the working groups, some updates were worth noting.

Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show

First, the changes to the ORTC, presented at the TechXPOT by Bob Doering. Of interest were changes focused directly or indirectly on 450mm. ITRS has moved the forecast production start date to 2015-2016. The definition of

July 13, 2012 — SEMICON West, this week in San Francisco, CA, hosted 3 TechXPOT sessions on the International Technology Roadmap for Semiconductors (ITRS, http://www.itrs.net/) 2012 update. At the back-end technologies session, roadmapping for More than Moore was addressed as both a philosophical and technical matter.

Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show

Introducing the back-end-focused working group presentations, Bob Doering, representing the Overall Roadmap Technology Characteristics (ORTC), said that the Roadmap is not just about scaling anymore. Patrick Cogez, presenting More than Moore, picked up this thread, saying that the long-time focus on semiconductor scaling now has a partner, diversification, in More than Moore process technologies. More than Moore — encompassing advanced wafer-level and 3D packaging, micro electro mechanical systems (MEMS), and related microelectronics technologies — are harder to roadmap than CMOS technologies. Scaling semiconductor nodes has always offered the combined benefits of faster, cheaper, smaller, lower-power chips (Moore

July 12, 2012 — CEA-Leti co-located its research updates presentation with SEMICON West 2012 in San Francisco, CA, this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology’s digital media editor Meredith Courtemanche to talk about their fields of interest.

Also read: Semicon West Day 1: FDSOI and TSV R&D with CEA-Leti by blogger Michael A. Fury, PhD.

Check out the videos for details on the research:

Hughes Metras, VP of strategic partnerships in North America, presented on cost and energy consumption in large-scale computing, and what technical innovations will meet the industry’s needs. Energy efficiency must improve at the circuit, interconnect, and system level, he said.

 

Silicon photonics waveguides are one way to significantly increase bandwidth in semiconductors. CEA-Leti is migrating to a 300mm Si photonics line in its research work. Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, presented on the question of low-cost/low-power computing architectures, and the answers available in photonics.

 

Maud Vinet, LETI FDSOI Manager, IBM Alliance, shared the benefits of fully depleted silicon on insulator (FDSOI) transistor architecture. The performance? Excellent parasitic capacitance resistance because of the smaller gate length than bulk CMOS. The energy efficiency? Back bias allows tuning of the devices’ threshold voltage to reduce wasted power. (We cover energy efficiency of new transistors/interconnects in more detail here.) The manufacturing parameters? Easier than a FinFET, Vinet says, as the majority of processes are the same as today’s semiconductor fab methods. The one challenge is potential silicon loss, because planar FDSOI uses thin Si films on the order of a few nanometers.

 

Mark Scannell and Denis Dutoit both lead 3D interconnect operations at CEA-Leti, with Scannell focused on manufacturing and Dutoit on design. Unfortunately, we did not have time to interview Scannell, though his research is summarized here. The interview below is with Dutoit. Leti has both a 200mm and 300mm line for wafer-level 3D packaging research. 2.5D passive interposers and 3D active stacks are “cousins” in device packaging, and you will see both of them used for different purposes for quite some time. While both 3D and 2.5D technologies can appear in the same package, the supply/value chains for each technology are quite different.

What’s in store in this area? “Smart” interposers are being developed with integrated passives on the interposer. 3D partitioning is enabling scaling as you like it — preventing chips from being held back to a larger device node by one of the blocks involved. Also on the horizon is via-last through silicon vias (TSV), an old technology that could now come back to offer continued TSV diameter scaling past what via-middle architectures can provide. The enabling technology here is permanent bonding. Also on CEA-Leti’s agenda is direct bonding, which spreads the stress gradient over the entire copper daisy chain, unlike today’s TSVs, and has a lower contact resistance. Finally, the researchers are considering sequential or monolithic 3D to make 50nm stacked structures on a wafer.

 

Before the meeting ended, Laurent Malier, CEO of Leti, spoke with Solid State Technology about the research organization’s current goals.

 

Check out Solid State Technology’s coverage of SEMICON West 2012!