Category Archives: Wafer Level Packaging

May 3, 2012 – Marketwire — GaN Systems Inc., provider of gallium nitride power switching semiconductors, and Arkansas Power Electronics International Inc. (APEI), developer of state-of-the-art technology for power electronics systems, electronic motor drives, and power electronics packaging, will co-develop a high-temperature, high-performance package optimized for gallium nitride (GaN) transistors and diodes.

The collaboration is funded in part by the Government of Canada through Sustainable Development Technology Canada (SDTC), with the goal of demonstrating the efficiency, performance, and reliability of gallium nitride power devices in a power converter for hybrid and electric vehicles (HEVs and EVs).

Next-generation power semiconductors are adopting GaN, and prospective users want to see the technology validated through real system design implementations, said Girvan Patterson, CEO of GaN Systems. GaN Systems uses a patented, island-based topology, an emerging gallium nitride device technology. "Advanced packaging…unlocks the vast potential of gallium nitride in high-power applications.

Solid State Technology is proud to announce that David McCann will speak at The ConFab 2012. The event will be held June 3-6, 2012 at The Encore at The Wynn in Las Vegas. David McCann is Sr Director for Packaging R&D at GLOBALFOUNDRIES in Malta, New York.  In this role, Dave is responsible for Packaging R&D and back-end strategy and implementation.

David will speak on the evolution toward silicon-based interconnect and packaging, which is having profound impact on how we think about technology development and the supply chain. “Previously, companies in incremental steps of the supply chain could develop products relatively independently,” he notes in his abstract. “Now they must work together to create solutions, or fail their common customers.  Although the shortest path to market may be for the foundry to do everything in-house, the path to the best solutions that will enable competitive costs and high volume adaption will be flexible supply chains with collaborative partnering, flexibility, and transparency.”

In a session focused on advanced packaging and progress in 3D Integration, David will be joined by fellow presenters Sandeep Bharathi, vice president of engineering, Xilinx; Ron Huemoeller, senior vice president, 3DAmkor; and Bill Chen, ASE Fellow and Sr. Technical Adviser, ASE Inc. The chair of the session is Abe Yee, Dir. Adv.Technology & Package Development, Nvidia Corp.

Prior to GLOBALFOUNDRIES, David worked at Amkor Technology for 11 years, most recently leading the BGA, Flip Chip and MEMS product groups.  He was responsible for extensions of package technology, bump, applications, and business performance.  Prior to this, Dave was responsible for the fcBGA and fcCSP business group at Amkor.  He led cross-functional teams in various areas including networking product strategy, mobile product development, large die/lead free flip chip development, and wafer level product strategy.  David worked closely with Amkor factories in Asia.

Prior to Amkor, David worked at Biotronik, GmbH in Portland, OR.  Biotronik is a developer and manufacturer of implanted medical devices including defibrillators and pacemakers.  David worked at Biotronik for 9 years and had various roles in Production, Process Engineering, Product Engineering, and Flip Chip implementation.  His last role at Biotronik was leading the assembly, interconnect, and product transition from wire bond to flip chip.

David has supported the Electronic Component and Technology Conference for more than 10 years.  This year he is Conference General Chair.

April 24, 2012 – BUSINESS WIRE — Toshiba Corporation (TOKYO: 6502) will rebuild its semiconductor manufacturing operations in Thailand by relocating Toshiba Semiconductor Thailand Co., Ltd. (TST) to a new manufacturing facility. The move will position the company to meet future growth in demand and replace the factory inundated by the 2011 floods.

Established in 1990, TST carries out back-end processes — assembly and packaging — for small signal devices and photocouplers. Small signal devices control current and voltage in digital consumer products, a product segment that is expected to grow in coming years, with a primary focus on smart phones and tablets PCs. Photocouplers are used widely in industrial products, such as inverters, and are also expected to see strong demand growth.

The new facility will be located at the 304 Industrial Park, Prachinburi, approximately 140km northeast of Bangkok and will replace TST’s facilities at Bangkadi Industrial Park in Pathumthani, in the suburbs immediately north of Bangkok. The new site is at 15 to 20 meters above sea level and outside Thailand’s main drainage basins, with no major rivers, so it offers TST advantages in the viewpoint of business continuity planning (BCP). Construction of a 2-story building will begin in July on a lot with an area of approximately 135,000 square meters, 1.4 times the size of the Bangkadi lot.

Construction of the state-of-the-art factory will allow TST and Toshiba Group to respond flexibly to market demand with facilities offering greater operating efficiency and higher productivity. The plant is scheduled for completion next spring and mass production is slated to start in the second quarter (April-June) of 2013.

The initial investment of the facility including the cost of the construction will be largely met by flood insurance settlements and is not expected to impact on the results of Toshiba’s semiconductor business. Future investment and production expansion will be flexibly determined in light of market trends and customer needs.

Last year’s flooding completely inundated TST’s manufacturing facilities, resulting in a forced suspension of operations. As TST made every effort to recover operations, Toshiba responded with a BCP based on transferring operations to its production facilities in Japan and Malaysia and making use of outsourcing.

Toshiba Group is promoting a revitalization of its discrete device business aimed at boosting efficiency and profitability. Measures deployed to date include transitioning to larger wafers and higher output in the front-end process, and accelerating the overseas transfer of the back-end process. Construction of the new TST facility will improve cost competitiveness in the back-end process, strengthen the bottom line and contribute to the overall strength of the discrete business unit.

Outline of Toshiba Semiconductor (Thailand) Co., Ltd.

Location:

 

Pathumthani prefecture, Thailand

Established:

 

October 1990

Representative:

 

Yasuo Ashizawa, President

Employees:

 

Approx 1,400

Capital:

 

1,215 million Thai Baht

Production item:

 

Discrete semiconductors (small signal devices, photocouplers)

 

 

 

Outline of new factory

Location:

 

Prachinburi prefecture, Thailand

Site Area:

 

Approx 135,000m2

Floor area:

 

Approx 40,000m2

Groundbreaking:

 

July 2012 (scheduled)

Building completion:

 

Spring 2013 (scheduled)

Mass-production start:

 

2nd quarter, calendar year of 2013 (scheduled)

Learn more at http://www.toshiba.co.jp

Visit the Semiconductors Channel of Solid State Technology!

April 23, 2012 – Marketwire — Semiconductor packaging service provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) appointed Pasquale Pistorio as a member of the Board of Directors, effective immediately, at its annual general meeting. Pistorio joined as an advisor to STATS ChipPAC’s board last year.

Pistorio is known throughout the semiconductor industry for his role in the creation of STMicroelectronics (ST). He was president and CEO at SGS Microelectronica from 1980 to 1987. In May 1987, he led the formation of ST, integrating SGS Microelectronica with Thomson Semiconducteurs. He became president and CEO of the new company, serving through 2005. Pistorio has been Honorary Chairman of the STMicroelectronics group of companies since 2005. He has more than 39 years of experience in the semiconductor industry.

Pistorio has received honorary degrees from the University of Genova, the University of Malta, the University of Pavia, the University of Catania, the University of Palermo, and the University of Sannio, Benevento. He holds an Electronics degree in Electrical Engineering from the Polytechnic of Turin.

Pistorio

April 19, 2012 — Pure-play MEMS foundry Silex Microsystems brought its Met-Via full-wafer-thickness through silicon via (TSV) technology into Chip Architectures by Joint Associated Labs for European Diagnostics (CAJAL4EU), where it is being used to create cost-effective molded chip-level packaging with through metal vias (TMV).

Figure 1. Cross section of final product, showing Biosensor from NXP (Netherlands), TSV interposers from Silex, and epoxy mold to be performed by Frauenhofer (Germany) and gold (Au) bumping by Pactec (Germany). Frontside RDL to be processed by Bosch (Germany), and backside RDL to be processed by Frauenhofer (Germany).

The program is developing nanoelectronics-based biosensor technology platforms for in-vitro diagnostic test manufacturers to rapidly build various new multi-parameter test applications cost-effectively. CAJAL4EU will develop a generalized platform for low cost biofluidic sensing. Biosensing allows for rapid detection of unique biological markers (proteins, antibodies, and other biomarkers for infectious diseases) from microliter fluid samples in an extremely controlled environment. The biosensors will consist of a nanoelectronics-based transducer with an interface chemistry, which makes the connection to the clinical sample to be analyzed. With on-chip detection electronics, small electrical changes can be detected within milliseconds, enabling massively parallel real-time monitoring of bio-molecule binding events. Besides the transducers, interface chemistry and spotting technologies, microfluidics, software and hardware developments (and their integration) will play a crucial role to realize fully integrated biosensor systems and lab-on-chip devices. Therefore, the main deliverables of this project are the different developed technologies: sensor technology including bio-chemical functionalization, microfluidics and related hardware and software drivers.

Figure 2. Actual TSV interposer die from Silex.

Silex

The 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2012) will be held May 15-17 in Saratoga Springs, New York. The conference will feature presentations of more than 85 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features a panel discussion on “Competing for R&D Dollars,” moderated by Solid State Technology Editor-in-Chief Pete Singer, and 15 technical sessions on advanced semiconductor manufacturing, as well as a tutorial on Advanced Device Design offered by IBM Research.

For over 20 years, ASMC has provided a premier venue for industry professionals to learn and share knowledge on new and “best practice” semiconductor manufacturing issues and concepts.  ASMC provides a valuable source of cost-effective, hands-on solutions to address real-world manufacturing challenges. It is acknowledged as a leading technical conference that enables collaboration and sharing of technical breakthroughs. This year’s conference features keynotes delivered by industry leaders, including: Michael Campbell, senior vice president, Engineering, Qualcomm, and Andrea Lati, principal analyst, VLSI Research.

As advances in materials and process technology continue, the semiconductor manufacturing industry is faced with difficult challenges as it balances costs and critical technology issues. Limited R&D dollars is the reality, and it is unclear how wafer size transition, next node scaling, new transistor technology, 450mm EUV, and 3D-IC will be funded. To address this issue, ASMC offers a panel discussion this year on “Competing for R&D Dollars: Funding the Future” with panelists from Applied Materials, ASML, GLOBALFOUNDRIES and IBM addressing 450mm, EUV and 3D.  

ASMC 2012 sessions include:

  • Factory Optimization: Semiconductor equipment and manufacturing are increasingly complex with strict economic constraints. The sessions discuss novel solutions to improve equipment/factory productivity and performance.
  • Advanced Metrology: Advanced semiconductor manufacturing demands advanced metrology techniques. This session details new technologies and improvements.
  • 3D/Through Silicon Via (TSV): Very Large Scale Integration motivates 3D integrated circuit architectures. This session presents complexities of TSV techniques supporting 3D designs.
  • Equipment, Materials & Processes: Advanced memory and logic manufacturers face daunting challenges as the next generation device nodes come on line. Innovations in equipment, materials, and processes help meet those challenges.  
  • Emerging Technologies and Innovative Devices: Innovative integrated circuit functionalities continue to be integrated in semiconductor manufacturing. This session presents analysis of the effects of enabling technologies, and innovative integrated circuit designs.
  • Equipment and Materials Productivity: Optimizing equipment and performance will help improve fab metrics, minimize wafer costs and maximize competitiveness— how to help optimize equipment utilization, improve predictive modeling of fab operations, and tool performance.
  • Advanced Patterning and Design for Manufacturability: IC production today requires innovative lithography design and manufacturing techniques, including collaborative efforts between chip makers and equipment suppliers discussing leading-edge solutions
  • Process Development and Control: The demand for high quality and product yields is a constant driver for advanced process development and control techniques. Session covers improvements in processes, tool controls and predictive process performance analysis.
  • Defect Inspection and Yield Optimization: Defect inspection, yield analysis and optimization are integral components in the development and manufacture of semiconductor devices

ASMC also holds an interactive poster session and reception, which provides an ideal opportunity for networking between authors and conference attendees. During this session, participants can engage authors in in-depth discussion of a wide range of issues.

ASMC 2012 is presented by SEMI with technical sponsors: Institute of Electrical & Electronics Engineers (IEEE), IEEE Electron Devices Society (EDS), and IEEE Components, Packaging and Manufacturing Technology Society (CPMT).  Corporate sponsors include: Applied Materials, ATMI, ChemTrace, CNW Courier Network, Edwards, KLA-Tencor, Mentor Graphics, Nikon, NY Loves Nanotech, and Valqua. Additional sponsors include: Saratoga Convention & Tourism Bureau, Saratoga Economic Development Corporation, and the city of Saratoga Springs, New York.

April 16, 2012 — Semiconductor assembly and test services (SATS) provider ChipMOS TECHNOLOGIES (Bermuda) LTD. (NASDAQ:IMOS), via its majority-owned subsidiary, ChipMOS TECHNOLOGIES INC. (ChipMOS Taiwan), purchased a 393,173sq.ft. building adjacent to its existing facility in Southern Taiwan Science Park.

ChipMOS Taiwan won a public court bidding process for the building, at a purchase price of approximately US$10.1 million. The location — across the street from ChipMOS Taiwan

April 16, 2012 – PRNewswire — Highly secretive wafer level chip scale packaging (WLCSP) start-up Deca Technologies might take over SunPower Corp. (NASDAQ:SPWR) Fab 1, when the solar photovoltaics (PV) supplier consolidates its Philippine manufacturing operations to Fab 2 this quarter.

SunPower invested an undisclosed amount of capital in Deca when the packaging house launched, and is a minority shareholder. It gave Deca half of its fab space in Laguna Technopark, Philippines to use, as well as human resources, and process/operational know-how. Deca is also funded by Cypress Semiconductor. Read about Deca Technologies’ launch here.

Sunpower has 2 lines running on its new process for Maxeon Gen E cells, and expects to have all 12 lines at Fab 2 converted by the end of 2012, said Tom Werner, SunPower president and CEO. He added that repurposing Fab 1 enables SPWR to rationalize operating expenses, improve supply chain efficiency, and lower manufacturing cost per watt. Yields and efficiency will be improved at Fabs 2 and 3 in conjunction with the move.

SunPower is working with Deca Technologies and others on the use of the Fab 1 facility. Employees at Fab 1 will be transferred to Fab 2 or have the opportunity to work for potential Fab 1 tenants. SunPower will transfer some equipment from Fab 1 to Fab 2 to reduce manufacturing constraints.

SunPower expects to record pre-tax GAAP charges in restructuring totaling $51 million to $69 million, primarily non-cash asset impairment charges of $40 million to $54 million, and other cash-based associated costs of $11 million to $15 million, for the closure of Fab 1.  Of the pre-tax GAAP charges totaling $51 million to $69 million, $47 million to $63 million will likely be recorded in the second quarter of fiscal 2012 and the remainder in ensuing quarters.

SunPower Corp. (NASDAQ:SPWR) designs, manufactures and delivers high-efficiency, high-reliability solar panels and systems. For more information, visit www.SunPowercorp.com.

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