Category Archives: Wafer Level Packaging

September 16, 2011 — The Burn-in & Test Socket Workshop (BiTS Workshop) will change its name to The Burn-in & Test Strategies Workshop to reflect the "evolution of packaged ICs," announced Fred Taber, general chairman of the workshop.

The 2012 BiTS Workshop takes place March 4-7, 2012, in Mesa, AZ.

The event will cover next-generation solutions to burn-in and test while still gathering new work on traditional technologies, Taber continued. The BiTS Workshop is not deviating from its mission to present relevant work on "burn-in and test tooling for today’s IC package technologies," said Taber. It is now expanding to cover "what’s next."

Burn-in and test have changed along with the emergence and market adoption of advanced packaging technologies, including wafer-level packaging (WLP) and fan-out WLP, system in package (SiP), wafer-level test of chip scale packages (CSP), embedded die packages, flip chip packages, package-on-package (PoP), and other 3D packaging.

For more information about the BiTS Workshop, visit www.bitsworkshop.org.

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September 15, 2011 — Citing increased semiconductor industry demand, Honeywell (NYSE:HON) Electronic Materials will more than double refining and casting capacity for high-purity copper (Cu) and tin (Sn) at its Spokane, WA, facility.

Demand is growing for both mature and leading-edge semiconductor sectors. Honeywell notes multiple semiconductor industry trends that require higher copper and tin quantities: Advanced chip designs use more high-purity copper; memory manufacturers are transitioning from aluminum (Al) to copper; and copper and tin use in advanced chip packaging applications is increasing. Cu offers lower resistivity than Al, increasing chip speeds. It also costs less than gold (Au) for semiconductor packaging materials. Tin is a lead alternative for chip package soldering, boosted by multiple anti-lead regulations globally, such as EU RoHS.

Honeywell is "making supply chain and technology investments" to meet this need, said Mike Norton, product line director for Honeywell Electronic Materials’ Advanced Metals business. Phase one of the capacity expansion will be ready in Q1 2012; phase two will be complete around the middle of 2012. Honeywell is vertically integrated in the production of source materials, with a supply of metals designed specifically for use in the semiconductor industry.

Honeywell supplies metals to the semiconductor industry, manufacturing high-purity physical vapor deposition (PVD)/sputtering targets and advanced packaging materials for electrical interconnect. Honeywell also supplies a range of materials to the semiconductor industry, including electronic polymers, precision thermocouples and electronic chemicals. Honeywell International is a Fortune 100 diversified technology and manufacturing company. Honeywell’s shares are traded on the New York, London, and Chicago Stock Exchanges. For more news and information on Honeywell, please visit www.honeywellnow.com.

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September 14, 2011 — Infrared materials and systems supplier IRphotonics added a high-resolution FLIR thermal imaging camera to its application engineering lab. The camera will be used to analyze heat distribution during iCure use.

IRphotonics engineers hope to optimize energy, wavelength and irradiance for particular processes, developing customized curing profiles with better control and manufacturing productivity, said Ruben Burga, VP of sales for IRphotonics.

The iCure AS200 inline fiber optic spot cure system uses infrared radiation to heat-cure thermal epoxies, bond plastic and glass components such as lenses, affix miniature components, assemble and bond semiconductor components, microsolder, and perform other precise welding operations. The system suits use with temperature-sensitive substrates and complex devices.

IRphotonics will be demonstrating the iCure AS200 at booth 765 at the MD&M Midwest in Chicago, September 20-23, 2011.

IRphotonics designs and manufactures infrared fibers and systems for the transmission of infrared light, and for assembly operations requiring high intensity infrared heat. For more information, visit www.icure-irphotonics.com.

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September 12, 2011 — Inspection equipment provider Rudolph Technologies Inc. (NASDAQ:RTEC) shipped the 1000th NSX Inspection System from its Bloomington, MN manufacturing facility. The NSX inspects wafer bumps, wafer-level packages (WLP), micro electro mechanical systems (MEMS) devices, and more.

The first 100 NSX systems were sold between 1997 and 2000 by August Technology Corporation (acquired by Rudolph in 2006). Doug Larsen, mechanical engineer on the original NSX-80 and current Rudolph employee, says that the automated macro inspection systems had to perform to meet customer expectations, and move from purchase order to installation on-time.

Each new NSX model for complex semiconductor back-end processes targets reduced cost of ownership (COO) and better production yields. The design was adjusted to inspect WLP, microbumps, MEMS, and LED wafers. Over 150 NSX Systems perform probe mark inspection (PMI), and more than that are inspecting bumps. Other applications include 100% inspection for automotive semiconductor makers.

The NSX 320 debuted with its first order in June 2011, optimized for advanced packaging processes that use through silicon vias (TSV) for 3D packaging.

Rudolph Technologies Inc. designs, develops, manufactures and supports defect inspection, process control metrology, and data analysis systems and software used by semiconductor device manufacturers. Additional information can be found on the company’s website at www.rudolphtech.com.

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September 8, 2011 – BUSINESS WIRE — Invensas Corporation, a Tessera Technologies Inc. (Nasdaq:TSRA) wholly owned subsidiary, will demonstrate dual-face down (DFD) implementation of its new multi-die face-down (xFD) semiconductor packaging technology at the Intel Developer’s Forum this month.

The multi-die package is wire bonded, mounting ICs upside down and staggering them in a shingle-like configuration. The short wire bonds required resemble those of a window-BGA package. The design creates 25-35% vertical form factor savings from conventional packages. Speed-bin yield increases 50-70% thanks to the symmetric top and bottom die performance. Thermal management is improved with 20-30% better heat dissipation than conventional dual-die packages (DDPs), according to the company.

Invensas XFD is a "market-ready" packaging technology that can be performed on existing wire-bond lines. A parallel process packaging flow reduces manufacturing costs for the multi-die DRAM packages, specifically reducing materials usage, including gold.

The packages improve DRAM/memory capacity and performance, targeting data center servers, tablets/smartphones, and other applications. Simon McElrea, president of Invensas Corporation, touts "single-die package performance in a multi-die configuration" with density and cost advantages.

Invensas will demonstrate its DFD technology at the Intel Developers Conference in San Francisco’s Moscone Center, West Hall, Booth #414, September 13-15, 2011.

Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc. (Nasdaq: TSRA), acquires, develops and monetizes strategic intellectual property (IP) in areas such as circuitry design, 3D systems, memory modules and other enabling technologies. Go to www.invensas.com.

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September 7, 2011 – 3M and IBM say they are jointly developing a new class of material adhesives specifically for stacking and packaging semiconductors in layers of up to 100 separate chips. The resulting silicon "brick" could make chips 1000

August 31, 2011 — Amkor Technology Inc.’s (NASDAQ:AMKR) Board of Directors authorized the repurchase of up to $150 million of AMKR common stock, to enhance stockholder value and support its business model, said Ken Joyce, Amkor president and CEO.

Amkor reported cash and cash equivalents of about $475 million as of June 30, 2011.

Details: The purchase of stock under this program may be made in the open market or through privately negotiated transactions. The timing, manner, price and amount of any repurchases will be determined by Amkor at its discretion and will depend upon a variety of factors including economic and market conditions, price, applicable legal requirements and other factors. The stock repurchase program will be funded with available cash and may be suspended or discontinued at any time.

Also read: GLOBALFOUNDRIES, Amkor co-develop semiconductor assembly and test methods and Amkor expands package design kit for Agilent ADS

Amkor is a semiconductor assembly and test services (SATS) provider to semiconductor companies and electronics OEMs. Learn more at www.amkor.com.

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August 29, 2011 — Gold wires are used in electronic devices due to the material’s flexiblity and conductive quality. At the nanoscale, however, gold wires (<20nm wide) become "brittle-like" under stress, according to a new study at Rice University.

Rice materials scientist Jun Lou and his team studied nanowires under strain conditions expected to be found in flexible electronics and other nanoelectronics. The study could be performed on gold, silver, tellurium, palladium, and platinum nanowires.

Researchers expected the wires to undergo extensive plastic deformation and fracture under stress, a condition called "necking" where nanowires deform in a specific region and stretch to a point before they eventually break. Gold’s ductility allows it to withstand very large displacement, but at the nanoscale, it forms "twin" defects, said Lou, an assistant professor of mechanical engineering and materials science. These differ from normal necking defects.

Figure 1. A single crystal nanowire shows twinning under tensile loading. SOURCE: Lou Lab, Rice University.

"Twin" defects have a mirrorlike atomic structure unique to crystals. Atoms to the left and right of the defect boundary "exactly mirror each other," Lou said. The twinning was visible asdark lines across the nanowire observed with an electron microscope.

Gold nanowires are "brittle-like" because ductility is reduced but not eliminated, and the fracture differs from typical necking, he said.

Figure 2. A series of electron microscope images showing a gold nanowire with several twin boundaries (dark lines). The wire fractures at the site of a groove that appears at the bottom twin. SOURCE: Lou Lab, Rice University.

Rice tested 22 gold wires less than 20nm wide, clamping them to a transmission electron microscope/atomic force microscope (TEM/AFM) sample holder and pulling the wires at constant loading speeds. Twins appeared under stress, which forced atoms to shift at the location of surface defects. The "damage-initiation sites" reduce ductility and cause premature fractures, Lou said, which was an unexpected degree of defect.

With current technology, it’s nearly impossible to align the grip points on either side of the wire, so shear force on the nanowires was inevitable. "But this kind of loading mode will inevitably be encountered in the real world," he said. "We cannot imagine all the nanowires in an application will be stressed in a perfectly uniaxial way."

Results are published in the journal Advanced Functional Materials. Read the abstract at http://onlinelibrary.wiley.com/doi/10.1002/adfm.201101224/abstract

Lou’s team included former Rice graduate student and the paper’s first author, Yang Lu, now a postdoctoral researcher at MIT. Jun Song, an assistant professor at McGill University, and Jian Yu Huang, a scientist at Sandia National Laboratories, are co-authors of the paper.

The Air Force Office of Sponsored Research, National Science Foundation and Department of Energy supported the research.

Rice University operates schools of Architecture, Business, Continuing Studies, Engineering, Humanities, Music, Natural Sciences and Social Sciences and is known for its "unconventional wisdom."

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August 29, 2011 — Foundry GLOBALFOUNDRIES entered into a strategic partnership with packaging house Amkor Technology Inc. (NASDAQ:AMKR) to develop integrated semiconductor assembly and test processes for advanced silicon nodes. The aim is integrated fabbumpprobeassemblytest steps that can be commercialized across multiple customers and end-market applications.

Amkor is becoming a founding member of GLOBALFOUNDRIES’ Global Alliance for Advanced Assembly Solutions, formed to foster semiconductor interconnect, assembly and packaging technology innovation.

The integration of interconnect, assembly and packaging at advanced semiconductor nodes makes supply chain management more critical, as chip designers can exploit packaging technologies as part of the silicon development. 3D IC stacking is also an alternative to traditional technology node scaling at the transistor level. Chip-package interaction is becoming more complex. This was the topic of "Collaboration to Strengthen the IC Supply Chain," held at The ConFab 2011, in which Amkor and GlobalFoundries gave presentations. Read summaries from the talk in More Moore & More than Moore require fabless, foundry, and packaging houses on board.

The companies also recently expanded their lead-free wafer bump licensing relationship by amending their existing lead-free bumping technology license agreement.

The joint development effort on advanced packaging will target lower costs, faster time-to-volume, and reduced technical risks, said Gregg Bartlett, senior vice president of technology and research and development at GLOBALFOUNDRIES. Dr. Robert Darveaux, Amkor’s corporate vice president, technology and platform development, noted the value of major packaging and foundry companies working together, serving "our common customers."

GLOBALFOUNDRIES is a full-service semiconductor foundry with a global manufacturing and technology footprint. For more information, visit http://www.globalfoundries.com.

Amkor is a leading provider of semiconductor assembly and test services to semiconductor companies and electronics OEMs. More information at www.amkor.com.

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