Category Archives: Wafer Level Packaging

August 4, 2011 — Apple Inc.’s iPad has thus far thwarted competitive tablets in design efficiency, according to an IHS iSuppli Teardown Analysis of eight tablet models from IHS (NYSE: IHS). Major savings come from Apple’s control of chips like SDRAM and applications processors.

Apple is a vertically integrated manufacturer, creating much of the hardware and software in the iPad, points out Wayne Lam, senior analyst, competitive analysis, at IHS. Apple uses its own applications processor design in the iPad and iPad 2, Lam notes, while other tablets have processors sourced from Nvidia, Texas Instruments and Qualcomm.     

Apple has limited the memory in the iPad 2, with only 512 megabytes (competitive designs use 1 gigabyte) of synchronous dynamic random access memory (SDRAM). This cuts nearly $14 from the iPad bill of materials (BOM) compared to the competition. Because Apple controls the hardware and software of the iPad, it can structure the operating system to use less memory.

Similiarly, the iPad battery is the thinnest of all competing tablet designs, yet has the largest capacity.

The table below presents an overview of the results of the dissection of eight tablet models. Note that the BOM figures accounts only for hardware and manufacturing costs and do not take into consideration other expenses such as software, licensing, royalties or other costs.

Table. Teardown comparison of 8 tablet models (BOM and summary of major components). SOURCE: IHS iSuppli 2011.
  Apple iPad (WiFi) Apple iPad (WiFi + 3G) Samsung Galaxy Tab Motorola XOOM* Apple iPad2 (WiFi + 3G) RIM Blackberry Playbook Asus Eee Pad HP TouchPad
Release
 April 2010 April 2010 Sept. 2010 Feb. 2011 March 2011 April 2011 May 2011 July 2011
OS iOS 3.x iOS 3.x Android 2.x Android 3.x iOS 4.x QNX Android 3.x WebOS 3.x
Screen/
Display		 9.7 Inch IPS Display w/ Capacitive Multitouch Overlay 9.7 Inch IPS Display w/ Capacitive Multitouch Overlay 7 Inch TFT Display w/ Capacitive Multitouch Overlay 10.1 Inch TFT Display w/ Capacitive Multitouch Overlay 9.7 Inch IPS Display w/ Capacitive Multitouch Overlay 7 Inch TFT Display w/ Capacitive Multitouch Overlay 10.1 Inch IPS Display w/ Capacitive Multitouch Overlay 9.7 Inch IPS Display w/ Capacitive Multitouch Overlay
Apps
Processor		 Apple A4
(Single Core)		 Apple A4
(Single Core)		 Samsung S5PC110 (Single Core) Nvidia Tegra2
(Dual Core)		 Apple A5
(Dual Core)		 TI OMAP 4
(Dual Core)		 Nvidia Tegra2
(Dual Core)		 Qualcomm APQ8060 (Dual Core)
Memory (SDRAM) 256MB DDR 256MB DDR 512MB DDR 1GB DDR2 512MB DDR2 1GB DDR2 1GB DDR2 1GB DDR2
Storage (NAND) 16GB 16GB 16GB 16GB* 16GB 16GB 16GB 16GB
Camera
(1st/2nd)		 N/A N/A 3MP/1.3MP 5MP/2MP 1MP/VGA 5MP/3MP 5MP/1.2MP 1.3MP
3G Modem N/A Infineon (HSPA) Infineon (HSPA) Qualcomm (EVDO) Infineon (HSPA) / Qualcomm (EVDO) N/A N/A N/A
Battery 6600mAh / 3.75V Dual Cells 6600mAh / 3.75V Dual Cells 4000mAh / 3.7V Single Cell 3250mAh / 7.4V Dual Cells 6930mAh / 3.75V Dual Cells 5400mAh / 3.7V Dual Cells 3300mAh / 7.4V Dual Cells 6000mAh / 3.7V Dual Cells
Sensors eCompass and Accelerometer GPS, eCompass and Accelerometer GPS, eCompass and Accelerometer GPS, eCompass, Accelerometer, Gyro and Pressure GPS, eCompass, Accelerometer and Gyro eCompass, Accelerometer and Gryo GPS, eCompass, Accelerometer and Gyro Accelerometer and Gyro
BOM Cost $268 $320 $262 $330 (w/o LTE module) $310 (HSPA) $271 $284 $318
Retail Price $499 $629 $749 N/A* $629 $499 $399 $499
*Motorla XOOM only comes in 32GB which retails for $799.  We’ve normalized capacity for purpose of this comparitive exercise.
Source: IHS iSuppli Research, Aug 2011

The IHS iSuppli Teardown Analysis Service also illustrates the trend toward multi-core processors in tablet designs, price points, and display sizes. Following the introduction of the Motorola Xoom in February and the iPad 2 in March, all new tablet designs within 2011 have included dual-core processors that deliver higher computing and graphical performance. In 2012 IHS expects to see this trend to continue with the introduction of tablets featuring quad-core processors for even more enhanced performance.

Learn more about this topic with IHS iSuppli Teardown Analysis Service at http://www.isuppli.com/Teardowns/Pages/Products.aspx.

Also read: Apple’s A5 Processor is by Samsung, not TSMC

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August 3, 2011 — Great Lakes Engineering signed an agreement with DEK, enabling it to supply DEK’s VectorGuard interchangeable foil-frame stencil systems.

VectorGuard interchangeable foil stencil system is used by semiconductor packaging and surface mount technology assemblers to print materials.

The stencil technology is able to maintain tension over time, without an air bladder, noted John Carr, director of sales for Great Lakes Engineering. The extruded aluminum edges of each foil protect operators and enable easy assembly.  When VectorGuard foils are stored in their protective cassettes, storage space can be reduced by as much as 75% as compared to traditional stencils.

Allowing other stencil manufacturers to carry the stencil technology with their product lines simplifies supply chains for users, added DEK’s PSP Global Operations Manager, David Byrd. Great Lakes has customers in 32 states and three countries.

DEK is a global provider of advanced materials deposition technologies and support offerings. To find out more about DEK

August 3, 2011 – BUSINESS WIRE — Agilent Technologies Inc. (NYSE:A) and the University of California, Davis (UC Davis) established the Davis Millimeter Wave Research Center to develop advanced mm wave and THz systems for radar, sensors, imaging systems, communications and integrated passive devices (IPDs) found in electromagnetic metamaterials and antennae.

DMRC students and faculty will research devices, integrated circuits (ICs), packaging, metamaterials and defected ground integrated passives, imaging systems, THz vacuum electronics, THz micro-machined devices, nonlinear modeling, nanomaterials and wireless implantable devices. Agilent and UC Davis expect results that benefit medical imaging systems, security scanners, gigabit wireless communications devices and sensors, as well as defense usages such as radar and active denial systems.

The Davis Millimeter Wave Research Center is an industry-university cooperative research program with national and international aims.

Agilent is helping establish a core test facility with measurement capabilities that include Agilent nonlinear vector network and spectrum analysis test equipment up to 325 GHz. These facilities will support gigabit wireless communications at 60 and 80GHz, as well as the imaging, radar and active denial systems to 325GHz.

UC Davis has more than 32,000 students, more than 2,500 faculty and more than 21,000 staff, an annual research budget that exceeds $678 million, a comprehensive health system and 13 specialized research centers.

Agilent Technologies Inc. (NYSE: A) provides measurement tools for chemical analysis, life sciences, electronics and communications. Information about Agilent is available at www.agilent.com.

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August 2, 2011 – Marketwire — Data I/O Corporation (NASDAQ:DAIO), manual and automated device programming product provider, debuted the RoadRunner3 in-line programming system, a just-prior-to-placement programming tool. Its Factory Integration Software (FIS) helps RoadRunner3 streamline production and eliminate operator errors by interfacing with the user’s manufacturing execution system (MES) or other shop-floor control software.

The programming system’s feeder mounts directly onto an SMT placement machine, removing unprogrammed Flash memory devices from tape, programming four devices in parallel, and then delivering the programmed parts to the pick-up point of the placement machine. Interface kits match major SMT equipment: SIPLACE, Fuji, Panasonic, and MYDATA. A configurable Tape-In module adjusts for tape widths from 16 to 44mm.

FIS Remote and FIS Track modules allow customers to manage and monitor the programming process. The FIS Remote software module automates job selection and job downloads to RoadRunner3. FIS Track enables data-driven decision making through automated collection and export of programming results. The modules send e-mail alerts when RoadRunner3 needs maintenance or when yields drop below a set threshold.

RoadRunner3 features a FlashCORE III Flash programming architecture for memories such as e.MMC, SD and NAND Flash.

Data I/O Corporation manufactures, distributes, and services products for programmable devices in any package, whether programmed in a socket or on a circuit board. For further information, visit www.dataio.com.

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August 1, 2011 – BUSINESS WIRE — SATS provider Unisem purchased a LTX-Credence PAx RF Test System for its Sunnyvale, CA, test development center. The system includes the full feature set LTX-Credence offers for development and production test of front-end RF semiconductor devices.

The PAx system is designed to meet high-volume manufacturing test needs of advanced front-end RF devices: Multiband RF power amplifiers, RF analog system in package (SiP), RF front-end modules, and RF discrete devices. The X-Series XRF test instrumentation enables performance tests under WLAN, GSM, WiMAX, Edge CDMA, LTE, Bluetooth, WCDMA, or other RF signaling standards.

"Higher levels of functionality, high unit volume growth and constant pricing pressures" are driving the RF sector, said John Shelley, product director, LTX-Credence, explaining the aims of the PAx tester.

Unisem’s goal is to build up its Sunnyvale test center to be the leader in its test equipment roadmap, added Marita Erickson, general manager, Unisem-Sunnyvale. In March, Unisem added an Accretech wafer prober for 12" wafers at Sunnyvale. Earlier this month, Unisem added a Teradyne J750Ex for consumer digital testing. Customers work with Unisem at Sunnyvale to optimize test programs and scale up test routines to volume for transfer to Asia.

LTX-Credence provides ATE products for semiconductor test in wireless, computing, automotive and entertainment market segments. Additional information can be found at www.ltxc.com.

Unisem is a global provider of semiconductor assembly and test services (SATS), offering wafer bumping, wafer probing, wafer grinding, a wide range of leadframe and substrate IC packaging, wafer level CSP and RF, analog, digital and mixed-signal test services. Learn more at www.unisemgroup.com.

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July 28, 2011 — Texas Instruments Incorporated (TI, NYSE:TXN) has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.

In PowerStack, TI’s NexFET power MOSFETs are stacked on a grounded leadframe. Copper clip bonds connect the I/O voltage pins. The packaging technology enables heightened integration in a quad flat-pack no-lead (QFN) form factor. This 3D packaging cuts down on package area by as much as 50% (compared to side-by-side MOSFETs). The package’s thermal performance, current carrying capability, and effeciency are supported by this design.

PowerStack is in volume production at TI’s Clark facility, which is the company’s newest semiconductor assembly and test facility (Philippines). TI will expand capacity for advanced packaging at Clark in 2011, "nearly doubling initial capacity," added Bing Viera, managing director of TI Philippines.

The company is targeting PowerStack for computing and telecommunications applications that must handle higher loads, from "broadband mobile video and 4G communications…and take up less space," said Matt Romig, analog packaging at TI.

Texas Instruments makes semiconductors. Learn more at www.ti.com.

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July 26, 2011 — 3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.



Berry spoke to ElectroIQ in a podcast interview at SEMICON West 2011 this month in San Francisco, CA.

"People who are receiving wafers need something they can benchmark," said Berry. Towards the end of the through silicon via (TSV) process, "if you take too much silicon off the wafer, you going to take the dies with it…and if you take too much silicon off the wafer, you’ll expose the circuitry." Metrology has to play a role in controlling wafer processing to achieve yields that make 3D ICs cost-competitive, he said.  

Another concern with 3D semiconductors is that the end user already has placed a lot of value in the wafers by the time TSVs are formed, noted Berry. Because the transistors have already been made, if the relatively simple and inexpensive 3D packaging process fails, then end users are writing off a lot of product. "But you don’t want to spend a lot of money in putting the metrology into place to get it right," so the key thing is "a balance between managing the process, understanding how the process flows, measuring at the right points so you know where the failure events will be so you can select them and control them, but not overdoing the metrology," Berry concludes.

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July 22, 2011 — Materials supplier Nippon Steel Material Co. Ltd. (NSMAT) and its semiconductor packaging materials subsidiary Nippon Micrometal Corporation (NMC) licensed their single-layer-palladium (Pd) coated copper (Cu) bonding wire to Tanaka Denshi Kogyo K.K., bonding wire manufacturer and traditionally a competitor.

The copper bonding wire, EX1, was developed by Nippon Steel Corporation as an alternative to gold in high-density large-scale integrated (LSI) circuits. The companies report that the wire bonds offer high reliability at one-fifth the cost of gold packaging, thanks to a unique structural design. It also offers high electrical conductivity, more than 20% higher than gold wire.
 
EX1 went into mass production in 2009 and claims more than 80% of the copper bonding wire market share. It has been adopted by packaging companies globally, with a large presence in Taiwan.

Nippon Steel has filed more than 80 patents on copper wire for semiconductor packaging. Several of the EX1 patents are now being licensed to Tanaka, a competitor, to ensure consistent global supply of the material, says Nippon Steel. NMC additionally increased production of the wire in its Japan and Phillipines facilities, upping output from 150k to 250k km/month.

The company also released an improved Pd monolayer Cu wire, EX1p, that enhances bonding to the die and leadframe, and allows increased wire-bonding speed. EX1p is not included in the license agreement with Tanaka Denshi Kogyo.

Learn more at http://www.nsc.co.jp/nsmat/english/index.html

More on copper wire bonding:

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July 21, 2011 — Inari Berhad, contract semiconductor packaging and test house, was listed on the ACE Market of the Bursa Malaysia Securities Berhad (Bursa Malaysia) on July 19, 2011, Stock Code: 0166, in an initial public offering (IPO) that was oversubscribed by 10.42 times.

At an issue price of 38 sen/share, Inari’s IPO raised RM31.54 million in proceeds for the Group. Listing on Bursa Malaysia was "crucial" to Inari’s expansion, said Dr. Tan Seng Chuan, managing director, Inari Berhad. Of the proceeds, RM17.5 million will be allocated for capital expenditure, including to build a new assembly and manufacturing facility in Penang by Q1 2012. RM7.6 million will be for repayment of debt, RM4.5 million for general working capital, and RM2.0 million to defray listing expenses.

Inari received 6,308 applications for 114.2 million shares with a total value of RM43.4 million for its public tranche of 10.0 million shares. Inari’s IPO entailed the public issue of 83.0 million new ordinary shares, of which 10.0 million were available to the Malaysian public via balloting, 10.4 million shares for eligible directors, employees and business associates of the Group and its subsidiaries, 26.1 million shares for private placement to selected investors, and 36.5 million shares for Bumiputera investors approved by the Ministry of International Trade and Industry.

From FY2007 to FY2010, Inari recorded a 91.5% compound annual growth rate (CAGR) in group revenue to RM154.8 million, and 202.9% CAGR in group net profits to RM15.2 million over the same period. The company recently (July 15) appointed a new CEO, Lau Kean Cheon, who started in the industry with Intel Penang, followed by KESP Sdn Bhd Penang, Globetronics Technology Berhad Group, and Iso Technology Sdn Bhd (wholly owned Globetronics subsidiary).

M&A Securities Sdn Bhd is the adviser, underwriter, sponsor, and placement agent for Inari’s IPO.

Inari provides end-to-end and vertically integrated semiconductor packaging services for chips used in RF mobile technology and devices. Learn more at www.Inariberhad.com.

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July 13, 2011 — Packaging materials supplier Henkel worked with STMicroelectronics (STM) to qualify Henkel’s Ablestik C100 conductive die attach film materials for production of very small package configurations in a process called ScalPack, which incorporates die with extremely small dimensions into leadframe packages.  

The die placement process was developed with Henkel to increase workability in leadframe packaging (over die attach pastes), said Laura Ceriati, STMicroelectronics corporate package development director for leaded package platforms. STMicro expects to use the conductive die attach tape for medium-power applications. With the Ablestik product, one leadframe design to be used for multiple package types.  

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