Category Archives: Wafer Level Packaging

BY SYAHIRAH MD ZULKIFLI, BERNICE ZEE AND WEN QIU, Advanced Micro Devices, Singapore; ALLEN GU, ZEISS, Pleasanton, CA

3D integration and packaging has challenged failure analysis (FA) techniques and workflows due to the high complexity of multichip architectures, the large variety of materials, and small form factors in highly miniaturized devices [1]. The drive toward die stacking with High Bandwidth Memory (HBM) allows the ability to move higher bandwidth closer to the CPU and offers an oppor- tunity to significantly expand memory capacity and maximize local DRAM storage for high throughput in the data center. However, the integration of HBM results in more complex electrical communications, due to the emerging use of a physical layer (PHY) design to connect the chip and subsystems. FIGURE 1 shows the schematic of a 2.5D stacked die package designed so that some HBM μbumps are electrically connected to the main CPU through a PHY connection. In general, the HBM and CPU signal length needs to be minimized to reduce drive strength requirements and power consumption at the PHY.

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This requirement poses new challenges in FA fault isolation. A traditional FA workflow using electrical fault isolation (EFI) techniques to isolate the defect becomes less effective for chip-to-chip interconnects because there are no BGA balls for electrically probing the μbumps at the PHY. As a result, new defect localization techniques and FA flows must be investigated.

XRM theory

X-ray imaging is widely employed for non-destructive FA inspection because it can explore interior structures of chips and packages, such as solder balls, silver paste and lead frames. Thus, many morphological failures, such as solder-ball crack/burn-out and bumping failure inside IC packages, can be imaged and analyzed through X-ray tools. In 2D X-ray inspection, an X-ray irradiates samples and a 2D detector utilizes the projection shadow to construct 2D images. This technique, however, is not adequate for revealing true 3D structures since it projects 3D structures onto a 2D plane. As a result, important information, such as internal faulty regions of electronic packages, may remain hidden. This disadvantage can be overcome by using 3D X-ray microscopic technology, derived from the original computed tomography (CT) technique. In a 3D imaging system, a series of 2D X-ray images are captured at different angles while a sample rotates.

These 2D images are used to reconstruct 3D X-ray tomographic slices using mathematic models and algorithms. The spatial resolution of the imaging technique can be improved through the integration of an optical microscopy system. This improved technology is called 3D X-ray microscopy (XRM) [2]. FIGURE 2 shows an example 3D XRM image for a stacked die. The image clearly shows the internal structures – including the TSV, C4 bumps and μbump of the electronic components – without physically damaging or altering the sample. The high resolution and quality shown here are essential to inspect small structural defects inside electronic devices. With its non-destructive nature, 3D XRM has been useful for non-destructive FA for IC packaging devices.

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Failure analysis approach

The purpose of an FA workflow is to have a sequence of analytical techniques that can help to effectively and quickly isolate the failure and determine the root cause. Typical FA workflows for flip-chip devices consist of non-destructive techniques such as C-Mode scanning acoustic microscopy (C-SAM) and time domain reflectometry (TDR) to isolate the failure, followed by destructive physical failure analysis (PFA). However, there are limitations to each of these techniques when posed with the failure analysis of a more complex stacked die package.

C-SAM allows the inspection of abnormal bumps, delamination and any mechanical failure. A focused soundwave is directed from a transducer to a small point on a target object and is reflected when it encounters a defect, inhomogeneity or a boundary inside the material. The transducer transforms the reflected sound pulses into electromagnetic pulses, which are displayed as pixels with defined grey values thereby creating an image [3]. However, stacked die composed of a combination of multiple thin layers may complicate C-SAM analysis. This is because the thin layers have smaller spacing between the adjacent interface, and shorter delay times for ultrasound traveling from one interface to another. Therefore, failures between the die and die attach may not be easily detected, and false readings may even be expected.

TDR is an electrical fault isolation tool that enables failure localization through electrical signal data. The TDR signal carries the impedance load information of electrical circuitry; hence, the reflected signals show the discontinuity location that has caused the mismatch of impedance. In-depth theory on TDR is further discussed in Chin et al [4]. However, TDR can only estimate where the failure lies, whether it is in the substrate, die or interposer region. To pin point the exact location within the area of failure is difficult, due to limitations in separating the various small structures through the TDR signal. Additionally, some of the pulse power is reflected for every impedance change, posing challenges regarding unique defect isolation and signal complexity – especially for stacked die [5]. In cases where the failure pins reside in the HBM μbump region, no BGA ball out is available to probe and send an electrical pulse through.

Physical Failure Analysis (PFA) is a destructive method to find and image the failure once non-destructive fault isolation is complete. PFA can be done both mechanically and by focused ion beam (FIB). For stacked dies, FIB is predominantly used to image smaller interconnect structures such as TSVs and μbumps. However, the drawback is that the success of documenting the failure through PFA is largely dependent on how well the non-destructive FA techniques can isolate the failure region. Without good clear fault isolation direction, the failure region might be destroyed or missed during the PFA process, and thus no root cause can be derived.

The integration of XRM into the FA flow can help to overcome the limitations of the various analysis techniques to isolate the failure. It is a great advantage to image small structures and failures with the high spatial resolution and contrast provided by XRM and without destroying the sample. For failures in stacked die, XRM can be integrated into the FA flow for further fault isolation with high accuracy. The visualization of defects and failed material prior to destructive analysis increases FA success rates. However, the trade-off for imaging small defects at high resolution is time. For stacked die failures, C-SAM and TDR can first be performed to isolate the region of failure. With a known smaller region of interest to focus on, the time taken for XRM to visualize the area at high resolution is significantly reduced.

In cases where failures are identified in the HBM μbump, XRM is an effective technique to isolate the failure through 3D defect visualization. With the failure region isolated, XRM can then act as a guide to perform further PFA. Following are three case studies where XRM was used to image HBM packages with stacked dies.

Case studies

In the first case study, we explore the application of XRM as the primary means of defect visualization where other non-destructive testing and FA techniques are not possible. An open failure was reported for non-underfilled stacked die packages during a chip package interaction (CPI) study. The suspected open location was within the μbump joints at the HBM stack/ interposer interface. The initial approach exposed the bottom-most die of the HBM stack, followed by FIB cross-sectioning at the specified location. Performing the destructive approach to visualize the integrity of μbump joints in non-underfilled stack die packages was virtually impossible due to the fragility of silicon. The absence of underfill (UF) means that the HBM does not properly adhere to the interposer and is susceptible to peel off. In addition, there was no medium to release shear stresses experienced by the μbump joints upon bending stresses, which could not be absorbed by the package. As seen in FIGURE 3, parallel lapping of the HBM stack without UF caused die crack and peeling.

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Consequently, to avoid aggravating the damage on the sample, 3D XRM was performed to inspect and visualize the suspected location using a 0.7μm/voxel and 4X objective without any sample preparation. FIGURE 4 shows an example virtual slice where the micro-cracks throughout the row of μbump joints are visualized. The micro-cracks are measured a few microns wide. It is worth noting that the micro-cracks were visible with a short scan time of 1.5 hrs.

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With the critical defect information in 3D, PFA was performed on a sample that was underfilled to facilitate ease of sample preparation. SEM images in FIGURE 5 validated the existence of μbump micro-cracks observed by 3D XRM inspection.

In the second case study, the 3D XRM technique was applied to a stacked die package with a failure at a specific HBM/XPU physical interface (PHY) μbump connection. This μbump connection provides specific communication between the HBM stack and XPU die, and there is no package BGA ball out to enable electrical probing. Accordingly, it was not possible to verify if the failure type was an open or short. In addition, there was no means to determine if the failure was at the HBM or XPU die. Since defects from previous lots were open failures at the PHY μbump of the HBM, 3D XRM was performed at the suspected HBM open region using a 0.85μm/voxel and 4X objective.

As no defect was observed, XRM was then applied to the corresponding XPU PHY μbump. Contrary to the anticipated μbump open, a short was observed between two μbumps as shown in FIGURES 6a and 6b.

Screen Shot 2018-03-01 at 11.47.22 AM Screen Shot 2018-03-01 at 11.47.28 AM

 

The μbump short resulted from a solder extrusion bridging two adjacent μbumps. If 3D XRM had not been performed, a blind physical cross-section likely would have been performed on the initially suspected open region. As a result, the actual failure region may have been missed and/or destroyed.

In the final case study, an open failure was reported at a signal pin of a stack die package. As per the traditional FA flow, C-SAM and TDR techniques were applied to isolate the fault. C-SAM results showed an anomaly, and TDR suggested an open in the substrate as demonstrated in FIGURE 7a and 7b respectively.

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To verify the observations made by C-SAM and TDR non-destructive techniques, 3D XRM was performed using a 0.80μm/voxel and 4X objective at the region of

FIGURE 8 revealed a crack between the failure C4 bump and associated TSV. A physical cross-section was performed and the passivation cracks between the TSV and interposer backside redistribution layer (RDL) was observed as shown in FIGURE 9.

Screen Shot 2018-03-01 at 11.47.35 AM

In this case, 3D XRM provided 3D information for the FA engineer to focus on. Without the visual knowledge on the defect’s nature and location, the defect would have been missed during PFA.

Summary and conclusions

3D integration and packaging have brought about new challenges for effective defect localization, especially when traditional electrical fault isolation is not possible. 3D XRM enables 3D tomographic imaging of internal structures in chips, interconnects and packages, providing 3D structural information of failure areas without the need to destroy the sample. 3D XRM is a vital and powerful tool that helps failure analysis engineers to overcome FA challenges for novel 3D stacked-die packages.

Acknowledgement

This article is based on a paper that was presented at the 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2017).

References

  1. F. Altmann and M. Petzold, “Innovative Failure Analysis Techniques for 3-D Packaging Developments,” IEEE Design & Test, Vol. 33, No. 3, pp. 46-55, June 2016.
  2. C. Y. Liu, P. S. Kuo, C. H. Chu, A. Gu and J. Yoon, “High resolution 3D X-ray microscopy for streamlined failure analysis workflow,” 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2016, pp. 216-219.
  3. M. Yazdan Mehr et al., “An overview of scanning acoustic microscope, a reliable method for non-destructive failure analysis of microelectronic components,” 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro- electronics and Microsystems, Budapest, 2015, pp.1-4.
  4. J. M. Chin et al., “Fault isolation in semiconductor product, process, physical and package failure analysis: Importance and overview,” Microelectronics Reliability, Vol. 51, Issue 9, pp. 1440-8, Nov. 2011.
  5. W. Yuan et al., “Packaging Failure Isolation with Time-Domain Reflectometry (TDR) for Advanced BGA Packages,” 2007 8th International Conference on Electronic Packaging Technology, Shanghai, 2007, pp. 1-5.

Super Micro Computer, Inc. (NASDAQ: SMCI) today announced that it has expanded its Silicon Valley Headquarters to over two million square feet of facilities with the grand opening of its new Building 22.

The Corporate Headquarters includes engineering, manufacturing and customer service making Supermicro the only Tier 1 systems vendor to build its servers in Silicon Valley and worldwide.  Supermicro is ranked as the third largest server systems supplier in the world (Source: IDC).  In addition to the branded solution business used in the ranking, Supermicro also services large OEM and system integrator customers and shipped over 1.2 million units in 2017.

This latest building is the second of five facilities that the company plans to build on the 36-acre property formerly owned by the San Jose Mercury News. Additionally, the company continues to expand its other facilities worldwide.

“Having our design, engineering, manufacturing and service teams all here at our Silicon Valley campus gives Supermicro the agility to quickly respond to the newest technologies in the industry and to our customer’s needs and unique requirements, which is a major advantage that we have over the competition,” said Charles Liang, President and CEO of Supermicro.  “As our business continues to rapidly scale with over 1.2 million server and storage systems shipped globally last year, increasing our production capacity and capabilities is vital to keeping up with our rapid growth.  The opening of Building 22, along with the opening of two new facilities at our technology campus in Taiwan, provides the additional capacity and rack scale integration plug and play capabilities to ensure that we can provide the best possible service to our enterprise, datacenter, channel and cloud customers.”

“We’re thrilled to see an innovative, sustainable, and community-minded leader like Supermicro continuing to invest and grow in San Jose, and we look forward to their continued success now and for years to come!” said San Jose Mayor Sam Liccardo.

“The Corporation for Manufacturing Excellence – Manex would like to congratulate Supermicro for its continued growth through design and engineering excellence,” said Gene Russell, President and CEO of Manex.  “Its investments in workforce, physical plant and equipment are crucial to the Silicon Valley Ecosystem and to its global client base.  Manex, as a network member of the NIST Manufacturing Extension Partnership and the CMTC California network is a proud partner of Supermicro.”

Working closely with key partners like Intel, Supermicro leverages its strength in design and engineering to lead the way with first-to-market server and storage technology innovations. The company offers the industry’s broadest portfolio of advanced server and storage solutions including the popular BigTwin™ and SuperBlade® product lines and provides rack scale integration with rack plug and play capabilities.

Entering 2018 on solid ground


February 22, 2018

By Walt Custer, Custer Consulting Group

2017 finished on an upturn – both in the USA and globally.  Based on consolidated fourth-quarter actual and estimated revenues of 213 large, global electronic manufactures, sales rose in excess of 7 percent in 4Q’17 vs. 4Q’16 (Chart 1).  This was the highest global electronic equipment sales growth rate since the third quarter of 2011. Because some companies in our sample didn’t close their financial quarter until the end of January, final results will take a few more weeks – but all evidence points to a very strong fourth quarter of last year.

Custer1-Electronic-Equipment

 

Using regional (country specific) data (Chart 2), the normal, consumer electronics driven seasonal downturn began again in January.  However the recent year-over-year growth is still substantial.  On a total electronic equipment revenue basis, January 2018 was up almost 19.5 percent over January 2017.

Custer2-World-Electronic

Because this regional data in local currencies was converted to U.S. dollars at fluctuating exchange, the dollar denominated-growth was amplified by currency exchange effects.  At constant exchange the January growth was only 14 percent.   That is, when the stronger non-U.S. currencies were converted to weakening dollars, the dollar-denominated January 2018 fluctuating exchange growth was amplified by 5.5 percent.

Chart 3 shows 4Q’17/4Q’16 growth of the domestic electronic supply chain.  U.S. electronic equipment shipments were up 9.1 percent.  Only computer equipment and non-defense aircraft sales declined in the fourth quarter.  And of note, SEMI equipment shipments to North America rose almost 31 percent!

Custer3-US-Electronic-Supply

 

Chart 4 shows estimated fourth-quarter growth for the world electronic supply chain.  Only “Business & Office” equipment revenues declined in 4Q’17 vs. 4Q’16.

Custer4-Global-Electronic

Total global electronic equipment sales increased more than 7 percent in the fourth quarter and SEMI equipment revenues rose 32 percent.

2017 was a strong year and 2018 is off to a good start!  The 2017 lofty growth rates will temper, but this current expansion will likely continue.  Watch the monthly numbers!

Originally published on the SEMI blog.

Nordson Corporation (NASDAQ: NDSN) announces that the SEMI Foundation has appointed Joseph Stockunas, Corporate Vice President for Electronics Systems at Nordson Corporation and the immediate past chair of the SEMI North America Advisory Board, to the SEMI Foundation Board of Trustees in accordance with the association’s by-laws.

“We are excited to leverage Joe’s passion for innovation and his desire to help young people make thoughtful education and career choices,” said Leslie Tugman, Executive Director of the SEMI Foundation. “As the Foundation’s vision is expanding to address the larger industry workforce development pipeline and leadership in the area of women’s issues, Joe’s talent, industry insight, and commitment will be a great asset.”

The mission of the SEMI Foundation is to support education and career awareness in the field of high technology. The SEMI Foundation produces SEMI High Tech U (HTU), a three-day interactive program that encourages high school students to pursue academic paths that emphasize science, technology, engineering, and math (STEM) and to expose them to high technology careers such as semiconductor manufacturing.

The Nordson Corporation Foundation sponsored its first HTU program February 12 – 15, 2018 at the Nordson facility in Carlsbad, California. This was one of the first HTU events to be held in Southern California. Forty high school students from five local high schools, including Carlsbad, Sage Creek, San Marcos, Rancho Buena Vista, and Mission Hills, attended the program, where they learned from industry instructors and visited the UC San Diego campus for a look at college life. The Nordson Corporation Foundation is dedicated to improving the quality of life in its communities by improving educational outcomes that enable individuals to become self-sufficient, active participants in the community.

Stockunas has a long history of engaging and supporting STEM activities and the workforce development pipeline. Stockunas sponsored SEMI High Tech U at Air Products in Pennsylvania where he had previously worked for 30 years. In 2013, he joined Nordson Corporation, and has helped facilitate the company’s sponsorship of SEMI High Tech U in 2018.

“I have been a long-time supporter of the SEMI Foundation’s High Tech U program, which helps students make the connection between familiar electronic products and future career choices in high tech,” said Joe Stockunas. “I look forward to working with the Board to help drive new initiatives to support young people and strengthen the industry workforce.”

Qualcomm Incorporated (NASDAQ: QCOM) (“Qualcomm”) today announced that Qualcomm River Holdings B.V., an indirect wholly owned subsidiary of Qualcomm, has reached an agreement with NXP Semiconductors N.V. (NASDAQ: NXPI) to increase to $127.50 per share its previously announced cash tender offer to purchase all outstanding shares of NXP.  The amended agreement, which was approved by the Qualcomm and NXP Boards of Directors, also lowers the minimum tender condition from 80% of NXP’s outstanding shares to 70%.

Qualcomm also announced that Qualcomm River Holdings B.V. has entered into binding agreements with nine NXP stockholders who collectively own more than 28% of NXP’s outstanding shares (excluding additional economic interests through derivatives) to tender their shares at $127.50 per share.  These stockholders include funds affiliated with Elliott Advisors (UK) Limited and Soroban Capital Partners LP.

The revised price reflects enhanced current value drivers for NXP, including:

  • NXP’s recent performance, including calendar 2017 results that exceeded Qualcomm’s transaction model on revenue, gross margin and EBIT. NXP’s non-GAAP operating income (excluding Standard Products) increased 20% from calendar 2016 to 2017.
  • Strong market dynamics and positive outlook for key segments. NXP’s Auto business has increased revenues by 11% year over year. Qualcomm has also significantly improved its own capabilities in key industry segments such as Auto ($3 billion revenue pipeline), IoT ($1 billion in FY17 sales) and Networking, further enhancing the value proposition of the combined company to its customers and stockholders.
  • High confidence in annualized cost synergies of at least $500 million resulting from insights gathered during the integration planning process.

Steve Mollenkopf, Chief Executive Officer of Qualcomm Incorporated, said, “Qualcomm’s leading SoC capabilities and technology roadmap, coupled with NXP’s differentiated position in Automotive, Security and IoT, offers a compelling value proposition.  We remain highly confident in our fiscal 2019 Non-GAAP EPS target of $6.75–$7.50, which includes $1.50 per share accretion from the acquisition of NXP.  With only one regulatory approval remaining, we are working hard to complete this transaction expeditiously.  Our integration planning is on track and we expect to realize the full benefits of this transaction for our customers, employees and stockholders.”

Tom Horton, Presiding Director of the Qualcomm Board of Directors, said, “The acquisition of NXP will enable us to accelerate our growth strategy.  The Board unanimously believes this is an attractive acquisition at this price for Qualcomm stockholders based on NXP’s recent strong financial performance, the growth in key strategic areas such as Auto and IoT and our high confidence in management’s ability to execute upon the synergy opportunities.”

Dr. Paul E. Jacobs, Chairman of the Board of Qualcomm, said, “NXP is a highly strategic and attractive acquisition for Qualcomm that enhances the value of our leading 5G technologies.  We also believe the revised agreement provides certainty for both Qualcomm and NXP stockholders.”

Siemens announced it has entered into an agreement to acquire Oulu, Finland-based Sarokal Test Systems Oy, a provider of test solutions for fronthaul networks that are comprised of links between the centralized radio controllers and the radio heads (or masts) at the “edge” of a cellular network. Sarokal products are used by chipset vendors, fronthaul equipment manufacturers, and telecom operators to develop, test and verify their 4G and 5G network devices from the early design stages through implementation and field-testing.

“The planned acquisition of Sarokal reinforces our ongoing commitment to EDA and the IC industry,” said Tony Hemmelgarn, president and CEO of Siemens PLM Software. “Building on our acquisition of Mentor Graphics, we continue to make strategic investments which leverage Mentor’s existing strengths and enable Siemens to expand its offerings to the IC industry.”

Sarokal’s products are used to test transmission specifications across multiple domains. Its tester product family addresses the entire development and maintenance flow for cellular and wired transmission system testing. The technology is especially designed to detect radio frequency (RF) problems. With Sarokal’s foresight into the requirements of 5G testing, their testing models were created from the beginning for both the virtual (digitalization) environment as well as the physical testing environment.

“Sarokal has been on the forefront of the development of the 5G specification and its requirements for fronthaul networks since its inception. The 5G specification aims to greatly enhance performance for mobile broadband, network operation and Internet of Things (IoT) communication, and this requires new test methodologies,” said Harri Valasma, CEO at Sarokal. “Becoming part of Siemens and integrating our technology into the Veloce emulation platform will give us greater visibility into early customer adoption of 5G, which can help us maintain our leadership as this segment is forecasted to grow rapidly.”

“The addition of Sarokal’s one-of-a-kind fronthaul testing expertise is expected to provide our Veloce emulator customers with a unique advantage,” said Eric Selosse, vice president and general manager, Mentor Emulation Division, a Siemens business. “Sarokal’s tester technology in conjunction with Mentor’s Veloce emulation platform will enable customers to “shift left” the validation of 4G and 5G designs for accurate and timely pre- and post-silicon testing.”

The transaction is expected to close during the first quarter of calendar 2018, subject to receipt of regulatory approvals and other customary closing conditions. The terms of the transaction were not disclosed.

Siemens PLM Software, a business unit of the Siemens Digital Factory Division, is a global provider of software solutions to drive the digital transformation of industry, creating new opportunities for manufacturers to realize innovation. With headquarters in Plano, Texas, and over 140,000 customers worldwide, Siemens PLM Software works with companies of all sizes to transform the way ideas come to life, the way products are realized, and the way products and assets in operation are used and understood.

By Cherry Sun, SEMI China

Yawning differences between cultures, economic systems and rules of law stand as barriers for many China- and US-based technology companies to do business on each other’s soil, making it imperative for both countries to work together to bridge the gaps that make it harder for tech businesses in each country to find partners and open markets in the other, SEMI China president Lung Chu said at a recent conference.

One answer is for SEMI, serving as a natural unifying communications platform, to help foster greater cooperation between US and China tech companies, Lung Chu said, speaking at the 2nd Silicon Valley Beijing International IoT Summit & Investment and Financing Competition in Santa Clara last month. The event gathered industry experts and experts to mine opportunities across technologies including smart and mobile medical care, virtual and augmented reality, wearables, smart homes, artificial intelligence (AI), robotics, 3D printing, Internet of Things (IoT) and manufacturing design.

In the IoT roundtable chaired by Chu, he asked mayors and other city officials from Sunnyvale, Palo Alto and Cupertino to consider the potential of IoT technology for improving city management. Inspired by the idea of greater efficiency, the mayors pointed to IoT applications including traffic management to better regulate traffic flow; faster, more effective medical treatment from first responders and emergency medical technicians; more efficient energy usage by cities and the public; better water resources management; and bicycle sharing programs for commuters.

Deploying more advanced networking architectures, the mayors agreed, is the first step for cities seeking to fulfill the promise of IoT. A recognized global leader in smart city technologies, China is much more than a key trade partner with the U.S., having developed IoT use cases for cities in Silicon Valley and beyond to consider.

Chu also asked the mayors about the importance to their cities of attracting talent and encouraging entrepreneurship. The roundtable agreed that in Silicon Valley, taking risks in hopes of reaping huge profits is prized and that failure is embraced as necessary to innovation. In China, pressure on business startups to flourish can inhibit the free-wheeling thinking and calculated risk-taking often needed to build new enterprises.

On talent, one mayor underscored the importance of diversity in building a skilled workforce. According to a recent report based on 2016 census data, nearly three-quarters – about 71 percent of tech employees in Silicon Valley – “are foreign born, compared to around 50 percent in the San Francisco-Oakland-Hayward region,” The Mercury News reported. Carl Guardino, CEO of the Silicon Valley Leadership Group, has noted that this “diversity is the strength of Silicon Valley.”

Much as China can turn to Silicon Valley as a model of entrepreneurship and diversity, the U.S. can learn from China’s deployment of IoT technologies to power smart cities as the country’s prominence in the semiconductor manufacturing industry continues to grow. An ally in that rising influence, SEMI China follows the 5C principles – Connect, Collaboration, Community, Communication, China – to help narrow the differences between China and other countries and foster stronger partnerships.

Originally published on the SEMI blog.

IC industry wafer capacity, specifically in the memory segment, was inadequate to meet demand throughout 2017. However, with Samsung, SK Hynix, Micron, Intel, Toshiba/WD, and XMC/Yangtze River Storage Technology planning to significantly ramp up 3D NAND flash capacity over the next few years, and Samsung and SK Hynix boosting DRAM capacity this year and next, what does this mean for total industry capacity growth?  In its 2018-2022 Global Wafer Capacity report, IC Insights shows that new manufacturing lines are expected to boost industry capacity 8% in both 2018 and 2019 (Figure 1). From 2017-2022, annual growth in IC industry capacity is forecast to average 6.0% compared to 4.8% average growth from 2012-2017.

annual wafer trends

Figure 1

Large swings in the addition or contraction of wafer capacity by the industry, as a whole, appear to be moderating. Since 2010, annual changes in wafer capacity volume have been in the relatively narrow range of 2-8%, with the largest year-to-year difference being just three percentage points.  This suggests that IC manufacturers are better today than in years past about trying to match supply with demand.  It’s still an incredibly difficult task for companies to gauge how much capacity will be needed to meet demand from customers, especially given the time it takes a company to move from the decision to build a new fab to that fab being ready for mass production.

Many companies, DRAM and NAND flash suppliers in particular, have become much more active with new fab construction and expansion projects at existing fabs.  This surge in activity comes after four years (2014-2017) when capacity growth lagged wafer start volume increases.  During the past few years, IC producers have worked to increase utilization rates from the low levels in 2012-2013.

If all the new fab capacity expected to be brought on-line in 2019 happens as planned, the volume of capacity added that year will approach the record set in 2007.  Figure 2 shows more that 18 million wafers per year of new capacity is expected to be added in 2019, and this number even assumes some of the massive DRAM and NAND fabs being built by Chinese companies will not be carried out quite as aggressively as has been advertised.  IC Insights believes that construction of these China-owned fabs is progressing slower than planned.

Figure 2

Figure 2

By Jamie Girard and Jay Chittooran, SEMI Public Policy

With much pride, President Donald Trump, in his State of the Union address last week, touted the signature legislative achievement of his first year in office – passage of the Tax Cuts and Jobs Act.  As companies doing business globally, SEMI members have long stressed their concern that the US business tax code was putting them at a disadvantage.  SEMI has worked for many years to voice its position that the US code needed to be reformed to lower the overall tax rate on businesses while also retaining incentives for innovation, like the research and development (R&D) and tax credits.  SEMI also pushed for the US to move to a territorial tax system to bring the US into alignment with the rest of the world.

President Donald Trump, State of the Union speech. Photo credit: CNN

President Donald Trump, State of the Union speech. Photo credit: CNN

The Tax Cuts and Jobs Act implements all the of principle that SEMI members have advocated for, and included other industry priorities like repatriation of foreign held assets at a lower rate.  The new structure promises to allow for a more competitive business environment for companies doing business from the US, and greater growth for them globally.

“As tax cuts create new jobs, let us invest in workforce development and job training,” Trump noted in his State of the Union speech, addressing another major industry priority. “Let us open great vocational schools so our future workers can learn a craft and realize their full potential.”

Workforce development (Talent) is a critical issue for the industry, and SEMI recognizes the pressing need on multiple fronts to find the workers, both technical and highly-educated, to continue the work of driving innovation in the semiconductor industry.  While SEMI works with industry partners to boost the industry talent pool, we also recognize that the federal government has a role to play in ensuring that the US is doing its share to help address the problem. That’s why SEMI supports legislation like H.R. 4023, the Developing Tomorrow’s Engineering and Technical Workforce Act, aimed at providing federal dollars to promote engineering education at all levels of learning. The bill has bipartisan support in Congress, and SEMI will continue to work to see the bill travel to President Trump’s desk for his signature.

Facilitating trade and lowering barriers for good and services to move across borders is key to SEMI’s mission to support its members. The semiconductor industry has catalyzed growth across the global economy – growth that relies heavily on trade.

“America has also finally turned the page on decades of unfair trade deals that sacrificed our prosperity and shipped away our companies, our jobs, and our nation’s wealth,” Trump noted last Tuesday. “The era of economic surrender is over. From now on, we expect trading relationships to be fair and to be reciprocal. We will work to fix bad trade deals and negotiate new ones.”

Unfortunately, trade has been turned into a hot-button political issue, raising many new trade challenges to companies throughout the semiconductor industry. The Trump Administration has levied intense criticism of China, launched a number of trade investigations citing foreign overproduction, and has threatened to withdraw from the Korea-U.S. Free Trade Agreement (KORUS). The United States has also levied tariffs on a number of products, including solar cells. This is all on top of the North American Free Trade Agreement (NAFTA) modernization talks, which have seen slow and shallow progress.

While the United States “reexamines” and stands still, other countries are filling the leadership void. China, Canada, Korea, and the European Union, among others, are negotiating or have concluded trade deals in the last year. Indeed, the updated Trans-Pacific Partnership, which now excludes the US but covers many of the fastest-growing Asian markets, is on track to be enacted by the end of the year. SEMI will continue to work on behalf of its members around the globe to open up new markets and lessen the burden of regulations on cross-border trade and commerce.

Additionally, although President Trump devoted much his address to immigration, he overlooked the opportunity to address the need for immigration reform for high-skilled workers.  This important aspect of the immigration debate, which also has major implications for economic growth, will fall to Congress to sort out in any immigration package it considers in the coming weeks.

Fortunately, Sen. Orrin Hatch (R-UT) recently reintroduced his Immigration Innovation Act, also known as “I-Squared,” which would implement a number of reforms to the H1-B visa and green card system for highly-skilled workers.  The bill would raise the cap for H1-B visas from the current 65,000 to allow for as many as 190,000 in good economic times, while also lifting the cap on greed card holders with STEM degrees from US institutions.  SEMI has long supported these efforts and will continue to work with policymakers to see reforms implemented to improve the system.

While partisanship in Washington remains high, SEMI continues to work on behalf of its members to advance crucial public policy matters for its members with policymakers in Washington, DC. In particular, SEMI focuses on how these issues impact the four 4T’s – Trade, Taxes, Technology and Talent. The path forward on many of these issues will be complicated by midterm election year politics, but the opportunity remains to see real positive changes enacted, even in such a challenging environment.

If you’d like more information on SEMI’s public policy work, or how you can be involved, please contact Jamie Girard at [email protected].

Market shares of top semiconductor equipment manufacturers for the full year 2017 indicate large gains by Tokyo Electron and Lam Research while top supplier Applied Materials dropped, according to the report “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, a New Tripoli-based market research company.

The chart below shows shares for the entire years of 2016 and 2017. Market shares are for equipment only, excluding service and spare parts, and have been converted for revenues of foreign companies to U.S. dollars on a quarterly exchange rate.

market shares

Market leader Applied Materials lost 1.8 share points among the top seven companies, dropping from 28.8% in 2016 to 27.0% in 2017. Gaining share are Tokyo Electron Ltd., which gained 2.1 share points while rising from 17.4% in 2016 to 19.1% in 2017, and Lam Research, which gained 1.5 share points and grew from a 19.4% share in 2016 to a 20.9% share in 2017.

In third place ASML gained 0.6 share points, growing from an 18.8% share in 2016 to a 19.4% share in 2017.

Fifth place KLA-Tencor is the dominant supplier in the process control sector (inspection and metrology) and competes against Applied Materials and Hitachi High-Technologies, as well as several other companies including Nanometrics, Nova Measuring Instruments, and Rudolph Technologies. KLA-Tencor gained market share against each of its competitors in this sector in 2017.

Much of the equipment revenue growth was attributed to strong growth in the DRAM and NAND sectors, as equipment was installed in memory manufacturers Intel, Micron Technology, Samsung Electronics, SK Hynix, Toshiba, and Western Digital. The memory sector is expected to have grown 60.1% in 2017 and another 9.3% in 2018 according to industry consortium WSTS (World Semiconductor Trade Statistics).

Following the strong growth in the semiconductor equipment market, The Information Network projects another 11% growth in 2018. for semiconductor equipment.