Category Archives: Wafer Level Packaging

(December 16, 2010 – Marketwire) — The Centre Intégré de Microélectronique Provence Alpes Côte d’Azur (CIMPACA) selected DCG Systems products for its characterization and failure analysis platform: the ELITE lock-in thermography system and the Meridian WaferScan emission microscopy wafer prober with LVx option. The LVx technology provides continuous wave laser voltage probing (CW-LVP) and laser voltage imaging (LVI).

"These investments are a significant element of the CIMPACA three-year plan to offer access to key technologies for our members and customers," said Pascal Galand, characterization platform director of the CIMPACA. Added Dr. Israel Niv, president and CEO of DCG Systems, "CIMPACA continues to acquire the most advanced diagnostic and characterization systems in the market to meet the challenges of advanced semiconductor technologies down to 22nm." Read more about semiconductor inspection and test.

Sector Technologies, DCG’s European representative, will provide service and application support on all these systems for a quick and smooth ramp up at CIMPACA. "The extensive evaluation we performed demonstrated that these tools are very powerful, and application support is key for the best usage of the equipment and the development of new debug techniques," said Jean-Philippe Roux, president of SECTOR Technologies SAS.

"For external customers’ performance, flexibility and support efficiency are the keys to success," said Bernard Picart, LFoundry Lab Director. "DCG Systems products and Sector Technologies engineers are helping us to meet our objectives."

CIMPACA Characterization Lab is a mutualized platform between different local partners located in Rousset, France, and initiated by STMicroelectronics, LFoundry, and universities. It offers a range of complementary expertise in physical-chemical materials analysis and in failure analysis for issues relevant to a wide range of business fields (semiconductors, photovoltaic technologies, aerospace industry, etc.). For more information please visit www.arcsis.org/caracterisation.html

SECTOR Technologies SAS provides sales and service support for semiconductor high-technology products in Europe. For more information please visit www.sector-technologies.com.

DCG Systems, Inc. provides semiconductor debug and characterization solutions. DCG Systems is comprised of the former Schlumberger/NPTest Probe Systems division, Optonics, Inc., Hypervision, Inc. and Zyvex Instruments, LLC, with an installed base of over 950 systems worldwide. For more information please visit www.dcgsystems.com.

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by Dr. Phil Garrou, contributing editor

December 15, 2010 – With a general consensus that CMOS is becoming economically if not technically less and less viable as the industry continues to scale, it is to be expected that we will be seeing more and more 3D IC presentations at IEEE’s premier device conference, the IEDM (International Electronic Devices Meeting).

During his keynote presentation, Jim Clifford, SVP and operations GM at Qualcomm, indicated that scaling was becoming to expensive and therefore the company was backing 3D through-silicon via (TSV) technology. He urged the rest of the industry to "collaborate on 3D IC and invest in its infant infrastructure."

Conventional scaling has become more challenging in terms of materials, patterning and electrical performance, and now requires huge capital investments, noted Kinam Kim, president of Samsung Advanced Institute of Technology (SAIT), in his keynote presentation on the future of silicon technology. Current scaling strategy, he said, "is almost unusable for the 10nm node."

Kim expects mobile processors, FPGAs, and high-performance ASIC applications will require more functionality at greater speeds, which will necessitate "a heterogeneous device stack with a wide I/O interface and high data rates." 3D IC technology, he noted, is being adopted "as a promising solution for these devices."

In a presentation on 3D integration for the 28nm node and beyond, TSMC researchers indicated they have successfully integrated 3D technology into advanced CMOS foundry processes, described as "a major step toward 3D production."

Of special interest are the TSMC studies on Cu protrusion and its effects on device fabrication and reliability. As the system cools down from thermal excursions, mismatches in CTE between Si, SiO2 liner, and Cu introduces two un-desirable effects:

  • Cu extrusion around the center of the TSV. They find that protrusions depend on several process parameters, including the electroplating processes (ECP), electrolyte selection, impurities co-deposited with Cu, Cu grain size distribution, and post deposition annealing conditions.
  • Liner cracking. Having the smallest CTE, the oxide liner undergoes high stresses exerted by the Cu TSV and the Si substrate. The maximum stress concentration is found to be near TSV bottom, where the majority of liner cracks were observed that causes significant current leakage. TSMC has reportedly found solutions to these issues which strongly impact chip yield.

 

3D-induced stresses are one of the key constraints in a 3D design flow that must be controlled in order to preserve the integrity of front-end devices. IMEC and some of their consortium members (Panasonic, Qualcomm, Samsung) examined the stress induced by single- and arrayed TSVs, quantifying the stress distribution and determining its impact on both analog and digital FEOL devices and circuits. They conclude that stress aware design and accurate keep-out-zone (KOZ) dimensions will be needed to optimize silicon usage.

From stress modeling and experimental data, the IMEC consortium has developed transistor KOZ for both digital and analog circuits. The IMEC researchers conclude that the KOZ for a large matrix of TSVs is over 200μm for analog circuits and 20μm for digital circuits, and add that the complex interaction of stress components makes it difficult to use simple design rules without sacrificing large layout area. Depending on the TSV footprint and the number of TSV required, different TSV placements will be optimum (single, row, matrix).

 

Dr. Phil Garrou from Microelectronic Consultants of NC is a contributing editor for Solid State Technology and Advanced Packaging on www.ElectroIQ.com. Read his blog, Insights from the Leading Edge.

(December 15, 2010) — The adoption of flip chip and wafer level packaging (WLP) continues to expand to a wide range of devices. TechSearch International’s new study, "2010 Flip Chip and WLP: Market Projections and New Developments," projects a compound annual growth rate (CAGR) of more than 15% for flip chip units. In unit volumes, WLPs are expected to see a 12.48% CAGR from 2009 to 2014. The report profiles drivers for the demand for gold and solder bumping, as well as wafer level packaging.

The drivers for flip chip continue to be performance, on-chip power distribution, pad-limited designs, and form factor requirements. The use of FCIP is expanding for microprocessors, ASICs, field programmable gate arrays (FPGAs), DSPs, media devices, chipsets, and graphics chips. Driven by form factor, many wireless products are adopting flip chip interconnect. Solder bumped devices are found in applications such as automotive electronics, computers and peripherals, telecommunications, and consumer products. Strong growth is projected for copper (Cu) pillar and 300mm wafer bumping.

The growth in WLPs is driven by increased demand for thinner, lighter-weight portable products; WLPs are adopted for form factor, performance, and cost reduction reasons. The industry has seen an increase in shipments of analog devices such as power amplifiers, audio CODEC, integrated power management controllers, and ring tones for mobile phones, MOSFETs, image sensors, wireless, and integrated passive devices (IPDs). WLPs have historically been used for low-pin-count (≤100 I/O) applications, but many companies plan to use WLPs for higher-pin-count applications with larger die sizes (7 x 7mm or larger). An increasing number of companies are interested in fan-out WLPs (FOWLP). A variety of package offerings are appearing on the market. Fan-out WLPs are a package option for devices with a large number of I/Os that cannot be accommodated by a fan-in design. The use of a fan-out solution provides the same low-profile advantage as the conventional WLP.

The 200-page TechSearch International report provides an updated forecast for the flip chip wafer bumping market by product application, device type, FCIP/FCOB split, number of wafers, and number of die. Also included in this report are projected demand and capacity (merchant and captive) by the number of wafers and bump type. Geographic changes in the location of bumping supply are analyzed. WLP demand is projected in number of die, number of wafers and device type. Capacity is stated in wafers. Bumping, wafer level packaging, and contract assembly service providers are highlighted in terms of capability and experience. Contacts for these companies as well as suppliers of laminate substrates, bonding equipment, and inspection systems are provided.

TechSearch International, Inc. is a market research firm specializing in technology trends, microelectronics packaging, and assembly. Learn more at http://www.techsearchinc.com

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(December 14, 2010 – Marketwire) — FormFactor Inc. (NASDAQ: FORM) announced that Executive Chairman Carl Everett was elected to serve as non-executive Chairman of the Board of Directors. Current lead independent director Jim Prestridge will remain on the Board. FormFactor also announced the resignations of Board members Homa Bahrami, Chenming Hu and Harvey Wagner from the Company’s Board of Directors.

All of the changes are effective December 26, 2010, the start of the Company’s 2011 fiscal year.

"Carl did an outstanding job stepping in as CEO during a very challenging time for the Company and leading the transition to our new CEO, Tom St. Dennis," stated Jim Prestridge, lead independent director. "Carl will now lead the Board as it oversees the Company’s turn-around, its future growth and long-term strategic direction."

FormFactor noted that the resignations were not the result of any disagreements among the directors, but are a reflection of the Board’s decision to adjust its structure as a part of FORM’s larger efforts to streamline its operations. Prestridge added, "On behalf of the Board of Directors and all employees, we thank the retiring directors for their outstanding service to FormFactor."

FORM also announced that it expects revenue for its fourth fiscal quarter 2010 to be within its prior guidance range of $40 to $45 million.

FormFactor Inc. (NASDAQ: FORM) is a leader in advanced wafer probe cards, which are used by semiconductor manufacturers to electrically test integrated circuits, or ICs. The Company’s wafer sort, burn-in and device performance testing products move IC testing upstream from post-packaging to the wafer level. For more information, visit the Company’s website at www.formfactor.com

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(December 10, 2010) — Diodes Incorporated (Nasdaq: DIOD), high-quality application specific standard products manufacturer and supplier, released its first device in its unique PowerDI5060 package, the DMP3010LPS 30V rated p-channel enhancement mode MOSFET, offering designers of notebooks, netbooks and other consumer electronics improvements in reliability and reductions in PCB space requirements.

With a junction to case thermal resistance (Rthj-c) of 2.1°C/W, the PowerDI5060’s thermal resistance is 10 times lower than an SO8 alternative, improving on power dissipation performance, resulting in cooler running and more reliable product design. Its off-board height of 1.1mm is also 54% less than that of SO8, making it well suited for low profile applications.

With a large drain pad significantly reducing package inductance and resistance parameters, the PowerDI5060 package helps to significantly boost p-channel MOSFET performance. With the DMP3010LPS’s low typical on-resistance of 7.8mΩ at 10V VGS on-state losses are effectively minimized in load switching and battery charging duties.

Diodes Incorporated (Nasdaq: DIOD) manufactures and supplies high-quality application specific standard products within the broad discrete, logic, and analog semiconductor markets. Diodes serves the consumer electronics, computing, communications, industrial, and automotive markets. Diodes’ products include diodes, rectifiers, transistors, MOSFETs, protection devices, functional specific arrays, single gate logic, amplifiers and comparators, Hall-effect and temperature sensors; power management devices, including LED drivers, DC-DC switching and linear voltage regulators, and voltage references along with special function devices, such as USB power switches, load switches, voltage supervisors, and motor controllers. For further information, including SEC filings, visit http://www.diodes.com.

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(December 9, 2010) — The MiQro Innovation Collaborative Centre (MICC; Bromont, QC, Canada) will receive a $14.1 million grant as part of the Canadian government’s Centres of Excellence for Commercialization and Research (CECR) program. This new grant, to be paid to the MICC over five years, is in addition to $83 million from the Canadian government and $95 million from the Quebec government announced in 2009.

The investment is part of a $61.1 million program that establishes the MICC as one of five new Centres of Excellence. It is intended to accelerate and increase the MICC’s level of contribution to the Canadian and global semiconductor industries. The grant will be used to attract top researchers and add resources at the centre to support the process of translating leading-edge research into practical, commercializable industry solutions.

DALSA (Waterloo, ON, Canada) is one of the founding partners in the MICC along with IBM Canada and the Université de Sherbrooke. The MICC will house equipment for 200mm-based microelectromechanical systems (MEMS) and 3D wafer level packaging (WLP), as well as advanced technologies associated with the assembly and packaging of silicon chips.

For more information, contact DALSA at http://www.dalsa.com/

(December 9, 2010) — The MiQro Innovation Collaborative Centre (MICC; Bromont, QC, Canada) will receive a $14.1 million grant as part of the Canadian government’s Centres of Excellence for Commercialization and Research (CECR) program. This new grant, to be paid to the MICC over five years, is in addition to $83 million from the Canadian government and $95 million from the Quebec government announced in 2009.

The investment is part of a $61.1 million program that establishes the MICC as one of five new Centres of Excellence. It is intended to accelerate and increase the MICC’s level of contribution to the Canadian and global semiconductor industries. The grant will be used to attract top researchers and add resources at the centre to support the process of translating leading-edge research into practical, commercializable industry solutions.

DALSA (Waterloo, ON, Canada) is one of the founding partners in the MICC along with IBM Canada and the Université de Sherbrooke. The MICC will house equipment for 200mm-based microelectromechanical systems (MEMS) and 3D wafer level packaging (WLP), as well as advanced technologies associated with the assembly and packaging of silicon chips.

For more information, contact DALSA at http://www.dalsa.com/

(December 3, 2010) — DEK has launched an addition to its VectorGuard stencil range. VectorGuard 3D stencils are designed for specialist applications requiring multiple level printing. Facilitating printing on different levels with upward or downward steps, VectorGuard 3D enables a uniform stencil thickness.

Targeted at applications consisting of different levels on the PCB or substrate, the electroformed nickel VectorGuard 3D Stencil prints two levels at the same time, accommodating levels that differ by up to 3mm. Previously, devices such as power transistors requiring support on multiple levels, necessitated a dispensing operation following stencil print. VectorGuard 3D eliminates the dispenser requirement. VectorGuard 3D meets the challenges of providing coverage for dedicated areas on the board, such as chip on board (COB). Equally, the process can be used to protect bonding areas from contact with the stencil. Other applications particularly suited to VectorGuard 3D include printing of heatsink pockets for power components or printing of 3D mounting PCBs.

By avoiding the process of using thick stencils and milling down print areas, the 3D model is said to reduce stencil stress and increase process reliability.

VectorGuard 3D stencils will be individually engineered to meet specific application requirements.

Visit www.dek.com for more information.

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(December 2, 2010 – BUSINESS WIRE) — Vishay Intertechnology Inc. (NYSE: VSH) has entered into a new five-year $450 million credit facility. The senior secured facility, which matures on December 1, 2015, replaces VSH’s prior $250 million revolving credit facility, which was scheduled to mature on April 20, 2012.

Borrowings under the new facility will bear interest at LIBOR plus an interest margin. The applicable interest margin is based on Vishay’s then current leverage ratio. Based on Vishay’s current leverage ratio, borrowings bear interest at LIBOR plus 1.65%; Vishay is also required to pay a facility fee of 0.35% per annum on the entire commitment amount for a total borrowing cost, based on current leverage, of LIBOR plus 2.00% for the outstanding amount under the new credit facility. The interest rate under the prior facility was at LIBOR plus 1.875% plus a facility commitment fee of 0.35% per annum on the entire commitment amount for a total of LIBOR plus 2.225% for the outstanding amount.

The new facility also permits Vishay, upon satisfaction of certain conditions, to settle the principal amount of its 2.25% convertible senior notes in cash upon conversion, and settle any additional amounts in shares. The 2.25% convertible senior notes were issued on November 9, 2010.

Dr. Lior Yahalomi, Vishay’s CFO said, “We are excited to capitalize on favorable credit market conditions and Vishay’s new level of business performance to obtain this five-year, $450 million credit facility at lower interest rates than we are currently paying. Combined with our strong operational performance and continued free cash generation, this facility will provide Vishay with financial flexibility to pursue our business strategy.”

JPMorgan Chase Bank. N.A. acted as administrative agent. J.P. Morgan Securities LLC acted as lead arranger and joint bookrunner. Comerica Bank and Bank Leumi USA served as joint bookrunners and co-syndication agents. The Bank of Tokyo-Mitsubishi UFJ, Ltd. and HSBC Bank USA, N.A. functioned as co-documentation agents.

Vishay Intertechnology Inc., manufactures discrete semiconductors (diodes, MOSFETs, and infrared optoelectronics) and passive electronic components (resistors, inductors, and capacitors). Vishay can be found on the Internet at http://www.vishay.com.

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(December 1, 2010 – Marketwire) — MicroProbe, wafer test technology supplier, is extending its direct-dock offering to support Advantest’s T2000 SoC test platform. The T2000 platform-compatible option — now available on MicroProbe’s complete line of advanced probe cards — enables test coverage at wafer sort. More than 100 direct-dock probe cards are already in the field.

The direct-dock probe card enables final test at wafer sort by removing the bandwidth limitation between the tester and the semiconductor device under test. Using system-level optimization, the direct-dock option shortens the electrical trace length from the tester to the device which results in better signal bandwidth and fidelity. This means earlier detection of certain defects that might otherwise escape wafer test and only become apparent during final test of the packaged devices.

For new product ramps where cost efficiencies and time-to-volume are the new imperatives, or for known-good-die (KGD) test models that require 100% test coverage at wafer sort, the benefits of direct-dock are especially significant.

MicroProbe provides advanced wafer test solutions to global semiconductor manufacturers. For more information about MicroProbe, visit www.microprobe.com.

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