Category Archives: Wafer Level Packaging

by Dr Phil Garrou, contributing editor

December 1, 2010 – The first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits "3D-TEST" was held earlier this month in Austin TX, chaired by Yervent Zorian of Virage Logic and Erik Jan Marinissen of IMEC.

"The 3D topic is really being picked up by the test community now, commented Marinissen. "At the ITC [International Test Conference] last year coverage of 3D testing was limited. This year we see significant coverage in the main ITC meeting, followed by a this workshop dedicated to 3D Test issues which was attended by nearly 100 professionals."

Marinissen presented the early results of the IEEE Computer Societies standardization study group on 3D Test. The 42 corporate and institute participants include: AMD, ARM, Cadence, Cascade Microtech, Cisco, IBM, IMEC Infineon, ITRI, Mentor Graphics, Qualcomm, ST Micro, Synopsys, TI, TSMC and Verigy. The following standardization needs were identified:

Bob Patti, CTO of Tezzaron, discussed their form of built in self test (BIST) called Bi-STAR. He claims that Bi-STAR tests and compares 2304 bits/clock cycle, "more than 100× faster than can be achieved by any external memory tester." Reportedly Bi-STAR can test and repair bad memory cells, line drivers, and sense amps; shorted word lines and bitlines; leaky bits; and bad secondary bus drivers.

Sanjiv Taneja, VP for front-end design at Cadence, showed a long list of test challenges. Integration of design and test, he offered, is the only way to solve these complex issues, and concurrent optimization for area, timing, power, and testability is the only means to achieve required predictability.

Ken Smith of Cascade Microtech showed details on their high-density MEMS probe card technology, which makes 1g tip forces feasible and very low pad damage (and scrub marks <100nm deep) possible at 40μm array pitch.

 

Such lithographically fabricated probe cards "enable scalability which will lower cost just as IC linewidth scaling has reduced the cost of IC functions," Smith said. "Instead of probe costs being roughly proportional to pincount, the cost of a MEMS probe should be roughly proportional to the probe area."

Chen Hao, test engineer at TSMC, presented an assessment of the failure modes seen when fabricating 3D ICs with microbumps including issues with alignment, TSV voids, impurities at the bonding interfaces, nonuniformity in the insulation liner, and TSV delamination from the substrate due to the thermal stress and warpage.

Besides testing, thermal issues, electromigration, TSV redundancy, and ESD also need attention, Hao added.

Dr. Phil Garrou from Microelectronic Consultants of NC is a contributing editor for Solid State Technology and Advanced Packaging on www.ElectroIQ.com. Read his blog, Insights from the Leading Edge.

(December 1, 2010 – GLOBE NEWSWIRE) — Alpha and Omega Semiconductor Limited, or AOS (Nasdaq:AOSL), a designer, developer and global supplier of a broad range of power semiconductors, today announced that it has entered into definitive share purchase agreements for the acquisition of all of the outstanding shares of Agape Package Manufacturing Ltd., or APM, that are not already owned by AOS. APM is a provider of semiconductor packaging and testing services. The consideration for the acquisition is approximately $38 million, comprising of approximately $17 million in cash and 1.8 million AOS’s common shares.

Prior to this acquisition, AOS held 43% equity stake in APM, which was accounted for under the equity method of accounting. Upon closing of this acquisition, APM will become a wholly-owned subsidiary of AOS and its financial results will be fully consolidated in the financial statements of AOS.

AOS currently accounts for approximately 75% of APM’s production output. AOS do not anticipate any substantive change after this acquisition, and APM will continue to provide capacity and services to APM’s existing customers without interruption.

"This acquisition represents a successful execution of our long-term strategy to expand manufacturing capacity as our business grows. We believe that this will have a positive impact on our gross margin and profitability," said Dr. Mike Chang, CEO and chairman of AOS. "We expect a smooth transition and integration after the acquisition since we already have an excellent working relationship with APM."

The transaction has been approved by the board of directors. The transaction is subject to customary closing conditions and expected to be closed in early December 2010.

Alpha and Omega Semiconductor Limited, or AOS, is a designer, developer and global supplier of a broad range of power semiconductors, including a wide portfolio of Power MOSFET and Power IC products. For more information, visit www.aosmd.com.

(November 30, 2010) — Rudolph Technologies Inc. (NASDAQ: RTEC), process characterization equipment and software provider for wafer fabs and advanced packaging facilities, is partnering with a major outsourced semiconductor assembly and test (OSAT) services manufacturer to provide its inspection and metrology capability in the development of stacked packaging processes. The process uses silicon interposer technology, sometimes referred to as 2.5D IC, as an intermediate step toward full blown 3D ICs.

“The NSX System will measure via depth, inspect for defects and provide 3D metrology of solder bumps. Rudolph is collaborating with several leading-edge companies in the assembly and test sector, and we believe this effort will help to ensure the continued successful development of our NSX Systems for 3D IC applications,” said Rajiv Roy, Rudolph’s vice president of business development and director of back-end marketing.

Roy adds, “We were selected for this development project because we were able to meet the customer’s current specifications, and they are willing to work with us to make adjustments to the NSX System as we move forward with this project.”

Silicon interposer technology allows manufacturers to stack multiple chips to improve performance and increase the computing power in a small volume. It is particularly attractive to makers of cell phones and other handheld devices that must combine various chips with different functionality in a small space. The silicon interposer provides high density, short path signal routing between the stacked chips without requiring drastic changes in the design and manufacture of the chips themselves. Also read: Xilinx stacked silicon interconnect creates multi-die FPGA

"This is an important step toward full-blown 3D ICs,” Roy continued. “There are still a number of hurdles, however, such as lack of standards and high manufacturing costs for through-silicon-via based 3D ICs in high volume.” Silicon interposer technology allows manufacturers to roll out production-worthy devices without the TSV standards in place, and without the need to modify existing devices already in production.

Rudolph’s NSX Series Macro Defect Inspection Systems help to reduce the manufacturing costs and time-to-market of integrated circuits (ICs). Their high throughput and high repeatability are well established in high-volume applications throughout the device manufacturing process. The NSX System, equipped with Discover Defect Analysis and Data Management software, quickly and accurately detects yield-inhibiting defects, providing quality assurance and valuable process information.

Rudolph Technologies Inc. designs, develops, manufactures and supports defect inspection, process control metrology, and data analysis systems and software used by semiconductor device manufacturers worldwide. Additional information can be found at www.rudolphtech.com.

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(November 29, 2010) — Applied Materials (AMAT) speaks about its new conductor etch system — the Centris AdvantEdge Mesa Etch — released at SEMICON Japan this week. The company sees the gap in the lithography roadmap is an etch opportunity. Thorsten Lill, VP Etch Business Group, at Applied, told ElectroIQ that new steps in advanced transistors, double-patterning, and advanced packaging are driving growth in the conductor etch market (~$1.6B market in 2010). Along with advanced processes, however, is the requirement to drive down the cost-per-bit (Figure 1).

Click to Enlarge
 
The tool features eight process chambers: six etch and two post-etch clean chambers. Applied Materials’ proprietary software accomplishes chamber matching (Figure 2). Calibration technology is incorporated into the system — when not running product wafers, the system runs auto calibration routines that control pressure and gas flow. "By keeping these processing parameters stable, we also keep the output stable, i.e., the critical dimension (CD)," said Lill.

Click to Enlarge

The Mesa process chambers, released in July of this year (see product news about the Mesa, and podcast interview on the technology), feature synchronous pulsing technology that creates a plasma environment to reduce micro-loading. “When we turn the plasma off, we allow the wafer to "relax" electrically, i.e., the charges can dissipate and this reduces one major root cause of micro-loading (mass charging and ion deflection)," Lill told Debra Vogler, senior technical editor. "Basically, the ions’ trajectories are distorted and the ions, instead of hitting the bottom of the feature, they hit the sidewall and they either get lost, or you get profile distortions."

Listen to Lill’s interview about the AMAT conductor etch technology: Download or Play Now

Lill said that end users — particularly the mega-fabs — are pushing for tools that provide ever larger savings on facilitization costs. The company released calculations using standard SEMI S23 methods that indicate an ~35% improvement in energy savings when compared to standard etchers, and lower CO2 emissions per system: equivalent to taking 50 cars per year off the road, said Lill. And one system saves an Olympic-size swimming pool of water per year.

An additional system feature is that bromine (a bromine-containing gas is used during the process) is abated in the load lock, rather than in a separate, dedicated treatment chamber. “This allows us to run six chambers – so the new system, in essence, is an eight-chamber mainframe,” said Lill. 

(November 29, 2010) — The phoenix nanotom m, from GE´s Inspection Technologies business, has been developed for high resolution and high precision X-ray computed tomography (CT) in non-destructive 3D analysis and 3D metrology.

Featuring fully automated CT scan execution, volume reconstruction and the analysis process, it offers ease of use as well as fast and reproducible CT results, in applications ranging from small biological and geological samples to medium-sized industrial components such as injection nozzles or injection molded plastic parts, even with metal inlays.

"Compared with current state-of-the-art phoenix|x-ray nanoCT equipment, the new phoenix system provides significantly better object penetration and image sharpness, as well fewer imaging artifacts and anomalies because of its extremely high long-term stability. Moreover, due to its excellent contrast-to-noise ratio, CT scans can be performed up to four times faster for the same resolution and image quality," said Oliver Brunke, product manager for CT at GE’s Inspection Technologies business.

nanoCT of through-silicon-vias (50µm diameter) in an electronic package revealing voids in the copper filling.

The nanotom m incorporates a new phoenix 180kV/15W, high-power nanofocus X-ray tube, which is optimized for long-term stability and allows scanning of high absorbing materials such as metals and ceramics. The internal cooling of the tube also significantly reduces thermal effects such as drift, to ensure even sharper imaging as well as allowing the long scanning times frequently required in scientific research.

The new CT system also features a high dynamic range, typically five times better than current state-of-the-art nanoCT equipment, because of its temperature-stabilized, 3072 x 2400 pixel DXR 500L detector from GE. With such a large detector area, this allows sample sizes of up to 250 x 240 mm and the combination of proprietary GE technology in terms of X-ray tube, detector, generator and CT software ensures that a voxel size of down to 300 nm (0.3 µm) can be achieved.

The phoenix nanotom m can also be supplied with a comprehensive 3D metrology package. This is optimized for stable and reproducible environmental and acquisition conditions and provides fast reconstruction and precise measurement results within minutes. It comprises an air-conditioned cabinet and a high accuracy direct measuring system  as well as vibration insulation of the manipulator. It also includes a calibration object and GE’s phoenix datos|x 2.0 CT software packages “click & measure|CT” and “metrology”. With datos|x 2.0, the entire CT process chain can be fully automated, reducing operator time by a factor of up to five. Once the appropriate set up is programmed, the whole scan and reconstruction process including volume optimization features or surface extraction, runs without any operator interaction. Furthermore, 3D metrology or failure analysis tasks performed with third party programs can be executed automatically. Once programmed, under normal circumstances, automatic creation of a first article inspection report even with complex internal geometries can be provided within an hour.

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Read more about package inspection and test here.

(November 29, 2010 – Asia Pulse) — Japan’s Fujitsu Semiconductor Ltd. will transfer its flip chip mounting technology to a Chinese group affiliate for system chip assembly.

Flip chip mounting attaches semiconductor chips directly to boards with solder bumps, eliminating the need for metal lead wires. This speeds assembly, enables chips to be designed thinner, and reduces power consumption.

Before the end of the year, the Fujitsu Ltd. (TSE:6702) arm will transfer some of the manufacturing equipment from its main domestic factory in Mie Prefecture to Nantong Fujitsu Microelectronics Co (SSE:002156), a Jiangsu Province joint venture in which the Fujitsu group owns a roughly 20% stake.

This will mark the first time that a leading Japanese chipmaker transfers such advanced mounting technology to China. Fujitsu Semiconductor is doing this to strengthen Chinese operations and better compete with rivals like Texas Instruments Inc. and Renesas Technology Corp., which have bolstered their own production operations in China to cut costs.

Fujitsu Semiconductor will also collaborate with Nantong Fujitsu to open an R&D center in the city of Nantong this December. The company will dispatch engineers to this center so they can work with Chinese counterparts to develop chip assembly technologies meeting the needs of China’s electronics manufacturing service providers.

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(November 23, 2010) — IMAPS 2010 presenter Jae-Woong Nah, research staff member, Packaging Materials Technology, at IBM’s Thomas J. Watson Research Center, briefed ElectroIQ on his conference paper: "Mask and mask-less injection molded solder (IMS) technology for fine-pitch substrate bumping."

Figure 1. Mask IMS method for substrate bumping. SOURCE: IBM

The paper describes the researchers’ work to develop a new pre-solder bumping technology of injection-molded solder (IMS) for fine pitch organic substrates (Figure 1). “Four years ago, IBM introduced C4NP (C4 new process) as a low cost and environmentally friendly process for applying C4s to wafers that are in volume production at IBM," said Nah. IMS is a variation of C4NP for solder deposition on fine-pitch laminates. The manufacturing technology currently in use for bumping on organic substrates is the solder paste stencil printing method. "However, the paste printing method is difficult to extend to <150µm pitch because the flux volume in the solder paste is about 50%," observed Nah. "The flux bridging after stencil printing leads to pre-solder bump bridging after solder reflow, especially with decreasing pitch and/or increasing pre-solder volume."

In an interview with Debra Vogler, senior technical editor, Nah explained how the researchers injected 100% pure molten solder instead of solder paste with a reusable film mask for forming high-volume solder on fine-pitch substrates.

Listen to Nah’s technical discussion: Download (for iPod/iPhone) or Play Now  

"Since only molten pure solder is used instead of solder paste, this method can achieve higher volume solder bumps for a given pitch, and can be used for fine-pitch applications," said Nah. Over the last year, the researchers ran hundreds of singulated laminates through the process and had no solder bridging and no missing bumps. The group demonstrated 70µm height solder bumps above the solder resist on 150µm pitch substrates (4,500 areal arrays in an 11 × 15mm area); it also demonstrated 35µm height solder bumps on an 80µm pitch substrate (15,000 bumps in a 10 × 10mm area).

 

Figure 2. Mask-less IMS method for substrate bumping. SOURCE: IBM

"In addition to the mask IMS process, we developed a mask-less solder bumping process — direct injection of molten solder without a mask,” said Nah (Figure 2). "It is a very simple and reliable process with low cost compared to any other bumping method," said Nah. He explained that the height of the solder bump is smaller than the mask IMS process because it is limited by the solder resist opening volume. "We demonstrated a 15µm solder height over the solder resist by using the mask-less IMS process."

Nah told ElectroIQ about technical challenges that had to be overcome. Because molten solder has a viscosity similar to water and the organic substrate warps, it is important to prevent leakage between the tool head and the mask as well as between the mask and the substrate. “We used a compliant material on the bottom of the tool head and flexible film mask,” explained Nah. “The compliant material creates a sliding seal between the tool head and the film mask, and the flexible mask follows any non-flat contours on the substrate under the influence of the compressive force that is distributed by the compliant material.” Nah also notes that in the mask-less IMS process, the low friction compliant material is important because the solder resist surface is very rough compared to the film mask. "The mask-less process today is perfect for applications that don’t require large solder volumes — and at a significant cost saving."

Nah believes that the IMS method redefines the role of solder bumping on a substrate. "The IMS method can provide a very large solder volume on substrates and it can reduce the chip bump volume, and potentially eliminate the wafer bumping process," observes Nah. As a result, the decrease in bump volume on the chip reduces the total package cost. "In the case of Cu pillars, the decrease in the Cu pillar height can reduce the stress on back-end-of-line during the flip-chip assembly process, in addition to decreasing the Cu die bumping cost."

Nah told ElectroIQ that IBM is working with another company to commercialize the process and they will have tooling available for large size substrate by sometime next year. "You will see a prototype tool using IMS technology next year," said Nah.

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(November 23, 2010 – Marketwire) — Mattson Technology Inc. (NASDAQ: MTSN), advanced semiconductor manufacturing process equipment supplier, received a repeat order for the Alpine etch system from a leading semiconductor manufacturer. The system, which is scheduled to ship in November 2010, will be used in the customer’s leading-edge 300mm packaging facility in Asia for advanced wafer-level packaging processes.

"The Alpine was again selected by this leading semiconductor manufacturer for its ability to provide the process and technology solution for key etch steps to meet this customer’s advanced packaging requirements," said Rene George, vice president and general manager of Mattson Technology’s Plasma Products Group. "The system’s temperature and material removal control enable back-end wafer-level packaging customers to address increasingly challenging integration processes related to wafer bumping and 3D packaging processes."

George continued, "The customer chose our reliable, high-productivity Alpine etch system based on its significant productivity and cost-of-ownership advantages over competitive systems for packaging applications. This repeat order validates Mattson Technology’s strengthening position in the 300mm packaging market. We look forward to supporting our long-time customer with state-of-the-art process technologies on cost-effective systems to address its development and production needs in advanced packaging."

Mattson Technology Inc. designs, manufactures and markets semiconductor wafer processing equipment used in the fabrication of integrated circuits, primarily Dry Strip, Rapid Thermal Processing and Etch. Internet: www.mattson.com.

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(November 22, 2010) — NovaCentrix announced that Metalon ICI-020, a new copper-based screen ink, will be featured at Printed Electronics USA 2010 in Santa Clara, CA, November 30-December 2, 2010. Pre-printed samples of Metalon ICI-020 screen ink on card stock will be distributed with the registration packs by IDTechEx staff, and attendees may bring their samples to the NovaCentrix exhibit area to cure the ink with NovaCentrix’s PulseForge process tool.
 
"This new ink is the proper next step for printed electronics conductive materials development. By combining low cost, high performance, use with paper-based substrates and deposition by screen printing, the Metalon ICI-020 screen ink expands the practical utility of printed electronics,” said Stan Farnsworth, VP Marketing. "This event’s size and the diversity of attendees representing all aspects of the development and supply chain makes it the perfect venue to launch this revolutionary new screen-print ink."
 
The Metalon ICI-020 screen ink is based on the same functional principles as the Metalon ICI-003 inkjet ink.  Copper oxide particles are formulated with a reduction agent. After the ink is printed, a PulseForge tool is used to modulate a reduction reaction thereby converting the copper oxide into a thin film of highly conductive copper. Importantly, this process is performed in ambient air on low temperature substrates at speeds exceeding 100 meters/minute. NovaCentrix received an R&D 100 award in 2010 for its development of this technology as well as recognition by IDTechEx in April of this year at the Printed Electronics Europe event in Dresden, Germany.
 
NovaCentrix, based in Austin, Texas, is a leader in printed electronics manufacturing technologies. The Company’s PulseForge tools sinter functional inks in milliseconds on low-temperature, flexible substrates such as paper and plastic. NovaCentrix’s tools process a wide array of metal-based conductive inks, as well as non-metallic and semiconductor inks. NovaCentrix also offershigh-performance, economical Metalon conductive inks which work optimally with PulseForge tools. To learn more, please visit www.novacentrix.com.

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(November 18, 2010) — Advanced Packaging’s senior technical editor Debra Vogler asked Tarun Verma, senior director, packaging engineering at Altera, to comment on the MEPTEC Semiconductor Packaging Roadmaps conference (11/10/10, Santa Clara, CA).

Listen to Verma’s recap: Download (iPhone/iPod) or Play Now

Verma calls collaboration and partnerships across the supply chain critical to tackling interconnect and packaging challenges, which are becoming a larger part of the semiconductor cost equation, and was pleased with the attention the conference presentations brought to the topic.

With respect to technical challenges, Verma observed that copper pillar platform technology, such as that introduced by TI this year, is an essential first step that can set in motion the kind of partnerships and collaboration that will be needed going forward. Additional topics he would like to see covered include standardization, heterogeneous integration, EDA tools, and the cost and business models that will be needed going forward.

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