Category Archives: Wafer Processing

Nanoelectronics research center imec has today announced the opening of its new 300mm cleanroom. With this 4000m2 new facility, imec’s semiconductor research cleanrooms now totals 12,000m2, one of the most advanced research facilities in the world dedicated to scaling IC technology beyond 7nm. This facility will enable imec to keep its global leading position as a nanoelectronics R&D center serving the entire semiconductor ecosystem.  Its global partners including foundries, IDMs, fabless and fablite companies, equipment and material suppliers, will benefit from topnotch semiconductor processing equipment (including alfa and beta tools) to develop innovative solutions for more powerful, high-performing, cheaper and energy-efficient ICs, which are crucial in the evolution of the Internet of Everything and a sustainable digital future.

Extending the existing cleanroom, the new facility complies with the newest standards in the semiconductor industry, and provides additional space for the most advanced tools that will lead innovations in new device and system concepts. Installations of the first tools began in January 2016. The new 300mm cleanroom complements imec’s other production facilities including its bio-nanolabs, neuroelectronics labs, imaging and wireless and electronics test labs, photovoltaic pilot lines, and GaN-on-Si, Silicon photonics and MEMS pilot lines.

“Since our founding in 1984, imec has become the world’s largest independent nanoelectronics research center with the highest industry commitment,” stated Luc Van den hove, president and CEO at imec. “This success is the result of the unique combination of our broad international partner network, including the major global players of the semiconductor industry, top scientific and engineering talent, and imec’s one of a kind infrastructure. The extension of our cleanroom provides our partners with the necessary resources for continued leading edge innovation and imec’s success in the future within the local and global high-tech industry.”

The cleanroom was constructed by M+W, an internationally renowned contractor of  large-scale high-tech infrastructure. The construction was completed in 20 months, and includes a  reflecting facade, from Architect Stéphane Beel, which is intended to integrate the building with the environment. The new cleanroom comprises a total investment (building and equipment) of more than 1 billion euro of which 100 million euro funding from the Flemish Government and more than 900 million euro investments from joint R&D with the leading players from the entire semiconductor industry, totaling more than 90 industrial partners.

new imec center

GLOBALFOUNDRIES today announced the availability of a new set of process design kits (PDKs) with an interoperable co-design flow to help chip designers improve design efficiency and deliver differentiated RF front-end solutions in increasingly sophisticated mobile devices.

GLOBALFOUNDRIES’ RF Silicon-on-Insulator (RF SOI) technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. GLOBALFOUNDRIES’ most advanced RF SOI technology, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications.

The challenges of high-frequency and large-signal design in these applications have increased the need for an interoperable co-design flow. Designed for use with Keysight Technologies’ Advanced Design System (ADS) EDA software, GLOBALFOUNDRIES’ new 7SW SOI PDKs allow designers to edit their designs in ADS using a single Si2 OpenAccess database without any interference.

The RFIC interoperability simplifies the design process by enabling the user to work from a single design database in ADS. This allows the user to edit and simulate schematic designs created in ADS. The same is true for layout where, for example, a user can open an IC layout cell view in ADS, instantiate the cell within a package or module, and then run an electromagnetic simulation on the complete design to validate its overall system performance.

“After releasing the first co-design PDK for our 5PAe silicon germanium offering, we are now extending our coverage of ADS PDK to our most advanced RF SOI technology, 7SW SOI. Our 7SW platform, with superior LNA, switch devices, and trap-rich substrates, offer improved devices reception, interference rejection, and battery life for fewer dropped calls and longer talk time,” said Peter Rabbeni, senior director of RF product marketing and business development at GLOBALFOUNDRIES. “Our RF SOI technology has gained significant industry traction for cellular front-end module applications, and the new RFIC interoperability feature will allow us to provide our 7SW customers additional design flexibility with a single PDK.”

“GLOBALFOUNDRIES customers can now access ADS’ dedicated RF design flow tools based on an OpenAccess based silicon PDK,” said Volker Blaschke, Silicon RFIC product marketing manager, Keysight EEsof EDA. “The new interoperability feature facilitates the design process by using a single OpenAccess design data library, removing redundant steps of keeping the design across different EDA environments in sync.”

Light and electrons interact in a complex dance within fiber optic devices. A new study by University of Illinois engineers found that in the transistor laser, a device for next-generation high-speed computing, the light and electrons spur one another on to faster switching speeds than any devices available.

Milton Feng, the Nick Holonyak Jr. Emeritus Chair in electrical and computer engineering, found the speed-stimulating effects with graduate students Junyi Qiu and Curtis Wang and Holonyak, the Bardeen Emeritus Chair in electrical and computer engineering and physics. The team published its results in the Journal of Applied Physics.

As big data become bigger and cloud computing becomes more commonplace, the infrastructure for transferring the ever-increasing amounts of data needs to speed up, Feng said. Traditional technologies used for fiber optic cables and high-speed data transmission, such as diode lasers, are reaching the upper end of their switching speeds, Feng said.

“You can compute all you want in a data center. However, you need to take that data in and out of the system for the user to use,” Feng said. “You need to transfer the information for it to be useful, and that goes through these fiber optic interconnects. But there is a fundamental switching limitation of the diode laser used. This technology, the transistor laser, is the next-generation technology, and could be a hundred times faster.”

Diode lasers have two ports: an electrical input and a light output. By contrast, the transistor laser has three ports: an electrical input, and both electrical and light outputs.

The three-port design allows the researchers to harness the intricate physics between electrons and light. For example, the fastest way for current to switch in a semiconductor material is for the electrons to jump between bands in the material in a process called tunneling. Light photons help shuttle the electrons across, a process called photon-assisted tunneling, making the device much faster.

In the latest study, Feng’s group found that not only does photon-assisted tunneling occur in the transistor laser, but that it in turn stimulates the photon absorption process within the laser cavity, making the optical switching in the device even faster and allowing for ultra-high-speed signal modulation.

“The collector can absorb the photon from the laser for very quick tunneling, so that becomes a direct-voltage-modulation scheme, much faster than using current modulation,” Feng said. “We also proved that the stimulated photon-assisted tunneling process is much faster than regular photon-assisted tunneling. Previous engineers could not find this because they did not have the transistor laser. With just a diode laser, you cannot discover this.

“This is not only proving the scientific point, but it’s very useful for high-speed device modulation. We can directly modulate the laser into the femtosecond range. That allows a tremendous amount of energy-efficient data transfer,” Feng said.

The researchers plan to continue to develop the transistor laser and explore its unique physics while also forming industry partnerships to commercialize the technology for energy-efficient big data transfer.

Paul Lindner, executive technology director at EV Group, is the recipient of the 2015 European SEMI Award.  Since 1989, the European SEMI Award has been presented to the person or team that made significant contributions to the European semiconductor and related industries.  This award, an industry honor for Lindner, was presented at the SEMI Industry Strategy Symposium Europe 2016 conference held in Nice on 6–8 March.

Paul Lindner was nominated and selected by his peers within the international semiconductor community in recognition of his outstanding contributions in the field of wafer processing equipment.  Lindner led exceptional innovations in wafer bonding technologies at EV Group (EVG).  The process separation between wafer alignment and wafer bonding, developed in 1990, revolutionized wafer bonding technology and has since become an industry standard.  Lindner changed the way the industry builds semiconductors.  Lindner exemplifies EVG’s ongoing effort of “being the first” in exploring new techniques and serving next-generation applications of micro- and nano-fabrication technologies.

“We are very proud of SEMI Member EVG’s achievements in wafer bonding technologies and the contributions that Paul Lindner and his team have made to the semiconductor community,” says SEMI Europe president Laith Altimime.

Lindner heads the R&D, product and project management, quality management, business development and process technology departments at EVG Group. He joined EVG in 1988 as a mechanical design engineer and has since pioneered semiconductor and MEMS processing systems, which have set industry standards.

The European SEMI Award was established more than two decades ago to recognize individuals and teams who have made a significant contribution to the European semiconductor and related industries. Prior award recipients hailed from these companies: Infineon, Semilab, Deutsche Solar, STMicroelectronics, IMEC, Fraunhofer Institute, and more.

GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, announced today that Alain Mutricy has joined the company as senior vice president of the Product Management Group. In this role, Mutricy is responsible for the company’s leading edge and mainstream technology solutions and go-to-market activities for these differentiated products.

Mutricy succeeds Mike Cadigan, who will transition to a newly created role as senior vice president of global sales and business development.

“Alain is an accomplished senior executive with more than 25 years of experience in the consumer electronics, mobile, and semiconductor industries,” said GLOBALFOUNDRIES CEO Sanjay Jha. “He brings a strong portfolio of successes contributing to growth, profitability, and competitiveness for global product organizations, which will help him build on the strong foundation we have already established in our product management group. I am thrilled to welcome Alain to the GlobalFoundries team.”

Before joining GlobalFoundries, Mutricy was founder and executive adviser at AxINNOVACTION, a consulting firm that promotes action to unlock and accelerate innovation in big organizations, as well as co-founder and CEO of Vuezr, which attempted to revolutionize mobile direct marketing by delivering product visual recognition to consumers’ mobile devices via augmented reality.

From 2007-2012, Mutricy served as senior vice president of portfolio and device product management for mobile devices at Motorola Mobility Holdings, Inc., where he led a global team responsible for defining the company’s mobile devices product portfolio strategy and structure. He and his team advanced a strategic focus on Android-based smartphones, which included the widely acclaimed family of DROID by Motorola products. During his tenure at Motorola Mobility, Mutricy was also responsible for defining and directing the Mobile Devices business unit’s global strategy for silicon and software platforms, as well as leadership of a global R&D team responsible for designing and implementing integrated circuits, wireless chipset solutions, platform software, product software for non-CDMA products, and an ecosystem strategy for mobile devices.

Prior to joining Motorola in 2007, Mutricy served at Texas Instruments for 18 years, where he was promoted to vice president in January 2002. From 2004 until his departure from Texas Instruments, Mutricy served as vice president and general manager for the company’s Cellular Systems Solutions business. In that role, he was responsible for commercializing and building a leadership position for the company’s wireless chipset solutions for GSM/GPRS/EDGE/3G and OMAP application processors. Prior to leading Cellular Systems Solutions, Mutricy was general manager for the Texas Instruments OMAP business, which he led from start-up status to global leadership between 2000 and 2004. Additionally, from the time he joined Texas Instruments in 1989, Mutricy was promoted through a series of general- management positions, each with increasing scope and responsibility in areas including sales, marketing and general management.

Mutricy holds a master’s degree in engineering from ENSAM and an MBA from HEC Group—both in Paris.

Toppan Printing Co., Ltd. announced it has developed a next-generation EUV photomask for semiconductors.

The new photomask minimizes the unwanted reflection of light to peripheral sections during EUV exposure, a next-generation semiconductor manufacturing technology. Sample shipments to semiconductor manufacturers will begin in fiscal 2016, with the start of full-scale mass production slated for fiscal 2017.

Based on this technology, Toppan Printing is aiming to establish the industry standard for next-generation EUV photomasks. This development marks the first time anywhere in the world that a structure to suppress the unwanted reflection of light to peripheral sections has been created on the surface of an EUV photomask, and the areas around the pattern have been miniaturized.

By further developing and fusing its microfabrication and optical design technologies, Toppan Printing has become the first company in the world to form a special 3D structure on the light-shielding black border on the surface of an EUV photomask and reduce the reflection of OOB light by approximately 70% compared with conventional products. Transfer testing using EUV exposure machinery manufactured by ASML has verified that this new EUV photomask can reduce dimension variability on silicon substrates by two-thirds. As a result, it enables improvements in quality and yield for semiconductor patterns.

A team of researchers, led by a group at the University of California, Riverside, have demonstrated for the first time the transmission of electrical signals through insulators in a sandwich-like structure, a development that could help create more energy efficient electronic devices.

Conventional electronic devices rely on the transport of electrons in a semiconductor such as silicon. Now, researchers are exploiting the ‘spin’ of the electron rather than its charge to create a new generation of ‘spintronic’ devices that are potentially more energy efficient and more versatile than those currently making up silicon chips and circuit elements.

The UC Riverside-led research, which was published online Wednesday (March 2) in the journal Nature Communications, is significant because it demonstrates that a tri-layer, sandwich-like, structure can serves as a scalable pure spin current device, an essential ingredient in spintronics.

A key element in this breakthrough is the material. To demonstrate the effect, the magnetic insulator needs to be truly insulating, or there will be a parasitic signal from leakage. On the other hand, a high-quality magnetic insulator grown on metal had never been demonstrated.

Using combination of sputtering (for metals) and pulsed laser deposition (for insulator), we successfully showed that the 50-100 nanometer thick magnetic insulator, such as yttrium iron garnet, is not only magnetic and insulating, but also of high quality when it is grown on 5 nanometer thick platinum.

In the structures used by the researchers, there are two metals and a magnetic insulator in between. The metals are for spin current generation and detection (conversion of spin current back to charge current) via the so-called spin Hall effect and inverse spin Hall effect.

The magnetic insulator is an electrical insulator but a good spin current conductor. The spin current flowing in the insulator does not involve mobile electrons therefore it does not dissipate energy as an electrical current does in joule heating.

The researchers have also demonstrated that the signal transmission can be switched on and off and modulated in its strength by a magnetic field. The electrical signal transmission through the magnetic insulators can be switched on and off depending on the magnetic state, or direction of the magnetization, of the magnetic insulators.

So the direction of the magnetization can be regarded as a memory state of non-volatile random access memory devices. In addition, the signal level can be modulated by changing the direction of the magnetization; therefore, it can also be used as analog devices. The sandwich structure can be made small by nanofabrication so that the devices can be scaled down.

IC Insights recently released its new Global Wafer Capacity 2016-2020 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, by process geometry, by region, and by product type through 2020.  Figure 1 breaks down the world’s installed monthly wafer production capacity by geographic region (or country) as of December 2015.  Each regional number is the total installed monthly capacity of fabs located in that region regardless of the headquarters location for the companies that own the fabs.  For example, the wafer capacity that South Korea-based Samsung has installed in the U.S. is counted in the North America capacity total, not in the South Korea capacity total.  The ROW region consists primarily of Singapore, Israel, and Malaysia, but also includes countries/regions such as Russia, Belarus, Australia, and South America.

Figure 1

Figure 1

Some highlights of regional IC capacity by wafer size are shown below.

As of Dec-2015, Taiwan led all regions/countries in wafer capacity with nearly 22% of worldwide IC capacity installed in the country.  Taiwan surpassed South Korea in 2015 to become the largest capacity holder after having passed Japan in 2011.  China became a larger wafer capacity holder than Europe for the first time in 2010.

For wafers 150mm in diameter and smaller, Japan was the top region in terms of the amount of capacity.  The fabs running small size wafers tend to be older and typically process low-complexity, commodity type products or specialized devices.

The capacity leaders for 200mm wafers were Taiwan and Japan.  There have been many 200mm fabs closed over the past several years, but not in Taiwan and that resulted in the country becoming the largest source of 200mm capacity beginning in 2012.  With Taiwan being home to most of the IC industry’s foundry capacity, the country’s share of 200mm capacity will likely rise further in the coming years.

For 300mm wafers, South Korea was at the forefront, followed by Taiwan.  Taiwan lost its position as the leading supplier of 300mm wafer capacity in 2013.  That was in large part because ProMOS closed its large 300mm fabs, but it was also due to Samsung and SK Hynix continuing to expand their fabs in South Korea to support their high-volume DRAM and flash businesses.

Mentor Graphics Corp. ushered in a new era of emulation by announcing new applications for the Veloce emulation platform. The new Veloce Apps—Veloce Deterministic ICE, Veloce DFT and Veloce FastPath—overcome critical system-level verification challenges in complex SoC and system designs. They run on an upgraded Veloce OS3 operating system that significantly accelerates design compile cycles, gate-level flows, and the time it takes to review results (“time to visibility”). The combination of Veloce Apps on Veloce OS3 puts more capabilities into the hands of more engineers more quickly than hardware-centric strategies.

Each of the new Veloce Apps addresses a specific verification issue:

  • Veloce Deterministic ICE overcomes unpredictability in In-circuit Emulation (ICE) environments by adding 100% visibility and repeatability for debug, and provides access to other ‘virtual-based’ use models;
  • Veloce DFT accelerates Design for Test (DFT) verification prior to tape-out to
    minimize the risk of catastrophic failure, and significantly reduces run times when verifying designs after DFT insertion; and
  • Veloce FastPath optimizes emulation performance when verifying large multi- clock SoC designs by enabling faster model execution speed.

These new Veloce Apps join Veloce Power, Veloce Enterprise Server and other apps in an expanding arsenal of software innovations for the Veloce emulation platform. Mentor will continue to expand the library of Veloce Apps to introduce new ways to ensure designs meet their functional and performance specifications on schedule.

The new Veloce Deterministic ICE, Veloce DFT and Veloce FastPath applications expand the Veloce Apps library to put more emulation capabilities the hands of more engineers.

The new Veloce Deterministic ICE, Veloce DFT and Veloce FastPath applications expand the Veloce Apps library to put more emulation capabilities the hands of more engineers.

The Veloce OS operating system adds software programmability and resource management to the Veloce platform, making it easier to add new use models that increase the ROI of the emulator. The recent upgrade of Veloce OS3 covers several innovations:

  • Integration of new High Performance Computing platforms cuts compile time by 50%.
  • A faster gate-level flow operates as “plug-and-play”—able to accept flat or hierarchical designs. This flow reduces the amount of memory needed for compilation, which improves performance. By making it easier to load and verify gate-level designs, the new flow improves confidence in silicon fidelity.
  • The combination of software and hardware improvements spanning the run time and debug cycles achieves 200% faster time-to-visibility.

These new Veloce emulation capabilities demonstrate how innovative software, running on powerful, qualified hardware and an extensible operating system, can target design risks faster than hardware-centric strategies. As emulation enters its fourth decade and expands across mainstream markets, the Veloce emulation platform has become a powerful resource across a range of hardware, software and system verification flows.

“Mentor continues to demonstrate its technology leadership through its application-based strategy for the Veloce emulation platform,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “These latest innovations accelerate overall verification throughput performance for our customers. The focus on software apps for specific SoC and system-level challenges is driving the future of emulation.”

About the Veloce emulation platform

The Veloce emulation platform is a core technology in the Mentor Enterprise Verification Platform (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform.

Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system- level prototyping, low-power verification and power estimation and performance characterization.

The Semiconductor Industry Association (SIA) applauded congressional approval of the Trade Facilitation and Trade Enforcement Act of 2015 (H.R. 644/S.1269), bipartisan Customs legislation that includes a key provision to combat counterfeit semiconductors. The bill requires U.S. Customs and Border Protection (CBP) to expeditiously share information and samples of suspect counterfeit parts – including semiconductors – with rights holders, enabling quick identification of counterfeits.

“Counterfeit semiconductors pose significant risks to public health, safety, and national security,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Customs bill Congress approved today will help reduce this risk and root out counterfeit semiconductors by ensuring open communication between Customs officials and semiconductor manufacturers, who are best-equipped to identify counterfeits. This legislation is good news for the semiconductor industry and consumers of our products – and bad news for semiconductor counterfeiters.”

Semiconductors are embedded into countless products and systems that perform critical functions in our society, and the failure of a single component in one of these products or systems can have dangerous consequences. SIA has long advocated for a multi-pronged approach to combatting counterfeit semiconductors. In December, SIA urged House and Senate leaders to approve the Customs legislation in order to better help identify shipments of counterfeits.

CBP has previously redacted images of suspect counterfeit semiconductors and delayed sharing information with companies that play a vital role in determining if parts are counterfeit and require seizure. Enactment of this legislation would allow CBP to use the expertise of rights holders in determining if parts are counterfeit, thereby helping prevent counterfeit products from entering the United States.

The threat of counterfeit semiconductors can also be greatly reduced by buying semiconductor products either directly from Original Component Manufacturers (OCMs) or their authorized distributors or resellers. This was the chief recommendation of SIA’s anti-counterfeiting white paper.

“We applaud Congress for approving this bipartisan legislation and urge the President to sign it into law in short order,” Neuffer said. “Doing so will help ensure the safety and security of technologies that are critical to America’s economic and national security.”