Category Archives: Wafer Processing

By Wilfried Vogel, NETA

Downsizing and thinning all the electronic parts has always been a trend in our modern era. However, the nanoscience and nanotechnologies were still science fiction in the 60’s and the word nanotechnology was used for the first time in 1974. At the same time, the first atomic force microscopes (AFM) and scanning acoustic microscopes (SAM) were developed. Today nanotechnologies represent huge investments –  even from governments – and a global market of several thousand of billions of euros.

Non-destructive testing at the nanometric scale is the purpose here. Ultrasounds are widely used in the aeronautics industry or during medical echography. The spatial resolution reached in that case is around the millimeter which is a million time too large when we speak of nanotechnologies.

SAM systems benefit from a higher definition thanks to MHz/GHz ultrasounds, the smallest axial resolution found on the market is below the micron.

The nanometric world requires another 2 to 3 orders of magnitude below and it can only be reached thanks to THz ultrasounds. These frequencies cannot be generated with standard transductors, that’s why the ASynchronous OPtical Sampling (ASOPS) systems are equipped with ultrafast lasers.

This complex technology is now available on the market in a compact instrument. The JAX is the first industrial imaging ASOPS system (Fig. 1).

When the laser hits the surface, the most part of the energy is absorbed by the first layers of atoms and converted into heat without damaging the sample (Fig. 2), leading to transient thermoelastic expansion and ultrasound emission.

The choice of the probe is also important to keep the temporal and the spatial resolution as low as possible, that’s why another ultrafast laser is used as a probe (Fig 3.).

The ultrasound is propagating a few nanometers per picosecond through the thin film and at some point will bounce back partially or completely to come back to the surface when meeting a different medium.

The probe laser is focused at the surface, when the ultrasound hits back the surface, the reflectivity fluctuates locally over time.

The variation of reflectivity is detected and stored into the computer as a raw data.

The technique is often called picosecond ultrasonics, it has been developed at Brown University in the USA by Humphrey Maris in the mid 80’s.

The ASOPS is not the only kind of technology able to perform picosecond ultrasonics, but it’s the latest evolution and the fastest to perform a full measurement. The trick here is to slightly shift the frequency of the probe laser compared to the pump’s one (Fig. 4). Both lasers are synchronized by a separate electronical unit. The probe arrives slightly after the pump and this delay is extending with time until the whole sampling is over.

The elastic answer of the thin film to a pump excitation is too fast to be measured in real time. You have to artificially extend time and reconstruct the signal of the probe.

The measure described above is for one single point. With a more standard instrument able to perform picosecond ultrasonics, it would take several minutes. Here with the ASOPS, the measure takes less than a second. It means that by simply scanning point by point all over the surface (Fig. 5), you will get a full map of the studied mechanical parameter in minutes.

Thickness measurement

For instance if your interest is in the thickness of a thin film, you can easily retrieve an accurate value by measuring the time between two echoes of the ultrasound at the surface of the sample (Fig. 6).

Until recently, the kind of setup required to make these measurement was found in a optical lab with a large honeycomb table full of mirrors and lenses. Even though the results are respectable, the time to install and repeatability are often the main issue.

Hopefully the technology is now accessible for non-specialists who just want to focus on measuring the mechanical properties of their samples and not to take care of all the optical part. The industrialization of such an innovative and complex device is giving an easy access to new information.

Since a punctual measurement takes a few milliseconds, it is easily feasible to measure all over the surface of the sample and get a full mapping of the thickness.

In the examplebelow (Fig. 7), the sample consists of a 500 µm silicon substrate and 255 nm sputtered tungsten single layer. The scanned surface is approximately 1.6 mm x 1.6 mm and the lateral resolution in X-Y is 50 µm, 999 points in total.

A large scratch is being highlighted at the surface but the average thickness remains in the range of 250 nm. The total time of measurement is less than 10 minutes, which is comparable to a single point measurement with one laser and a mechanical delay line (homodyne system).

Until now, the industry offer for production management was only homodyne instruments performing picosecond ultrasonics measurements, reducing the full scan of the surface to a very few points checked only over a full wafer.

We just saw that single layer thin film thickness measurement is pretty straight forward. If you are dealing with more than one layer the raw data is much more complex to read. However, it is possible to model the sample and to compare the simulated signal to the actual measure with an incredible fit.

Multiphysics

When you chat with several experts of thin films, they will all agree to tell you that:

  • Thickness is a key parameter
  • Adhesion is always a problem
  • Non-destructive measurement is a fine improvement
  • Faster is better
  • Imaging is awesome

In the industry, thickness and adhesion are the main concern at all steps of the manufacturing process, whether you are working in the display or the semiconductor field. The picosecond ultrasonics technique is already used in-line for wafer inspection, which shows its maturity and yet confidentiality.

The standard procedures for adhesion measurement are applicable only on flat and large samples, and they are destructive. When it comes to 3D samples and if you want to check the adhesion on a very small surface, the laser is the only solution. Adhesion can now be verified inline all over the sample during every step of the manufacturing process.

Now the academic world has different concerns and goes deeper and deeper in the understanding of the material behavior at the atomic scale.

The ASOPS system can go beyond the picosecond ultrasonics – which is already a great source of information if we stick to thickness and adhesion –  and get even more from the raw data such as thermal information or critical mechanical parameters.

Thermal conductivity

Thermal conductivity is the parameter representing the heat conducting capability of a material.

Thin films, superlattices, graphene, and all related materials are of broad technological interest for applications including transistors, memory, optoelectronic devices, MEMS, photovoltaics  and more. Thermal performance is a key consideration in many of these applications, motivating efforts to measure the thermal conductivity of these films. The thermal conductivity of thin film materials is usually smaller than that of their bulk counterparts, sometimes dramatically so.

Compared to bulk single crystals, many thin film have more impurities which tend to reduce the thermal conductivity. Besides even an atomically perfect thin film is expected to have reduced thermal conductivity due to phonon leakage or related interactions.

Using pulsed lasers is one of the many possibilities to measure the thermal conductivity of a thin material. The time-domain thermoreflectance (TDTR) is a method by which the thermal properties of a material can be measured. It is even more suitable for thin films materials, which have properties that vary greatly when compared to the same materials in bulk.

The temperature increase due to the laser can be written as follows:

∆T(z)=(1-R) Q/(C(ζA)) exp⁡(-z/ζ)

where R is the sample reflectivity,
Q is the optical pulse energy,
C is the specific heat per unit volume,
A is the optical spot area,
ζ is the optical absorption length,
z is the distance into the sample

The voltage measured by the photodetector is proportional to the variation of R, it is possible then to deduce the thermal conductivity.

In some configuration, it can be useful to shoot the probe on the bottom of the sample (Fig. 7) or vice versa in order to get more accurate signal from one side or the other of the sample.

Surface acoustic wave

When the pump laser hits the surface, the ultrasound generated is actually made of two distinct waves modes, one propagating in the bulk, which is called longitudinal (see Fig. 1), one traveling along the surface, it’s called the Rayleigh mode.

In the industry the detection of surface acoustic wave (SAW) is used to detect and characterize cracks.

The surface wave is very sensitive to the presence and characteristics of the surface coatings, even when they are much thinner than the penetration depth of the wave. Young Modulus can be determined by measuring the velocity of the surface waves.

The propagation velocity of the surface waves, c, in a homogeneous isotropic medium is related to:

– the Young’s modulus E,
– the Poisson’s ratio ν,
– the density ρ

by the following approximate relation c=(0.87+1.12ν)/(1+ν) √(E/(2ρ(1+ν)))

When using an industrial ASOPS system to measure and image the SAW, the pump laser is fixed (Fig. 8) and always hitting the same spot.

The probe is measuring its signal around the pump laser thanks to a scanner installed in the instrument.

Future challenges

We had a quick overview of some applications and parameters that can be measured with an industrial  ASOPS imaging system. Of course it was not exhaustive, we could think for instance of adding Brillouin scattering detection in transparent material and more.

Today, ASOPS technology is moving from the margin to the mainstream. The academic community already recognizes this non-destructive technology as truly operational and able to deliver reliable and accurate measurements. For industrial applications, ASOPS systems will most certainly begin to replace standard systems in the short term and to fill the gap of ultrasonic inspection at nanometric scale.

Besides it is easily nestable in the production line while some other instruments are meant to remain research devices because they require much more care, vacuum pumps, complex settings etc.

However, the industry is far from done exploiting the full range of capabilities offered by ASOPS systems, this versatile technology also continues to be developed and validated for a broad range of other critical applications. Indeed, ASOPS systems has already shown a great potential on biological cell research. We can expect new developments to be done in the future and see instruments help the early disease detection within the next few years.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom and analog/mixed-signal (AMS) IC design tools have achieved certification for Samsung Foundry’s 7nm Low Power Plus (7LPP) process technology. This certification ensures Cadence and Samsung Foundry mutual customers of a highly automated circuit design, layout, signoff and verification flow with full extreme ultraviolet lithography (EUV) support. This certification complements the earlier announced certification of the Cadence® full-flow digital and signoff tools on Samsung 7LPP process technology.

The Cadence custom and AMS flow includes the Virtuoso® Analog Design Environment (ADE), Virtuoso Schematic Editor, Virtuoso Layout Suite with its Advanced-Node Platform, Virtuoso Space-Based Router, Spectre® Circuit Simulator, Voltus™-Fi Custom Power Integrity Solution, Quantus™ Extraction Solution, Physical Verification System, Litho Physical Analyzer, Cadence CMP Predictor and LDE Electrical Analyzer. These tools can be used throughout the complete custom AMS flow, including:

  • Custom layout design: An advanced, electro-migration and parasitic-aware environment that includes device and module generation, automated placement and routing, layout editing, and dynamic DRC checking with Virtuoso Integrated PVS DRC, interactive PVS metal fill, in-design DFM flows for LDE, process hotspot repair (PHR), pattern analysis and optimization, and chemical mechanical polishing (CMP) check, as well as support for correct-by-design multiple patterning flow.
  • Post-layout parasitic simulation and IR drop (IREM) analysis and integrated signoff: Including parasitic extraction, design rule checks, layout versus schematic checks, dummy metal fill and programmable electrical rule checks (PERC).
  • AMS design: Digital standard cell placement, pin optimization and automated space-based routing.

“In close collaboration with Samsung, we have delivered a certified, integrated flow for custom and AMS design at 7LPP technology based on our industry-leading Virtuoso and Spectre platforms,” said Wilbur Luo, Cadence vice president, product management, analog/custom marketing. “Samsung customers can now take advantage of the most advanced features for circuit design, performance and reliability verification, and automated layout, block and chip integration for custom and digitally controlled analog designs.”

“By working closely with Cadence, we can provide our customers the most advanced FinFET performance for their custom and AMS chip designs,” said Ryan Lee, vice president of Foundry Marketing at Samsung Electronics. “Cadence helps us offer our customers the best power, performance and area for their leading-edge designs.”

ClassOne Technology, a supplier of new wet process tools to the 200mm and below semiconductor manufacturing industry, today announced the sale of its flagship Solstice® S8 wet process tool to the Ferdinand-Braun-Institute (FBH) in Berlin, Germany. As a leading research institute in the fabrication of III-V compound semiconductors, FBH specializes in prototyping leading-edge microwave and optoelectronic devices for a diverse range of industries, including communications, energy, health, and mobility.

“Solstice is a perfect fit for the III-V compound semiconductor processes that FBH specializes in,” explains Olaf Krüger, Head of FBH’s Process Technology Department. “The exceptional flexibility of the Solstice platform will allow FBH to efficiently automate a number of distinct processes on a single tool. We expect to retain the fine-grained control needed in our research environment with the added production benefits of complete cassette-to-cassette automation.“

FBH is the latest example of a growing trend in the compound semiconductor industry—the need for integrated plating-related processes as part of a comprehensive plating solution. ClassOne’s eight-chamber Solstice S8 will provide FBH with sophisticated electroplating and wet processing capabilities for a range of processes. In particular, gold plating will be performed by a pair of ClassOne’s class-leading GoldPro™ chambers, and a new high-pressure spray solvent chamber will process highly-efficient Metal Lift-off. ClassOne has dubbed the wide range of plating-related wet processing capabilities on the Solstice platform as Plating-PlusTM.

“The configuration flexibility of Plating-PlusTM and the exceptional quality of our plating chambers are why ClassOne has become the supplier of choice for the compound semiconductor industry,” says Roland Seitz, Director of ClassOne’s European Operations. “Solstice is perfectly suited to the complex processing requirements of compound semiconductors. By placing several related processes on a single tool, FBH will enjoy processing efficiencies and device quality that simply cannot be achieved by any other supplier.”

North America-based manufacturers of semiconductor equipment posted $2.09 billion in billings worldwide in September 2018 (three-month average basis), according to the September Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 6.5 percent lower than the final August 2018 level of $2.37 billion, and is 1.8 percent higher than the September 2017 billings level of $2.05 billion.

“Quarterly global billings of North American equipment suppliers experienced their typical seasonal weakening in the most recent quarter,” said Ajit Manocha, president and CEO of SEMI. “Relative to the third quarter, we expect investment activity to improve for the remainder of the year.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg.)
Year-Over-Year
April 2018
$2,689.9
25.9%
May 2018
$2,702.3
19.0%
June 2018
$2,484.3
8.0%
July 2018
$2,377.9
4.8%
August 2018 (final)
$2,236.8
2.5%
September 2018 (prelim)
$2,091.9
1.8%

Source: SEMI (www.semi.org), October 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ).

By Jay Chittooran

Last week, the Office of the U.S. Trade Representative (USTR), on instruction from President Trump, notified Congress that the administration intends to begin bilateral trade negotiations with Japan, the European Union (EU), and the United Kingdom.

SEMI stands strong for free trade and open markets, and roundly supports efforts to increase market access and tap into more foreign economies, especially economies like Japan and the EU, both of which are central to the semiconductor industry. The semiconductor industry, which enables the $2 trillion electronics market, is built on global commerce. SEMI members rely on a vast network of supply chains that span the globe, bringing together components and tools made all around the world and assembled into a single sub-system that is then integrated into a larger tool used in the chipmaking process.

These free trade agreements will reduce tariffs, which will result in cost savings and productivity gains, and allow SEMI members to expand and grow. But the benefits of modern free trade agreements extend well beyond tariff reduction. Indeed, these trade deals will establish and enhance global trade rules that enable companies to innovate and compete fairly on a level playing field. Trade agreements strengthen certainty and further business continuity.

While the exact nature and negotiation timelines for the talks remain unclear, SEMI will engage the administration, urging it to maintain high standards in these agreements, such as:

  • Maintain strong respect for intellectual property and trade secrets through robust safeguards and significant penalties for violators
  • Remove tariffs and non-tariff barriers on semiconductor products as well as products that depend on semiconductors
  • Simplify and harmonize the customs and trade facilitation processes
  • Combat any attempts of forced technology transfer
  • Prevent use of data localization measures and enable the free flow of cross-border data flows
  • End discriminatory and/or burdensome regulatory practices
  • Ensure standards in all forms are market-oriented
  • Create rules for state-owned enterprises to ensure fair and non-discriminatory treatment of all companies

According to Trade Promotion Authority (TPA), the U.S. law that guides trade votes in Congress, negotiations with each country can only begin 90 days after last week’s notification. During that period, there will be intensive consultation with Congress and stakeholders. This means, at the earliest, talks can start on January 14, 2019. (Bear in mind that discussions with the UK can only begin in earnest once the UK has formally left the European Union on March 29, 2019.)

The Trump administration’s announcement comes after the U.S. imposed or threatened tariffs on imports on all trading partners, including the EU and China. All told, the U.S. has imposed tariffs on more than $300 billion worth of goods. SEMI has weighed in on the detrimental nature of tariffs, arguing that tariffs on China will ultimately do nothing to address the concerns with China’s trade practices. This sledgehammer approach will introduce significant uncertainty, impose greater costs, and potentially lead to a trade war, ultimately undercutting the ability of semiconductor companies to sell overseas, stifling innovation and curbing U.S. technological leadership.

Elsewhere, the Comprehensive and Progressive Agreement for Trans-Pacific Partnership, the multilateral trade deal that links 11 Asia-Pacific economies, is well on its way to taking force. Canada will be taking its final steps to ratify the deal, joining Mexico, Japan and Singapore. The deal, formerly known as the Trans-Pacific Partnership, should take effect by the first half of 2019.

SEMI will continue tracking ongoing trade developments. Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Samsung Electronics Co., Ltd. today announced several groundbreaking additions to its comprehensive semiconductor ecosystem that encompass next-generation technologies in foundry as well as NAND flash, SSD (solid state drive) and DRAM. Together, these developments mark a giant step forward for Samsung’s semiconductor business.

Unveiled at its annual Samsung Tech Day include:

  • 7nm EUV process node from Samsung’s Foundry Business, providing significant strides forward in power, performance and area.
  • SmartSSD, a field programmable gate array (FPGA) SSD, that will offer accelerated data processing and the ability to bypass server CPU limits.
  • QLC-SSD for enterprise and datacenters that offer 33-percent more storage per cell than TLC-SSD, consolidating of storage footprints and improving total cost of ownership (TCO).
  • 256-gigabyte (GB) 3DS (3-dimensional stacking) RDIMM (registered dual in-line memory module), based on 10nm-class 16-gigabit (Gb) DDR4 DRAM that will double current maximum capacity to deliver higher performance and lower power consumption.

“Samsung’s technology leadership and product breadth are unparalleled,” said JS Choi, President, Samsung Semiconductor, Inc. “Bringing 7nm EUV into production is an incredible achievement. Also, the announcements of SmartSSD and 256GB 3DS RDIMM represent performance and capacity breakthroughs that will continue to push compute boundaries. Together, these additions to Samsung’s comprehensive technology ecosystem will power the next generation of datacenters, high-performance computing (HPC), enterprise, artificial intelligence (AI) and emerging applications.”

Advanced Foundry Technology

Initial wafer production of Samsung’s 7nm LPP (Low Power Plus) EUV process node represents a major milestone in semiconductor fabrication. The 7LPP EUV process technology provides great advances, including a respective maximum of 40-percent area reduction, 50-percent dynamic power reduction and 20-percent performance increase over 10nm processes. The 7LPP process represents a clear demonstration of the foundry business’ technology roadmap evolution, providing Samsung’s customers a direct path forward to 3nm.

Powering Server-less Computing

Samsung enables the most advanced providers of server-less computing through products including the new SmartSSD, quad-level cell (QLC)-SSD, 256GB 3DS RDIMM as well as High Bandwidth Memory (HBM) 2 Aquabolt. By accelerating data processing, bypassing server CPU limits and reducing power demands, these products will enable datacenter operators to continue to scale at faster speeds while containing costs.

Samsung’s industry-leading flash memory products for future datacenters will also include Key Value (KV)-SSD and Z-SSD. KV-SSD eliminates block storage inefficiency, reducing latency and allowing datacenter performance to scale evenly when CPU architectures max out. The company’s next-generation Z-SSD will be the fastest flash memory ever introduced, with dual port high availability, ultra-low latency and a U.2 form factor, designed to meet the emerging needs of enterprise clients. Z-SSD will also feature a PCIe Gen 4 interface with a blazing-fast 12-gigabytes-per-second (GB/s) sequential read, which is 20 times faster than today’s SATA SSD drives.

Accelerating Application Learning

A range of revolutionary Samsung solutions will enable the development of upcoming machine learning and AI technologies. The Tech Day AI display highlighted astounding data transfer speeds of 16Gb GDDR6 (64GB/s), ultra-low latency of Z-SSD and industry-leading performance of Aquabolt, which is the highest of any DRAM-based memory solution currently in the market. Together, these solutions help Samsung’s enterprise and datacenter clients open new doors to application learning and create the next wave of AI advancements.

Streamlining Data Flow

Samsung’s new solutions will enable not just faster speeds and higher performance but also improved efficiency for its enterprise clients. Enterprise products on display at Tech Day included D1Y 8Gb DDR4 Server DRAM, which incorporates the most advanced DRAM process, resulting in lower power usage. Samsung’s 256GB 3DS RDIMM also helps to improve enterprise performance and enables memory-intensive servers capable up to 16-terabytes (TB).

Additionally, Samsung’s dual-port x4 PCIe Gen 4 32TB SSD offers 10GB/s performance. Samsung’s 1Tb QLC-SSD presents a cutting-edge storage option for enterprise clients with competitive efficiency when compared to hard disk drives (HDD), while KV-SSD allows server performance to scale even as CPU architectures max out, also providing a competitive TCO, write amplification factor (WAF) improvement and scalability.

Breaking Performance Barriers

With their leading-edge specs, Samsung’s QLC-SSD, Z-SSD and 8GB Aquabolt help high-performance computing clients blast through performance barriers and reach new heights. The 8GB Aquabolt provides the fastest data transmission speed and highest performance of any DRAM-based memory solution on the market today at 307GB/s per HBM cube. QLC-SSD and Z-SSD, both powerful on their own, are also offered in a tiered storage solution that results in a 53-percent increase in overall system performance.

Enabling Future Innovation

Emerging tech requires the most innovative and flexible components. Samsung’s SmartSSD will increase speed and efficiency, and lower operating costs by pushing intelligence to where data lives. Movement of data for processing has traditionally caused increased latency and energy consumption while reducing efficiency. Samsung’s new SmartSSDs will overcome these issues by incorporating an FPGA accelerator into the SSD unit. This allows for faster data processing through bypassing server CPU limits. As a result, SmartSSDs will have higher processing performance, improved time-to-insight, more virtual machines (VM), scalable performance, better de-duplication and compression, lower power usage and fewer CPUs per system.

Unparalleled Product Ecosystem

Samsung’s comprehensive product portfolio with state-of-the-art solutions set new standards for data processing speed, capacity, bandwidth and energy conservation. By leveraging such solutions, data centers, enterprise companies, hyper-scalers and emerging tech platforms are able to configure product solutions based on their requirements and develop exciting new tech offerings such as 5G, AI, enterprise and hyperscale data centers, automotive, networking and beyond.

Samsung will continue to push boundaries in tomorrow’s semiconductor technologies through innovations such as its sixth-generation V-NAND built on a single structure, or with ‘1-stack technology,’ and sub-10nm DRAM with EUV for super-high density and performance.

Experts across the industry, including Apple co-founder, Steve Wozniak, were invited at Samsung Tech Day to address the advancements and challenges in today’s semiconductor market, and offer insights for the future of semiconductors. More than 400 customers, partners and industry influencers attended the event.

With tremendous growth of smartphones over the past decade, foundry sales to the communications market have soared and are now forecast to account for about 3x more than IC foundry sales to the computer market in 2018, based on IC Insights’ extensive part-two analysis of the integrated circuit foundry business in the September Update to The 2018 McClean Report (Figure 1).

Figure 1

Ten years ago, computers/computing systems were easily the largest application for pure-play IC foundry sales, but a relatively flat tablet PC market and lackluster desktop and notebook PC sales since 2011 contributed to weak pure-play foundry sales into the computer segment.

Now, new server applications targeting artificial intelligence (AI), the Internet of Things, Cloud Computing, and cryptocurrency are forecast to breathe new life into this market segment over the next five years. TSMC expects its IC sales into the IoT segment will grow by a CAGR of more than 20% from 2017 through 2022 (the company had greater than $1.0 billion in IoT sales in 2017).

Although IC foundry sales for computer applications are expected to surge 41% this year (driven by TSMC’s cryptocurrency device sales), the communications foundry market is still expected to be about 3x the size of the computer segment in 2018.  The communications foundry market is forecast to display only a 2% growth rate in 2018, six points less than the total pure-play foundry market growth rate expected for this year.

Overall, the communications (52%), computer (19%), and consumer (13%) market segments are forecast to represent 84% of the pure-play IC foundry market in 2018.

By Emir Demircan

SEMI today confirmed its support for a Joint-Industry Cooperation on an RoHS Review aimed at urging the European Commission to, at a minimum, consider dedicating more resources to a targeted outreach programme with third countries. The Joint-Statement is as follows:

Since its inception in 2002, the RoHS Directive has become a global reference point for regulation of hazardous substances in electrical and electronic equipment (EEE). This has been effective and given the EU a competitive advantage. The worldwide impact of RoHS is significant and the undersigned associations consider that this should be considered in the roadmap for reviewing the Directive.

RoHS-type laws have been introduced or are currently being introduced in more than 40 jurisdictions outside the European Economic Area (EEA). These include China, India, the Eurasian Customs Union and the Gulf States. Sometimes RoHS is copied exactly. However, often it is not. For example, countries might introduce a completely different approach on the scope, exemptions and declaration of conformity. Each time a new “RoHS” law is proposed, industry has to establish a bi-lateral dialogue with the relevant local public authorities improving the knowledge and understanding of regulatory stakeholders based on experience with the framework legislation in the EEA. Industry continues to spend a lot of time and money to ensure alignment with EU RoHS as far as possible. This is crucial for the global and complex EEE supply chains.

The European Commission’s DG TRADE “Market Access” services have been helpful with draft laws that have been notified to the WTO and have raised concerns with the Technical Barriers to Trade (TBT) Committee as well as bi-laterally with the countries in question. A recent example was the draft legislation in the United Arab Emirates.

Each time the EU updates the legislation, for example, withdrawing, renewing or granting an exemption, adding a substance, this will have a domino effect on the rest of the world.

To this end, we urge the Commission to, at a minimum, consider dedicating more resources to a targeted outreach programme with third countries. The EU recently adopted a Regulation on responsible minerals supply chains and DG TRADE subsequently launched such outreach with the United States, China, India, United Arab Emirates, Colombia, Mexico, South Africa, Malaysia, Thailand and Canada.

We, the undersigned associations, endorse the Commission’s roadmap for the evaluation and the aim to review and improve the effectiveness, efficiency, relevance of the RoHS Directive, as well as coherence with other EU laws and policies. However, we feel this important global dimension is absent and should be incorporated into the Review.

The Joint-Statement with the full list of participating associations can be accessed here.

SEMI encourages its members to communicate the Joint-Statement at regional and national levels. For more information, contact Emir Demircan, senior manager Advocacy and Public Policy, SEMI Europe, at [email protected].

Total wafer shipments in 2018 year are expected to eclipse the all-time market high set in 2017 and continue to reach record levels through 2021, according to SEMI’s recent semiconductor industry annual silicon shipment forecast. The forecast of demand for silicon units for the period 2018 through 2021 shows polished and epitaxial silicon shipments totaling 12,445 million square inches in 2018; 13,090 million square inches in 2019; 13,440 million square inches in 2020, and 13,778 million square inches in 2021 (see table below).

“As new greenfield fab projects continue to emerge for memory and foundry, silicon shipments are expected to remain strong for 2019 and through 2021,” said Clark Tseng, director of Industry Research & Statistics at SEMI. “Silicon demand will continue to grow as semiconductor content increases in mobile, high-performance computing, automotive, and Internet of Things applications.”

2018 Silicon* Shipment Forecast (MSI = Millions of Square Inches)
Actual
Forecast
2016
2017
2018
2019
2020
2021
MSI
10,577
11,617
12,445
13,090
13,440
13,778
Annual Growth
3.0%
9.8%
7.1%
5.2%
2.7%
2.5%

*Total Electronic Grade Silicon Slices – Excludes Non-Polished Wafers

*Shipments are for semiconductor applications only and do not include solar applications

Source: SEMI (www.semi.org), October 2018

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or chips are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

A new approach in Fault Detection and Classification (FDC) allows engineers to uncover issues more thoroughly and accurately by taking advantage of full sensor traces.

By Tom Ho and Stewart Chalmers, BISTel, Santa Clara, CA

Traditional FDC systems collect data from production equipment, summarize it, and compare it to control limits that were previously set up by engineers. Software alarms are triggered when any of the summarized data fall outside of the control limits. While this method has been effective and widely deployed, it does create a few challenges for the engineers:

  • The use of summary data means that (1) subtle changes in the process may not be noticed and (2) the unmonitored section of the process will be overlooked by a typical FDC system. These subtle changes or the missed anomalies in unmonitored section may result in critical problems.
  • Modeling control limits for fault detection is a manual process, prone to human error and process drift. With hundreds of thousandssensors in a complex manufacturing process, the task of modeling control limits is extremely time consuming and requires a deep understanding of the particular manufacturing process on the part of the engineer. Non-optimized control limits result in misdetection: false alarms or missed alarms.
  • As equipment ages, processes change. Meticulously set control limit ranges must be adjusted, requiring engineers to constantly monitor equipment and sensor data to avoid false alarms or missed real alarm.

Full sensor trace detection

A new approach, Dynamic Fault Detection (DFD) was developed to address the shortcomings of traditional FDC systems and save both production time and engineer time. DFD takes advantage of the full trace from each and every sensor to detect any issues during a manufacturing process. By analyzing each trace in its entirety, and running them through intelligent software, the system is able to comprehensively identify potential issues and errors as they occur. As the Adaptive Intelligence behind Dynamic Fault Detection learns each unique production environment, it will be able to identify process anomalies in real time without the need for manual adjustment from engineers. Great savings can be realized by early detection, increased engineer productivity, and containment of malfunctions.

DFD’s strength is its ability to analyze full trace data. As shown in FIGURE 1, there are many subtle details on a trace, such as spikes, shifts, and ramp rate changes, which are typically ignored or go undetected by a traditional FDC systems, because they only examine a segment of the trace- summary data. By analyzing the full trace using DFD, these details can easily be identified to provide a more thorough analysis than ever before.

Figure 1

Dynamic referencing

Unlike traditional FDC deployments, DFD does not require control limit modeling. The novel solution adapts machine learning techniques to take advantage of neighboring traces as references, so control limits are dynamically defined in real time.  Not only does this substantially reduce set up and deployment time of a fault detection system, it also eliminates the need for an engineer to continuously maintain the model. Since the analysis is done in real time, the model evolves and adapts to any process shifts as new reference traces are added.

DFD has multiple reference configurations available for engineers to choose from to fine tune detection accuracy. For example, DFD can 1) use traces within a wafer lot as reference, 2) use traces from the last N wafers as reference, 3) use “golden” traces as reference, or 4) a combination of the above.

As more sensors are added to the Internet of Things network of a production plant, DFD can integrate their data into its decision-making process.

Optimized alarming

Thousands of process alarms inundate engineers each day, only a small percentage of which are valid. In today’s FDC systems, one of the main causes for false alarms is improperly configured Statistical Process Control (SPC) limits. Also, typical FDC may generate one alarm for each limit violation resulting in many alarms for each wafer process. DFD implementations require no control limits, greatly reducing the potential for false alarms.  In addition, DFD is designed to only issues one alarm per wafer, further streamlining the alarming system and providing better focus for the engineers.

Dynamic fault detection use cases

The following examples illustrate actual use cases to show the benefits of utilizing DFD for fault detection.

Use case #1– End Point Abnormal Etching

In this example, both the upper and lower control limits in SPC were not set at the optimum levels, preventing the traditional FDC system from detecting several abnormally etched wafers (FIGURE 2).  No SPC alarms were issued to notify the engineer.

Figure 2

On the other hand, DFD full trace comparison easily detects the abnormality by comparing to neighboring traces (FIGURE 3).  This was accomplished without having to set up any control limits.

Figure 3

Use case #2 – Resist Bake Plate Temperature

The SPC chart in Figure 4 clearly shows that the Resist bake plate temperature pattern changed significantly; however, since the temperature range during the process never exceeded the control limits, SPC did not issue any alarms.

Figure 4

When the same parameter was analyzed using DFD, the temperature profile abnormality was easily identified, and the software notified an engineer (FIGURE 5).

Figure 5

Use case #3 – Full Trace Coverage

Engineers select only a segment of sensor trace data to monitor because setting up SPC limits is so arduous. In this specific case, the SPC system was set up to monitor only the He_Flow parameter in recipe step 3 and step 4.  Since no unusual events occurred during those steps in the process, no SPC alarms were triggered.

However, in that same production run, a DFD alarm was issued for one of the wafers. Upon examination of the trace summary chart shown in FIGURE 6, it is clear that while the parameter behaved normally during recipe step 3 and step 4, there was a noticeable issue from one of the wafers during recipe step 1 and step 2.  The trace in red represents the offending trace versus the rest of the (normal) population in blue. DFD full trace analysis caught the abnormality.

Figure 6

Use case #4 – DFD Alarm Accuracy

When setting up SPC limits in a conventional FDC system, the method of calculation taken by an engineer can yield vastly different results. In this example, the engineer used multiple SPC approaches to monitor parameter Match_LoadCap in an etcher. When the control limits were set using Standard Deviation (FIGURE 7), a large number of false alarms were triggered.  On the other hand, zero alarms were triggered using the Meanapproach (FIGURE 8).

Figure 7

Figure 8

Using DFD full trace detection eliminates the discrepancy between calculation methods. In the above example, DFD was able to identify an issue with one of the wafers in recipe step 3 and trigger only one alarm.

Dynamic fault detection scope of use

DFD is designed to be used in production environments of many types, ranging from semiconductor manufacturing to automotive plants and everything in between. As long as the manufacturing equipment being monitored generates systematic and consistent trace patterns, such as gas flow, temperature, pressure, power etc., proper referencing can be established by the Adaptive Intelligence (AI) to identify abnormalities. Sensor traces from Process of Record (POR) runs may be used as starting references.

Conclusion

The DFD solution reduces risk in manufacturing by protecting against events that impact yield.  It also provides engineers with an innovative new tool that addresses several limitations of today’s traditional FDC systems.  As shown in TABLE 1, the solution greatly reduces the time required for deployment and maintenance, while providing a more thorough and accurate detection of issues.

 

TABLE 1
FDC

(Per Recipe/Tool Type)

 DFD

(Per Recipe/Tool Type)
FDC model creation 1 – 2 weeks < 1 day
FDC model validation and fine tuning 2 – 3 weeks < 1 week
Model Maintenance Ongoing Minimal
Typical Alarm Rate 100-500/chamber-day < 50/chamber-day
% Coverage of Number of Sensors 50-60% 100% as default
Trace Segment Coverage 20-40% 100%
Adaptive to Systematic Behavior Changes No Yes

 

 

TOM HO is President of BISTel America where he leads global product engineer and development efforts for BISTel.  [email protected].   STEWART CHALMERS is President & CEO of Hill + Kincaid, a technical marketing firm. [email protected].