Category Archives: Wafer Processing

The average revenue generated from processed wafers among the four biggest pure-play foundries (TSMC, GlobalFoundries, UMC, and SMIC) is expected to be $1,138 in 2018, when expressed in 200mm-equivalent wafers, which is essentially flat from $1,136 in 2017, according to a new analysis by IC Insights (Figure 1).  The average revenue per wafer among the Big 4 foundries peaked in 2014 at $1,149 and then slowly declined through last year, based on IC Insights’ extensive part-two analysis of the integrated circuit foundry business in the September Update to The 2018 McClean Report.

Figure 1

TSMC’s average revenue per wafer in 2018 is forecast to be $1,382, which is 36% higher than GlobalFoundries’ $1,014.  UMC’s average revenue per wafer in 2018 is expected to be only $715, about half of the projected amount at TSMC this year.  Furthermore, TSMC is the only foundry among the Big 4 that is expected to generate higher revenue per wafer (9% more) in 2018 than in 2013.  In contrast, GlobalFoundries, UMC, and SMIC’s 2018 revenue per wafer averages are forecast to decline by 1%, 10%, and 16%, respectively, compared to 2013.

Although the average revenue per wafer of the Big 4 foundries is forecast to be $1,138 this year, the amount generated is highly dependent upon the minimum feature size of the IC processing technology. Figure 2 shows the typical 2Q18 revenue per wafer for some of the major technology nodes and wafer sizes produced by pure-play foundries.  In 2Q18, there was more than a 16x difference between the 0.5µ 200mm revenue per wafer ($370) and the ≤20nm 300mm revenue per wafer ($6,050).  Even when using revenue per square inch, the difference is dramatic ($7.41 for the 0.5µ technology versus $53.86 for the ≤20nm technology).  Since TSMC gets such a large percentage of its sales from ≤45nm production, its revenue per wafer is expected to increase by a compound annual growth rate (CAGR) of 2% from 2013 through 2018 as compared to a -2% CAGR for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC during this same timeperiod.

Figure 2

There will probably be only three foundries able to offer high-volume leading-edge production over the next five years (i.e., TSMC, Samsung, and Intel).  IC Insights believes these companies are likely to be fierce competitors among themselves—especially TSMC and Samsung—and as a result, pricing will likely be under pressure through 2022.

When chemists from the Institute of Physical Chemistry of the Polish Academy of Sciences in Warsaw were starting work on yet another material designed for the efficient production of nanocrystalline zinc oxide, they didn’t expect any surprises. They were greatly astonished when the electrical properties of the changing material turned out to be extremely exotic.

The exotic transformations causes that one of the precursors of zinc oxide, initially an insulator, at approx. 300 degrees Celsius goes to a state with electrical properties typical of metals, and at ~400 degrees Celsius it becomes a semiconductor. Credit: IPC PAS

The single source precursor (SSP) approach is widely regarded as one of the most promising of the various strategies employed for the preparation of semiconductor nanocrystalline materials. However, one of the key obstacles hampering both the rational design of SSPs and their controlled transformation to the desired nanomaterials with highly controlled physicochemical properties is the scarcity of mechanistic insights during the transformation process. Scientists from the Institute of Physical Chemistry of the Polish Academy of Sciences (IPC PAS) and the Faculty of Chemistry of Warsaw University of Technology (WUT) have revealed that in the thermal decomposition process of a pre-organized zinc alkoxide precursor the nucleation and growth of the semiconducting zinc oxide (ZnO) phase is preceded by cascade transformations involving the formation of previously unreported intermediate radical zinc oxo-alkoxide clusters with gapless electronic states. Up to now, these types of clusters have not been considered either as intermediate structures on the path to the semiconductor ZnO phase or as a potential species accounting for the various defect states of ZnO nanocrystals.

“We discovered that one of the groups of ZnO precursors that have been studied for decades, zinc alkoxide compounds, undergo previously unobserved physicochemical transformations upon thermal decomposition. Originally, the starting compound is an insulator, when heated it rapidly transforms into a material with conductor-like properties, and a further increase in temperature equally rapidly leads to its conversion into a semiconductor,” says Dr. Kamil Soko?owski (IPC PAS).

The design and preparation of well-defined nanomaterials in a controlled manner remains a tremendous challenge and is acknowledged to be the biggest obstacle for the exploitation of many nanoscale phenomena. Professor Lewiski’s (IPC PAS, PW) group has for many years been engaged in the development of effective methods of producing nanocrystalline forms of zinc oxide, a semiconductor with wide applications in electronics, industrial catalysis, photovoltaics and photocatalysis. One of the studied approaches is based on the single source precursors. The precursor molecules contain all components of the target material in their structure and only temperature is required to trigger the chemical transformation.

“We dealt with a group of chemical compounds with the general formula RZnOR, as single source pre-designed ZnO precursors. A common feature of their structure is the presence of the cubic [Zn4O4] core with alternating zinc and oxygen atoms terminated by organic groups R. When the precursor is heated, the organic parts are degraded, and the inorganic cores self-assemble, forming the final form of the nanomaterial,” explains Dr. Soko?owski.

The tested precursor had the properties of an insulator, with an energy gap of about five electronvolts. When heated, it eventually transformed into a semiconductor with an energy gap of approximately 3 eV.

“An exceptional result of our research was the discovery that at a temperature close to 300 degrees Celsius the compound suddenly transforms into almost gap-less electronic state, showing electrical properties rather more typical of metals. When the temperature rises to approximately 400 degrees, the energy gap suddenly expands to a width characteristic of semiconductor materials. Ultimately, thanks to the combination of advanced synchrotron experiments with quantum-chemical calculations, we have established all the details of these unique transformations,” says Dr. Adam Kubas (IPC PAS), who carried out the quantum-chemical calculations.

The spectroscopic measurements were carried out using methods developed by Dr. Jakub Szlachetko (Institute of Nuclear Physics PAS, Cracow) and Dr. Jacinto Sa (IPC PAS and Uppsala University) at the Swiss Light Source synchrotron facility at the Paul Scherrer Institute in Villigen, Switzerland. The material was heated in a reaction chamber, and then its electron structure was sampled using an X-ray synchrotron beam. The set-up allowed for real-time monitoring of the transformations taking place.

This detailed in situ study of the decomposition process of the zinc alkoxide precursor, supported by computer simulations, revealed that any nucleation or growth of a semiconducting ZnO phase is preceded by cascade transformations involving the formation of previously unreported intermediate radical zinc oxo-alkoxide clusters with gapless electronic states.

“In this process homolytic cleavage of the R-Zn bond is responsible for the initial thermal decomposition process. Computer simulations revealed that the intermediate radical clusters tend to dimerise though an uncommon bimetallic Zn-Zn-bond formation. The following homolytic O-R bond cleavage then leads to sub-nano ZnO clusters which further self-organise to the ZnO nanocrystalline phase,” says Dr. Kubas.

Up to now, the radical zinc oxo clusters formed have not been considered either as intermediate structures on the way to the semiconductor ZnO phase or as potential species accounting for various defect states of ZnO nanocrystals. In a broader context, a deeper understanding of the origin and character of the defects is crucial for structure-property relationships in semiconducting materials.

The research, funded by the National Science Centre and the TEAM grant of the Foundation for Polish Science co-financed by the European Union, will contribute to the development of more precise methods of controlling the properties of nanocrystalline zinc oxide. So far, with greater or lesser success, these properties have been explained with the help of various types of material defects. For obvious reasons, however, the analyses have not taken into account the possibility of forming the specific radical zinc-oxo clusters discovered by the Warsaw-based scientists in the material.

Since the 2003 discovery of the single-atom-thick carbon material known as graphene, there has been significant interest in other types of 2-D materials as well.

These materials could be stacked together like Lego bricks to form a range of devices with different functions, including operating as semiconductors. In this way, they could be used to create ultra-thin, flexible, transparent and wearable electronic devices.

However, separating a bulk crystal material into 2-D flakes for use in electronics has proven difficult to do on a commercial scale.

The existing process, in which individual flakes are split off from the bulk crystals by repeatedly stamping the crystals onto an adhesive tape, is unreliable and time-consuming, requiring many hours to harvest enough material and form a device.

Now researchers in the Department of Mechanical Engineering at MIT have developed a technique to harvest 2-inch diameter wafers of 2-D material within just a few minutes. They can then be stacked together to form an electronic device within an hour.

The technique, which they describe in a paper published in the journal Science, could open up the possibility of commercializing electronic devices based on a variety of 2-D materials, according to Jeehwan Kim, an associate professor in the Department of Mechanical Engineering, who led the research.

The paper’s co-first authors were Sanghoon Bae, who was involved in flexible device fabrication, and Jaewoo Shim, who worked on the stacking of the 2-D material monolayers. Both are postdocs in Kim’s group.

The paper’s co-authors also included students and postdocs from within Kim’s group, as well as collaborators at Georgia Tech, the University of Texas, Yonsei University in South Korea, and the University of Virginia. Sang-Hoon Bae, Jaewoo Shim, Wei Kong, and Doyoon Lee in Kim’s research group equally contributed to this work.

“We have shown that we can do monolayer-by-monolayer isolation of 2-D materials at the wafer scale,” Kim says. “Secondly, we have demonstrated a way to easily stack up these wafer-scale monolayers of 2-D material.”

The researchers first grew a thick stack of 2-D material on top of a sapphire wafer. They then applied a 600-nanometer-thick nickel film to the top of the stack.

Since 2-D materials adhere much more strongly to nickel than to sapphire, lifting off this film allowed the researchers to separate the entire stack from the wafer.

What’s more, the adhesion between the nickel and the individual layers of 2-D material is also greater than that between each of the layers themselves.

As a result, when a second nickel film was then added to the bottom of the stack, the researchers were able to peel off individual, single-atom thick monolayers of 2-D material.

That is because peeling off the first nickel film generates cracks in the material that propagate right through to the bottom of the stack, Kim says.

Once the first monolayer collected by the nickel film has been transferred to a substrate, the process can be repeated for each layer.

“We use very simple mechanics, and by using this controlled crack propagation concept we are able to isolate monolayer 2-D material at the wafer scale,” he says.

The universal technique can be used with a range of different 2-D materials, including hexagonal boron nitride, tungsten disulfide, and molybdenum disulfide.

In this way it can be used to produce different types of monolayer 2-D materials, such as semiconductors, metals, and insulators, which can then be stacked together to form the 2-D heterostructures needed for an electronic device.

“If you fabricate electronic and photonic devices using 2-D materials, the devices will be just a few monolayers thick,” Kim says. “They will be extremely flexible, and can be stamped on to anything,” he says.

The process is fast and low-cost, making it suitable for commercial operations, he adds.

The researchers have also demonstrated the technique by successfully fabricating arrays of field-effect transistors at the wafer scale, with a thickness of just a few atoms.

“The work has a lot of potential to bring 2-D materials and their heterostructures towards real-world applications,” says Philip Kim, a professor of physics at Harvard University, who was not involved in the research.

The researchers are now planning to apply the technique to develop a range of electronic devices, including a nonvolatile memory array and flexible devices that can be worn on the skin.

They are also interested in applying the technique to develop devices for use in the “internet of things,” Kim says.

“All you need to do is grow these thick 2-D materials, then isolate them in monolayers and stack them up. So it is extremely cheap — much cheaper than the existing semiconductor process. This means it will bring laboratory-level 2-D materials into manufacturing for commercialization,” Kim says.

“That makes it perfect for IoT networks, because if you were to use conventional semiconductors for the sensing systems it would be expensive.”

According to Allied Market Research, the global compound semiconductor market was valued at USD 66,623 million in 2016 and is expected to reach USD 142,586 million in 2023 while growing at a CAGR of 11.3% from 2017 to 2023. The report indicates that a compound semiconductor is composed of two or more elements. Numerous compound semiconductors can be obtained by changing the combination of elements. Some of the factors affecting the market include the increasing demand for optoelectronic devices, as well as the attraction of compound semiconductor’s significant features, such as less power consumption, low price, and reduced heat dissipation. Rise in usage of optical devices, photovoltaic cells, and modules & wireless communication products is expected to provide an attractive opportunity for the compound semiconductor market. Squire Mining Ltd. (OTC: SQRMF), Nvidia Corporation (NASDAQ: NVDA), Advanced Micro Devices, Inc. (NASDAQ: AMD), KLA-Tencor Corporation (NASDAQ: KLAC), Maxim Integrated Products, Inc. (NASDAQ: MXIM)

As semiconductor technology begins to advance, new segments are swiftly being integrated into the market, such as Machine Learning. AI has observed significant growth in recent years. Initially, AI was considered a topic for academicians, though in recent years with development of various technologies, AI has turned into reality and is influencing many lives and businesses. According to MarketsandMarkets the global artificial intelligence chipset market is expected to be worth USD 16.06 Billion by 2022 and grow at a CAGR of 62.9% between 2016 and 2022.

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Earlier last week, the Company announced breaking news that, “to report on its prototype ASIC chip testing event held in Seoul, South Korea. With executives and board members from Squire, Future Farm, CoinGeek, Gaonchips and Samsung Electronics in attendance, Peter Kim, President of Squire’s subsidiary AraCore Technology Corp. (“Aracore”), and his team of front-end microchip engineers and programmers, unveiled and tested a working prototype mining system comprised of a newly engineered FPGA (field programmable gate array) ASIC microchip that will be converted into AraCore’s first ASIC chip utilizing 10 nanometer technology for mining Bitcoin Cash, Bitcoin and other associated cryptocurrencies. The test results confirm Aracore’s original design specifications indicating that the ASIC chip, once mass manufactured by Samsung Electronics, will be capable of delivering a projected hash rate of 18 to 22 terahash per second (TH/s) with an energy consumption of between 700 and 800 watts.

Taras Kulyk, Chief Executive Officer of CoinGeek Mining and Hardware, said “The CoinGeek team is very pleased with the progress of our strategic partners; Squire Mining and Aracore. With this next generation technology, CoinGeek will continue to pull the blockchain industry out of the proverbial basement and into the boardroom.”

Stefan Matthews, Chairman of nChain, one of the industry leaders in blockchain research and development, and a director of Squire Mining added, “The early results indicate that this ASIC microchip has the potential to be the next generation leader in providing hash power for enterprise mining of Bitcoin Cash and other associated crypto currencies. It has also demonstrated the potential to rapidly process consensus protocols across the blockchain faster whilst utilizing less energy than anything currently in this sector.”

Hash rate speed and microchip efficiency are the two most important measuring criteria in the crypto-mining industry to enable end-users to maximize profitability and ROI in their day to day mining operations.

Simon Moore, Executive Chairman and CEO of Squire Mining, stated, “Aracore’s time and investment to date have been validated by the impressive results of this new microchip. Once completed, we believe the speed and efficiency of our ASIC microchip combined with our respective mining systems powered by this Samsung manufactured microchip together have the potential to substantially increase the profitability of enterprise mining facilities around the globe. We look forward to releasing our mining system to the market in the first half of next year through our exclusive distribution partners CoinGeek, and competing for a significant piece of this multi-billion-dollar enterprise mining market.”

About AraCore Technology Corp. – Aracore is a joint venture company established by Squire and Peter Kim to design and develop next generation ASIC chips for mining Bitcoin Cash, Bitcoin and other associated cryptocurrencies. Squire owns a 75% interest in Aracore and Peter Kim owns the remaining 25% interest.

About Squire Mining Ltd. – Squire is a Canadian based company engaged, through its subsidiaries, in the business of developing data mining infrastructure and system technology to support global blockchain applications in the mining space including applicable specific integrated circuit (ASIC) chips and next generation mining rigs to mine Bitcoin Cash, Bitcoin and other associated cryptocurrencies.”

Nvidia Corporation (NASDAQ: NVDA), in 1999, sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Nvidia recently announced that it invited the world’s top automotive safety and reliability company, TÜV SÜD, to perform a safety concept assessment of its new NVIDIA Xavier system-on-chip (SoC). The 150-year-old German firm’s 24,000 employees assess compliance to national and international standards for safety, durability and quality in cars, as well as for factories, buildings, bridges and other infrastructure. As the world’s first autonomous driving processor, Xavier is the most complex SoC ever created. Its 9 billion transistors enable Xavier to process vast amounts of data. Its GMSL (gigabit multimedia serial link) high-speed IO connects Xavier to the largest array of lidar, radar and camera sensors of any chip ever built. “NVIDIA Xavier is one of the most complex processors we have evaluated,” said Axel Köhnen, Xavier lead assessor at TÜV SÜD RAIL. “Our in-depth technical assessment confirms the Xavier SoC architecture is suitable for use in autonomous driving applications and highlights NVIDIA’s commitment to enable safe autonomous driving.”

Advanced Micro Devices, Inc. (NASDAQ: AMD), for more than 45 years, has driven innovation in high-performance computing, graphics and visualization technologies ― the building blocks for gaming, immersive platforms and the datacenter. AMD recently announced the availability of world’s most powerful desktop processor, the 2nd Gen AMD Ryzen Threadripper 2990WX processor with 32 cores and 64 threads. Designed to power the ultimate computing experiences, 2nd Gen AMD Ryzen Threadripper processors are built using 12nm “Zen+” x86 processor architecture and offer the most threads on any desktop processor with the flagship model delivering up to 53% greater performance than the competition’s flagship model. Second Gen AMD Ryzen Threadripper processors support the most I/O2, and are compatible with existing AMD X399 chipset motherboards via a simple BIOS update, offering builders a broad choice for designing the ultimate high-end desktop or workstation PC. “We created Ryzen Threadripper processors because we saw an opportunity to deliver unheard-of levels of multithreaded computing for the demanding needs of creators, gamers, and PC enthusiasts in the HEDT market,” said Jim Anderson, Senior Vice President and General Manager, Computing and Graphics Business Group, AMD. “With the 2nd Gen processor family we took that challenge to a whole new level – delivering the biggest, most powerful desktop processor the world has ever seen.”

KLA-Tencor Corporation (NASDAQ: KLAC), a provider of process control and yield management solutions, partners with customers around the world to develop sinspection and metrology technologies. Recently, KLA-Tencor Corporation announced two new defect inspection products designed to address a wide variety of integrated circuit (IC) packaging challenges. The Kronos™ 1080 system offers production-worthy, high sensitivity wafer inspection for advanced packaging, providing key information for process control and material disposition. The ICOS™ F160 system examines packages after wafers have been diced, delivering fast, accurate die sort based on detection of key defect types-including sidewall cracks, a new defect type affecting the yield of high-end packages. The two new inspection systems join KLA-Tencor’s portfolio of defect inspection, metrology and data analysis systems that help accelerate packaging yield and increase die sort accuracy. “As chip scaling has slowed, advances in chip packaging technology have become instrumental in driving device performance,” said Oreste Donzella, Senior Vice President and Chief Marketing Officer at KLA-Tencor. “Packaged chips need to achieve simultaneous targets for device performance, power consumption, form factor and cost for a variety of device applications. As a result, packaging design has become more diverse and complex, featuring a range of 2D and 3D structures that are more densely packed and shrinking in size with every generation. At the same time, the value of the packaged chip has grown substantially, along with electronics manufacturers’ expectations for quality and reliability.”

Maxim Integrated Products, Inc. (NASDAQ: MXIM) develops innovative analog and mixed-signal products and technologies to make systems smaller and smarter, with enhanced security and increased energy efficiency. Maxim Integrated recently announced that automotive infotainment designers can now upgrade to bigger, higher resolution displays with greater ease, reduced cost and smaller solution size with the MAX20069 from Maxim Integrated Products, Inc. The MAX20069 provides the industry’s first solution integrating four I2C-controlled, 150mA LED backlight drivers and a four-output thin-film-transistor liquid-crystal display (TFT-LCD) bias in a single chip. The IC can reduce design footprint up to one-third compared to the closest competitor’s parts. “Automotive manufacturers are using more screens, larger panels and brighter displays across several vehicle lines to support a safer and more engaging experience on the road,” said Szukang Hsien, Executive Business Manager, Automotive Business Unit, Maxim Integrated. “Maxim’s integrated LED backlight driver and TFT-LCD bias solution supports newer panel types to help automotive manufacturers adopt lower cost yet higher resolution panels with smaller solution size and a high level of integration.”

Toshiba Memory Corporation (TMC) today announced the appointment of Stacy J. Smith as Executive Chairman, effective on October 1, 2018.

Smith brings a long and proven track record of executive leadership to TMC. He has extensive international experience, having both lived and led organizations in the Asia-Pacific, Latin America, Europe, the Middle East and Africa. He will work closely with CEO Yasuo Naruke to provide overall leadership to the business.

Smith previously spent three decades at Intel leading organizations across multiple disciplines. In his role as President, Manufacturing, Operations and Sales, from 2016 to 2018, he led 40,000 employees involved in worldwide manufacturing, technology development, supply chain, pricing and sales. He also served as Intel’s Chief Financial Officer for almost a decade and in this role also had responsibility for corporate strategy, M&A, and Intel Capital. Prior to that he served as Intel’s Chief Information Officer and Vice President for Sales for Europe, the Middle East and Africa.

Smith also brings strong board leadership experience. He currently serves as board chairman at Autodesk and as a director for Metromile. He served previously as a director for Virgin America and for GEVO. He also serves on the Board of Trustees for The Nature Conservancy of California and on the University of Texas McCombs School of Business Advisory Board. Smith attended The University of Texas at Austin, where he received his MBA in 1988 and his BBA in 1985.

“We are thrilled that Stacy is joining Toshiba Memory Corporation in this crucial leadership role at an important time in the company’s history,” said Yasuo Naruke, President and CEO of TMC. “With Stacy’s wealth of international leadership experience and knowledge of the semiconductor space, there is no doubt he is the perfect person to help lead our company in the next phase of growth as an independent company.”

“I am excited to take on this important challenge, and honored to join the TMC team,” said Smith. “Toshiba invented flash memory, and with TMC now operating as an independent company with increased capacity to invest in developing and growing semiconductor technology, the company has a strong growth trajectory ahead of it.”

Smith’s hiring follows the acquisition this year of TMC by an industry consortium led by Bain Capital Private Equity. Bain Capital Private Equity has a long history of successful investments in Japan including Skylark, Jupiter Shop Channel, BellSystem24, Domino’s Pizza Japan, Ooedo Onsen, and Asatsu-DK. The firm’s deep market knowledge, extensive local networks and expertise in driving operational improvement strategies have made Bain Capital a valued partner for Japanese companies.

“Stacy is the right leader to help TMC, already a technology leader in the flash memory industry, achieve its potential as an independent company,” said David Gross-Loh, a director of TMC and a managing director and co-head of Asia for Bain Capital Private Equity. “We are very pleased to welcome Stacy to TMC and look forward to working closely with him and the expanded management team.”

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has received four TSMC Partner of the Year awards at this year’s TSMC Open Innovation Platform® (OIP) Ecosystem Forum. Cadence was presented with awards for the joint development of the 5nm design infrastructure, the cloud-based TSMC OIP Virtual Design Environment (VDE), the Wafer-on-Wafer (WoW) design solution, and its Tensilica® DSP IP.

These awards were given to Cadence based on the following work that has been delivered:

  • 5nm design infrastructure: Cadence participated in an early, in-depth collaboration with TSMC on the design infrastructure development of this latest advanced-node technology for next-generation system-on-chip (SoC) designs.
  • Cloud-based TSMC OIP VDE: Cadence was one of the first TSMC OIP Cloud Alliance partners and has collaborated with TSMC and mutual customers on successful tapeouts.
  • WoW design solution: Cadence collaborated with TSMC on the development of a design solution and delivered a reference flow that includes implementation, electrical analysis and physical verification
  • DSP IP: Cadence collaborated with TSMC on the delivery of Cadence® Tensilica DSP IP, the most widely-used DSP IP in the TSMC portfolio, which mutual customers use to complete successful projects.

“Through our ongoing collaboration with TSMC, we’ve jointly worked to stay in front of industry trends so that we can enable our mutual customers to consistently deliver successful designs through use of the latest technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “These awards from TSMC exemplify our ability to drive the industry forward with our innovations with 5nm, cloud, WoW, and DSP IP.”

“Our ongoing, in-depth collaboration with Cadence provides our customers with confidence that they can use the latest technologies and tools to deliver new innovations in competitive market windows,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “We look forward to continuing to partner together on creative new solutions that our mutual customers can use to establish leadership in their respective markets.”

Semiconductors play increasingly important control roles in automotive, industrial and safety critical applications. Quality and reliability are therefore of vital importance and so Presto Engineering has completed certification to the ISO 9001:2015 quality standard at its facility in Caen, France, which is Europe’s largest independent semiconductor test facility.

“We have an extensive and comprehensive range of semiconductor test equipment,” said Dr Alban Colder, Presto’s Site Director at Caen. “This includes testing at every stage from wafer, through die, to final packed device. As part of the ISO 9001: 2015 quality standard, we have a comprehensive range of equipment for non-destructive analysis such as X-Ray to check packaging and bondings, and ultrasound to see inside a device to check for delamination, voids and cracked silicon. There is also equipment to check for failure localization by photoemission or thermal laser stimulation, and deep physical analysis, i.e. strip a device down layer by layer to see exactly where it is failing and why. Other advanced equipment such as an atomic force microscope or a scanning electron microscope are used to reveal the precise details of the structure of a chip down to a few nanometers.”

The key part of a quality system in semiconductors industry, is traceability. Detailed record keeping traces every wafer, every operation, every die and every test. Thus, in the event that there is a faulty chip in the field, it can be traced back to try and determine the cause and to see if any other chips have been affected that might necessitate a recall. In the case of an automotive recall, this could be very expensive so it is vital to be able to narrow the problem down to only the affected chips.

Martin Kingdon, Presto’s VP of Sales, added, “We have assembled a suite of state-of-the-art equipment as part of our commitment of quality and this new standard. We provide customers with a comprehensive service once they provide us with a design that covers every stage of the chip manufacturing and testing process right through to final product. As part of our quality assurance to customers, we rigorously test at every stage. Such a comprehensive test and failure analysis capability all together under one roof is very rare; usually it requires a number of different test houses which means that issues could be missed. Having all the skills and equipment together in one place means that we can keep searching until we find the cause of a problem so that it can be resolved and quality maintained.”

By Alan Weber

Even for someone who has been in this industry since the days of the TI Datamath 4-function calculator and the TMS1100 4-bit microcontroller (yes, that’s been a LONG time – the movie Grease premiered the same year!), it is sometimes hard to grasp the scope and complexity of what happens in today’s leading-edge semiconductor gigafabs. In fact, the only way to comprehend the enormous volume of transactions that occur is to consider what happens in a single minute – this is illustrated in the infographic we have labeled “The Gigafab Minute.”*

It’s amazing enough to think that a single factory can start 100,000 wafers every month on their cyclical journey through 1500 process steps… and have 99%+ of them emerge 4 months later to be delivered to packaging houses and then on to waiting customers. It’s quite another to realize that all of this happens continuously (24 x 7) and automatically.

“How is this possible?” you ask.

Well, a big part of the solution is the body of SEMI standards which have evolved since the early 80s to keep pace with the ever-changing demands of the industry. From an automation standpoint, many of these standards deal with the communications between manufacturing equipment and the factory information and control systems that are essential for managing these complex, hyper-competitive global enterprises.

A significant characteristic of these standards is that they have been carefully designed to be “additive.” This means that new generations of SEMI’s communications standards do not supplant or obsolete the previous generations, but rather provide new capabilities in an incremental fashion. To appreciate the importance of this in actual practice, consider how the GEM, GEM300, and EDA/Interface A standards support the transactions that occur in a single Gigafab Minute.

Starting at 1:00 o’clock on the infographic and moving clockwise, you first notice that 2.31 wafers enter the line. Of course, these are actually released in 25-wafer 300mm FOUPs (Front-Opening Unified Pod), but 100K wafers per month translates to 2.31 per minute. Since these factories run continuously, once the line is full, it stays full. And with an average total cycle time of 4 months, this means that there are 400K wafers of WIP (work in process) in the factory at any given time. This number, and the total number of equipment (5000+), drive the rest of the calculations.

GEM (Generic Equipment Model) – SEMI E30, etc.

The GEM messaging standards were initially defined in the early 90s to support the factory scheduling and dispatching applications that decide what lots should go to what equipment, the automated material handling systems that deliver and pick-up material to/from the equipment accordingly, the recipe management systems that ensure each process step is executed properly, and the MES (Manufacturing Execution System) transactions that maintain the fidelity of the factory system’s “digital twin.”

Every minute of every day, GEM messages support and chronicle the following activities: 240 process steps are completed (i.e., 240 25-wafer lots are processed), 300 recipes are downloaded along with a set of run-specific adjustable control parameters, and 600 FOUPs are moved from one place to another (equipment, stockers, under-track storage, etc.). For each of these activities, the factory’s MES is notified instantaneously.

GEM300 – SEMI E40, E87, E90, E94, E157

With the advent of 300mm manufacturing in the mid-to-late 90s, a global team of volunteer system engineers from the leading chip makers defined the GEM300 standards to support fully automated manufacturing operations. Starting at 5:00 o’clock on the infographic, the number of transactions per minute jumps almost 3 orders of magnitude, from the monitoring of 900 control jobs across 4000 process tools to the tracking of 360,000 individual recipe step change events. This level of event granularity is essential for the latest generation of FDC (Fault Detection and Classification) applications, because precise data framing is a key prerequisite for minimizing the false alarm rate while still preventing serious process excursions. In this context, more than 6000 recipe-, product- and chamber-specific fault models may be evaluated every minute.

Simultaneously, the applications that monitor instantaneous throughput to prevent “productivity excursions” and identify systemic “wait time waste” situations depend on detailed intra-tool wafer movement events. In a fab with hundreds of multi-chamber, single-wafer processes, 75,000 or more of these events occur every minute.

EDA (Equipment Data Acquisition) – SEMI E120, E125, E132, E134, E164, etc.

Rounding out the SEMI standards in our example gigafab is the suite of EDA standards which complement the command and control functions of GEM/GEM300 with flexible, high-performance, model-based data collection. The EDA standards enable the on-demand collection of the volume and variety of “big data” required from the equipment to support the advanced analysis, machine learning, and other AI (Artificial Intelligence) applications that are becoming increasingly prevalent in leading semiconductor manufacturers. As EUV (Extreme Ultraviolet) lithography moves from pilot production to high-volume manufacturing at the 7nm process node and beyond, the litho process area will become a major source of process data by itself, generating 10 GB of data every minute. This is in addition to the 100 GB of data collected from other process areas.

The End Result

The final wedge (12:00 o’clock) in our infographic highlights the real objective – which is producing the millions of integrated circuits that fuel our global economy and provide the technologies that are an integral part of our modern way of life. Assuming a nominal die size of 50 square mm (typical of an 8 GB DRAM), the 2.31 wafers we started at 1:00 o’clock result in almost 3200 individual chips. But none of this would be possible without the pervasive factory automation technology we now take for granted. So, as you finish reading this posting on whatever device you happen to be using, take a micro-moment to acknowledge and thank the hundreds of standards volunteers whose insights and efforts made this a reality!

You may not be responsible for running a gigafab anytime soon, but the SEMI standards used in this setting are no less applicable to any Smart Manufacturing environment. Give us a call if you’d like to know more about how these technologies can benefit your operations for many years to come.

Alan Weber is Vice President, New Product Innovations, at Cimetrix Incorporated. Previously he served on the Board of Directors for eight years before joining the company as a full-time employee in 2011. Alan has been a part of the semiconductor and manufacturing automation industries for over 40 years. He holds bachelor’s and master’s degrees in Electrical Engineering from Rice University.

Originally published on the SEMI blog.

On October 1, 2018 INFICON Inc. (SWX:IFCN), a supplier of vacuum instrumentation and process control software to the semiconductor manufacturing industry acquired all assets of Final Phase Systems (FPS) of Austin, Texas, USA.

Founded in 2009 by Industrial Engineers from AMD/Spansion’s Fab25, FPS has grown to a team of 22 employees who will now join the INFICON organization. Together, INFICON and FPS have developed the most comprehensive Industrial Engineering Software Suite available in the semiconductor manufacturing industry. With many successful deployments in the USA and across the globe, they have a proven track record of improving capital productivity and labor efficiency. By utilizing its software and techniques, their customers have been able to realize greater than 10% improvement in overall fab efficiency. In collaboration with the international SEMI organization, Final Phase Systems has established itself as a key player in the Smart Manufacturing initiative and serves as Co-chair of SEMI’s Smart Manufacturing Americas Chapter.

“The acquisition of FPS is the latest step in INFICON’s vision to provide the semiconductor and display manufacturing industries with the most advanced factory and process control tools available,” said Oliver Wyrsch, President, INFICON Inc. “The combined product offering will put INFICON in a unique position to provide the industry’s only end-to-end software solution for the fully connected Smart fab of the future.”

Engineers at The Australian National University (ANU) have invented a semiconductor with organic and inorganic materials that can convert electricity into light very efficiently, and it is thin and flexible enough to help make devices such as mobile phones bendable.

The invention also opens the door to a new generation of high-performance electronic devices made with organic materials that will be biodegradable or that can be easily recycled, promising to help substantially reduce e-waste.

The huge volumes of e-waste generated by discarded electronic devices around the world is causing irreversible damage to the environment. Australia produces 200,000 tonnes of e-waste every year – only four per cent of this waste is recycled.

The organic component has the thickness of just one atom – made from just carbon and hydrogen – and forms part of the semiconductor that the ANU team developed. The inorganic component has the thickness of around two atoms. The hybrid structure can convert electricity into light efficiently for displays on mobile phones, televisions and other electronic devices.

Lead senior researcher Associate Professor Larry Lu said the invention was a major breakthrough in the field.

“For the first time, we have developed an ultra-thin electronics component with excellent semiconducting properties that is an organic-inorganic hybrid structure and thin and flexible enough for future technologies, such as bendable mobile phones and display screens,” said Associate Professor Lu from the ANU Research School of Engineering.

PhD researcher Ankur Sharma, who recently won the ANU 3-Minute Thesis competition, said experiments demonstrated the performance of their semiconductor would be much more efficient than conventional semiconductors made with inorganic materials such as silicon.

“We have the potential with this semiconductor to make mobile phones as powerful as today’s supercomputers,” said Mr Sharma from the ANU Research School of Engineering.

“The light emission from our semiconducting structure is very sharp, so it can be used for high-resolution displays and, since the materials are ultra-thin, they have the flexibility to be made into bendable screens and mobile phones in the near future.”

The team grew the organic semiconductor component molecule by molecule, in a similar way to 3D printing. The process is called chemical vapour deposition.

“We characterised the opto-electronic and electrical properties of our invention to confirm the tremendous potential of it to be used as a future semiconductor component,” Associate Professor Lu said.

“We are working on growing our semiconductor component on a large scale, so it can be commercialised in collaboration with prospective industry partners.”