Category Archives: Wafer Processing

The American Institute for Manufacturing Integrated Photonics (AIM Photonics) and Analog Photonics (AP) today announced the release of the AP SUNY Process Design Kit v2.5a (APSUNY_PDKv2.5a). In this latest release, Analog Photonics (AP) expanded the comprehensive set of Silicon Photonics Integrated Circuit (PIC) component libraries within SUNY Poly’s process capabilities to address the needs for O+C+L band applications. Combined with Multi-Project Wafer (MPW) runs, this updated PDK will give AIM Photonics’ members access to world-class silicon photonics components for the development of optical transceivers or systems used in all levels within data centers and high-performance computers.

The Silicon Photonics PDK includes design guide, design rule check deck, technology files, active and passive component documentation, abstracts, schematics, and compact models for the development of PICs.

The key features of the APSUNY_PDKv2.5a are:

  • O Band modulation, detection and coupling support.
  • C+L Band modulation, detection, filtering, switching, monitoring and coupling support.
  • Single-level and Multi-level modulation format support at 50Gbps, namely NRZ and PAM-4.
  •    Continued multi-vendor Electronics-Photonics-Design-Automation (EPDA) support with integrated EPDA PDK flow for hierarchical design and system-level simulation.

“We are thrilled to continue to expand the offerings of our state-of-the-art PDK to meet the needs of our more than 100 signed partners and other interested collaborators who can gain access to our unique capabilities. This also dovetails perfectly with our effort to efficiently process our Multi-Project Wafers (MPW’s) in the fab, with processing time decreasing from 130 days in 2016 to fewer than 90 days as we simultaneously add additional mask levels and functionality and continue to achieve world-class quality,” said Dr. Michael Liehr, AIM Photonics CEO and SUNY Poly Executive Vice President for Innovation and Technology.

The combined APSUNY_PDKv2.5a and MPW offering provides unmatched access to PIC systems for companies who desire a reduction in the time to market, product development risk, and investment.  By incorporating the design, verification, and process development within the PDK, interested organizations can rapidly modify their designs while reducing cost.

“The IEEE standards and multi-source-agreements (MSAs) for communications compatibility are key for our PDK component library. These standards require optical components to operate at O band (1260nm-to-1360nm), C band (1530nm-to-1565nm) and L band (1565nm-to-1625nm). With the PDKv2.5a component library, we are enabling components that cover all these bands in a single fabrication flow, and we look forward to the advancement of this library while innovating to meet industry needs,” said Director of PDK Development at Analog Photonics, Dr. Erman Timurdogan.

In the near future, the PDK will be empowered by laser and CMOS integration with an interposer, a capability that will be made possible at AIM Photonics’ Test, Assembly, and Packaging (TAP) facility, located in Rochester, NY. Additional releases of the AP SUNY Process Design Kit are planned over the next several years each quarter, with improved statistical models, optical components, and PIC systems.

“We are seeing customers take advantage of our repeatedly characterized and proven devices in the APSUNY PDK. With this valuable resource, which is validated on our 300mm advanced  semiconductor toolset, customers are able to rapidly address global standards, shrink their design sizes, and most importantly, reduce their time to market,” said AIM Photonics Design Center Offering Director Barton Bergman.

AIM Photonics is leveraging SUNY Poly’s state-of-the-art facilities for three total full-build/passive MPW runs that incorporate the PDK updates, with an interposer MPW run anticipated later in 2018. To ensure space for all interested parties, AIM Photonics is accepting reservations for these MPW runs. Those interested in participating in any of the AIM Photonics 2018 MPW silicon photonics runs should contact Chandra Cotter at [email protected] in order to guarantee a spot on these exciting new silicon photonics offerings. Interested parties can also sign up for the 2018 runs by visiting the initiative’s website at the following link: http://www.aimphotonics.com/mpw-schedule/

PDK and MPW fab access is solely available through the AIM Photonics MPW aggregator, MOSIS. Please contact MOSIS for access to the most current PDK version release at the following link: www.mosis.com/vendors/view/AIM.

According to data compiled by Inkwood Research, the global semiconductor market is projected to grow at a CAGR of 7.67% during the forecast period from 2017 to 2024. Data reflects that the market is driven by rising demand for consumer electronics, the growing automotive semiconductor market, the emerging internet of things (IoT) market and investments into New Product Development and R&D. Consumer electronics are primarily fueling the market due to demand for products such as tablets, smartphones, laptops and wearable devices. As semiconductor technology begins to advance, new segments are swiftly being integrated into the market, such as Machine Learning. Squire Mining Ltd. (OTC: SQRMF), Intel Corporation (NASDAQ: INTC), Texas Instruments Incorporated (NASDAQ: TXN), NXP Semiconductors N.V. (NASDAQ: NXPI), Skyworks Solutions, Inc. (NASDAQ: SWKS)

According to data by MarketsandMarkets, the global machine learning sector is expected to grow from USD 1.41 Billion in 2017 to USD 8.81 Billion in 2022 while registering a CAGR of 44.1% during the forecast period. The segment is rapidly growing due to many businesses adopting machine learning to gather intelligence for security and consumer interaction benefits, which can help eliminate human errors. However, machine learning is also being integrated into modern day technology, such as the automotive industry, to build autonomous vehicles. In a report by Forbes, Daniel Newman Principal Analyst and Founding Partner of Futurum Research, explained, “When dealing with a technology as advanced as machine learning, there simply isn’t an industry that would not benefit. I mean how could a business not take advantage of a technology that would make them more successful? In the next year, there will be multiple new uses for machine learning in all of these industries available for the taking and I’m not just talking about in marketing and sales.”

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Yesterday, the Company announced breaking news that, “to report on its prototype ASIC chip testing event held in Seoul, South Korea. With executives and board members from Squire, Future Farm, CoinGeek, Gaonchips and Samsung Electronics in attendance, Peter Kim, President of Squire’s subsidiary AraCore Technology Corp. (“Aracore”), and his team of front-end microchip engineers and programmers, unveiled and tested a working prototype mining system comprised of a newly engineered FPGA (field programmable gate array) ASIC microchip that will be converted into AraCore’s first ASIC chip utilizing 10 nanometer technology for mining Bitcoin Cash, Bitcoin and other associated cryptocurrencies. The test results confirm Aracore’s original design specifications indicating that the ASIC chip, once mass manufactured by Samsung Electronics, will be capable of delivering a projected hash rate of 18 to 22 terahash per second (TH/s) with an energy consumption of between 700 and 800 watts.

Taras Kulyk, Chief Executive Officer of CoinGeek Mining and Hardware, said ‘The CoinGeek team is very pleased with the progress of our strategic partners; Squire Mining and Aracore. With this next generation technology, CoinGeek will continue to pull the blockchain industry out of the proverbial basement and into the boardroom.’

Stefan Matthews, Chairman of nChain, one of the industry leaders in blockchain research and development, and a director of Squire Mining added, ‘The early results indicate that this ASIC microchip has the potential to be the next generation leader in providing hash power for enterprise mining of Bitcoin Cash and other associated crypto currencies. It has also demonstrated the potential to rapidly process consensus protocols across the blockchain faster whilst utilizing less energy than anything currently in this sector.’

Hash rate speed and microchip efficiency are the two most important measuring criteria in the crypto-mining industry to enable end-users to maximize profitability and ROI in their day to day mining operations.

Simon Moore, Executive Chairman and CEO of Squire Mining, stated, ‘Aracore’s time and investment to date have been validated by the impressive results of this new microchip. Once completed, we believe the speed and efficiency of our ASIC microchip combined with our respective mining systems powered by this Samsung manufactured microchip together have the potential to substantially increase the profitability of enterprise mining facilities around the globe. We look forward to releasing our mining system to the market in the first half of next year through our exclusive distribution partners CoinGeek, and competing for a significant piece of this multi-billion-dollar enterprise mining market.’

ANSYS (NASDAQ: ANSS) announced TSMC certified ANSYS solutions for the 7 nanometer FinFET Plus (N7+) process node with extreme ultraviolet lithography (EUV) technology and validated the reference flow for the latest Integrated Fan-Out with Memory on Substrate (InFO_MS) advanced packaging technology. The certifications and validations are vital for fabless semiconductor companies that require their simulation tools to pass rigorous testing and validation for new process nodes and packaging technologies.

ANSYS® RedHawk™ and ANSYS® Totem™ are certified for TSMC N7+ process technology that provides EUV-enabled features. Certification for N7+ includes extraction, power integrity and reliability, signal electromigration (EM) and thermal reliability analysis.

Industry-leading TSMC InFO advanced packaging technology is extended to integrate memory subsystem with logic die. TSMC and ANSYS enhanced the existing InFO design flow to support the new InFO_MS packaging technology, and validated the reference flow using ANSYS SIwave-CPA, ANSYS® RedHawk-CPA™, ANSYS® RedHawk-CTA™, ANSYS® CMA™ and ANSYS® CSM™ with the corresponding chip models. The InFO_MS reference flow includes die and package co-simulation and co-analysis for extraction, power and signal integrity analysis, power and signal electromigration analysis and thermal analysis.

“TSMC and ANSYS’ latest N7+ certification and InFO_MS enablement empowers customers to address growing performance, reliability and power demands for their next generation of chips and packages,” said Suk Lee, Senior Director of Design Infrastructure Marketing Division at TSMC.

“The number of smart, connected electronic devices continues to grow and manufacturers must keep pace to design power efficient, high-performing and reliable products at a lower cost and with a smaller footprint,” said John Lee, General Manager at ANSYS. “ANSYS semiconductor solutions address complex multi-physics challenges such as power, thermal, reliability and impact of process variation on product performance. ANSYS’ comprehensive Chip Package System solutions for chip aware system and system aware chip signoff help mutual customers accelerate design convergence with greater confidence.”

In its September Update to The 2018 McClean Report, IC Insights discloses that over the past two years, DRAM manufacturers have been operating their memory fabs at nearly full capacity, which has resulted in steadily increasing DRAM prices and sizable profits for suppliers along the way.  Figure 1 shows that the DRAM average selling price (ASP) reached $6.79 in August 2018, a 165% increase from two years earlier in August of 2016. Although the DRAM ASP growth rate has slowed this year compared to last, it has remained on a solid upward trajectory through the first eight months of 2018.

Figure 1

The DRAM market is known for being very cyclical and after experiencing strong gains for two years, historical precedence now strongly suggests that the DRAM ASP (and market) will soon begin trending downward.  One indicator suggesting that the DRAM ASP is on the verge of decline is back-to-back years of huge increases in DRAM capital spending to expand or add new fab capacity (Figure 2). DRAM capital spending jumped 81% to $16.3 billion in 2017 and is expected to climb another 40% to $22.9 billion this year. Capex spending at these levels would normally lead to an overwhelming flood of new capacity and a subsequent rapid decline in prices.

Figure 2

However, what is slightly different this time around is that big productivity gains normally associated with significant spending upgrades are much less at the sub-20nm process node now being used by the top DRAM suppliers as compared to the gains seen in previous generations.

At its Analyst Day event held earlier this year, Micron presented figures showing that manufacturing DRAM at the sub-20nm node required a 35% increase in the number of mask levels, a 110% increase in the number of non-lithography steps per critical mask level, and 80% more cleanroom space per wafer out since more equipment—each piece with a larger footprint than its previous generation—is required to fabricate ≤20nm devices. Bit volume increases that previously averaged around 50% following the transition to a smaller technology node, are a fraction of that amount at the ≤20nm node.  The net result is suppliers must invest much more money for a smaller increase in bit volume output.  So, the recent uptick in capital spending, while extraordinary, may not result in a similar amount of excess capacity, as has been the case in the past.

As seen in Figure 2, the DRAM ASP is forecast to rise 38% in 2018 to $6.65, but IC Insights forecasts that DRAM market growth will cool as additional capacity is brought online and supply constraints begin to ease. (It is worth mentioning that Samsung and SK Hynix in 3Q18 reportedly deferred some of their expansion plans in light of expected softening in customer demand.)

Of course, a wildcard in the DRAM market is the role and impact that the startup Chinese companies will have over the next few years.  It is estimated that China accounts for approximately 40% of the DRAM market and approximately 35% of the flash memory market.

At least two Chinese IC suppliers, Innotron and JHICC, are set to participate in this year’s DRAM market. Although China’s capacity and manufacturing processes will not initially rival those from Samsung, SK Hynix, or Micron, it will be interesting to see how well the country’s startup companies perform and whether they will exist to serve China’s national interests only or if they will expand to serve global needs.

 

SMART Global Holdings, Inc. (“SMART” or the “Company”) (NASDAQ: SGH), parent company of SMART Modular Technologies, Inc., today announced the appointment of Bryan Ingram, Senior Vice President and General Manager of the Wireless Semiconductor Division of Broadcom Inc., to its board of directors and its Compensation Committee, effective October 2, 2018.

“Bryan brings significant operating skills and an extensive network of relationships with industry leaders in all parts of the electronics and semiconductor supply chain, including the largest handset manufacturers in the world,” said Ajay Shah, Chairman of the Board, President & CEO of SMART. “Bryan is responsible for one of the largest divisions within Broadcom, and his long history of executive leadership in the global semiconductor industry will be of great benefit to SMART as we continue to execute our expansion strategy.”

Mr. Ingram currently leads the Wireless Semiconductor Division at Broadcom Inc. and has served in various executive roles for over 13 years, at Broadcom Inc. and its predecessor Avago Technologies Limited, which acquired Broadcom Corp. in 2015. Mr. Ingram also held executive positions at the predecessor to Avago within Agilent Technologies. From 1986 to 1999 Mr. Ingram held various management positions at Hewlett Packard and Westinghouse. Mr. Ingram holds a Bachelor of Science in Electrical Engineering from the University of Illinois and a Master of Science in Electrical Engineering from Johns Hopkins University.

With the appointment of Mr. Ingram, the board of SMART Global Holdings now has four independent directors and a total of nine members.

By Julian West

Process power and reactive gas subsystems for semiconductor manufacturing equipment have grown at a CAGR of 21% since 2013. The segment growth is considerably above the critical subsystems industry average of 9.5% and is attributable to higher demand for vacuum processing equipment over the period.

Process power and reactive gas subsystems now account for approximately 12% of all expenditures on critical subsystems used on semiconductor manufacturing equipment, up from 7% in 2013. The main driver of this exceptional growth has been the rise in vacuum processing steps (deposition and etch) during the manufacturing processes of both logic and memory devices. Most deposition and etch processes require an RF generator to provide a plasma energy source in the chamber, increasing demand for tools with power subsystems such as RF power supplies and matching networks.

Multiple patterning and the advent of 3D NAND in high-volume manufacturing have significantly increased the number of deposition and etch processing steps and, in the case of 3D NAND, longer and more difficult etch processes are requiring a wider range of power solutions. Further analysis shows that 3D NAND has been the principle growth catalyst, with the total share of power subsystems going to memory applications increasing 8 percentage points since 2013. Memory applications now account for almost half of all power subsystems demand in 2018.

Interestingly, investigation of power subsystems by tool type reveals that a clear majority of power subsystems (60%) find their way on to etch tools with only 40% on deposition tools. This can be explained by the fact that more delicate etch processes can require multiple RF power solutions per tool, whereas deposition does always use plasma energy sources, for example in thermal deposition processes.

Despite the staggering growth performance of the power subsystems segment over the past five years, we expect the growth rate to moderate significantly in the run-up to 2023. Now that 3D NAND has been adopted in high-volume manufacturing, we expect the rate of increase in vacuum/plasma processing steps to slow down. The introduction of EUV also has the potential to taper demand for vacuum processing equipment. However, it is not expected the reverse the trend as multiple patterning techniques will still be needed in conjunction with EUV to achieve the desired improvements in device density and performance. The future growth trend for power and reactive gas subsystems is forecast to be in line with the critical subsystems industry average at approximately 2.0% CAGR until 2023.

Originally published on the SEMI blog.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, to day announced worldwide sales of semiconductors reached $40.16 billion for the month of August 2018, an increase of 14.9 percent compared to the August 2017 total of $34.96 billion. Global sales in August 2018 were 1.7 percent higher than the July 2018 total of $39.49 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales continued to bound upward in August, easily outperforming sales from last August and narrowly surpassing last month’s total,” said John Neuffer, president and CEO, Semiconductor Industry Association. “While year-to-year growth has moderated somewhat in recent months, sales remain strong across every major semiconductor product category and regional market, with the China and Americas markets standing out with the largest year-year growth.”

Regionally, sales increased compared to August 2017 in China (27.3 percent), the Americas (15.0 percent), Europe (9.5 percent), Japan (8.4 percent), and Asia Pacific/All Other (4.7 percent). Sales were up compared to last month in China (2.1 percent), the Americas (3.6 percent), and Asia Pacific/All Other (1.3 percent), and decreased slightly inJapan (-0.1 percent), and Europe (-1.4 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

By Jay Chittooran

Last week, SEMI joined a coalition of business groups in calling for Ambassador Robert Lighthizer, U.S. Trade Representative, to enact an exclusion process for the most recent tranche of tariffs on $200 billion in goods imported from China.

While an exclusion process was provided for in the previous tariff lists, which cover about $50 billion in goods, the administration has said that no similar process will be provided on the most recent tariffs on $200 billion (List 3), which took effect Monday. SEMI members will face millions of dollars in additional duties as a result of these tariffs. This action will also curb growth, stifle innovation, and introduce significant uncertainty in the semiconductor industry.

Americans for Free Trade is a diverse coalition, which includes hundreds of companies across the United States, to illustrate the impacts of tariffs on American businesses, consumers and manufacturers. SEMI is a member of this coalition. The full text of the letter can be found here.

Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Originally published on the SEMI blog.

Visionary keynote speakers and industry luminaries will share insights on Smart technologies that are shaping the future at SEMICON Japan 2018, the largest and most influential exhibition in Japan for electronics manufacturing. Registration for SEMICON Japan, at Tokyo Big Sight in Tokyo on December 12-14, is now open for the exhibition and programs.

Themed “Dreams Start Here,” SEMICON Japan 2018 reflects the promise of AI (artificial intelligence), Internet of Things (IoT) and Smart technologies.

SEMICON Japan 2018 is the gathering place to connect the people, technologies and business across the electronics manufacturing supply chain, from semiconductor manufacturing to autonomous cars, robotics and other Smart applications.

Representing segments across the supply chain, the industry visionaries will present at SEMICON Japan’s SuperTHEATER in seven keynote forums, all with simultaneous English-Japanese translation.

Opening Keynotes – Alternative Future Envisioned by New Leaders 

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Motoi Ishibashi

CTO of Rhizomatiks, a leading media art company in Japan that staged the Rio Olympic Games closing ceremony. It will orchestrate the opening performance at SEMICON Japan 2018.

 
 

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Toru Nishikawa

President & CEO of Preferred Networks, a deep-learning research startup conducting collaborative research with technology giants including Toyota, Fanuc, NVIDA, Intel and Microsoft.
 

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Semiconductor Executive Forum – Views by Top Three in the Era of Smart World 

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Dr. Yasuo Naruke

President and CEO of Toshiba Memoryrepresenting memory sector

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Thomas Morgenstern

Senior VP and GM of GLOBALFOUNDRIESrepresenting foundry sector

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Junko Sunaga

President of Qualcomm Japan representing fabless sector

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SMART Transportation Summit – The Future Created by SMART Innovation 

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Takashi Imai

President and CEO of Toyota Info Technology Center

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Kazuyuki Iwata

Operating officer, Energy & Mobility Management System Executive LPL,

at Honda R&D

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Hajime Kumabe

Executive director, Engineering Research

and Development Center, at Denso
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Klaus Meder

President and representative director of Bosch
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Additional SEMICON Japan 2018 highlights include:

  • SEMI Market Forum on the growing China and global semiconductor ecosystem with speakers from IHS Markit and SEMI.
  • SMART Technology Forum on the front line of AI with speakers from the University of Tokyo, Microsoft Japan, Amazon Web Services and DefinedCrowd.
  • Manufacturing Innovation Forum on EUV lithography with speakers from ASML and Xilinx.
  • Mirai (future) Vision Forum on how advanced science and technology could transform the human body with speakers from Leave a Nest and more.

SEMICON Japan Sponsors

  • Platinum sponsors include Disco Corporation, Hitachi High-Technologies Corporation, Screen Semiconductor Solutions Co., Ltd., and Tokyo Electron Limited.
  • Gold sponsors include Advantest, Applied Materials, Ebara, Fasford Technology, Hitachi Chemical, JSR, Kokusai Electric, Lam Research, Nikon, and Tokyo Seimitsu.

For more information and to register for SEMICON Japan, click here.

Silicon carbide (SiC), a material known for its toughness with applications from abrasives to car brakes, to high-temperature power electronics, has enjoyed renewed interest for its potential in quantum technology. Its ability to house optically excitable defects, called color centers, has made it a strong candidate material to become the building block of quantum computing.

Now, a group of researchers has created a list of “recipes” physicists can use to create specific types of defects with desired optical properties in SiC. In one of the first attempts to systematically explore color centers, the group used proton irradiation techniques to create the color centers in silicon carbide. They adjusted proton dose and temperature to find the right conditions that reliably produce the desired type of color center. The team reports their findings in Applied Physics Letters, from AIP Publishing.

Atomic defects in the lattice of SiC crystals create color centers that can emit photons with unique spectral signatures. While some materials considered for quantum computing require cryogenically low temperatures, color centers in SiC can emit at room temperature. As the push to create increasingly smaller devices continues into atom-scale sensors and single-photon emitters, the ability to take advantage of existing SiC integrated circuit technology makes the material a standout candidate.

To create the defects, Michael Krieger and his colleagues bombarded SiC samples with protons. The team then let the SiC go through a heating phase called annealing. “We’re doing a lot of damage to these crystals,” Krieger said. “However, during annealing, the crystal structure recovers, but defects are also formed — some of them are the desired color centers.”

To ensure that their recipes are compatible with usual semiconductor technology, the group opted to use proton irradiation. Moreover, this approach doesn’t require electron accelerators or nuclear reactors like other techniques used to create color centers.

The data from using different doses and annealing temperatures showed that producing defects in SiC follows a pattern. Initially protons generate predominantly silicon vacancies in the crystal, then those vacancies sequentially transform into other defect complexes.

Studying the defects’ low-temperature photoluminescence spectra led the team to discover three previously unreported signatures. The three temperature-stable (TS) lines were shown to correlate with proton dose and annealing temperature.

Krieger said these TS lines have exciting properties and further research is already going on as the group hopes to utilize and control those defects for use in SiC-based quantum technology devices.