Category Archives: Wafer Processing

Rambus Inc. (NASDAQ: RMBS), a developer of digital security, semiconductor and IP products and services, today announced the appointment of Sanjay Saraf to its board of directors, effective immediately.

Mr. Saraf currently serves as the executive vice president and chief technology officer at YapStone, where he is responsible for product engineering, infrastructure, operations, information security, research and development, and product innovation. Prior to YapStone, he was chief technology officer at Western Union Digital and was responsible for digital transformation and leading product engineering teams. Throughout Mr. Saraf’s career, he successfully launched mobile payments applications in over 50 countries, integrated payments with over a thousand banks in over 70 countries and processed over $80 billion in principal volume in over 200 countries.

“Sanjay’s accomplished background in mobile payments and digital transformation makes him an outstanding addition to the Board. He will bring strong leadership, especially for our growing security and payments business,” said Eric Stang, chairman of the Board at Rambus. “We are pleased to welcome Sanjay to the Board and look forward to his collaboration and contribution.”

“I am honored and thrilled to be joining Rambus’ Board of Directors,” said Saraf. “I look forward to using my leadership experience and knowledge of the payments and security industry to support Rambus’ strategy and growth initiatives.”

Mr. Saraf holds a B.S. in Engineering from the University of Bombay and a M.S. in Engineering from the University of Wyoming. He will be serving on the Board alongside E. Thomas Fisher, Emiko Higashi, Charles Kissner, David Shrigley and Eric Stang.

Scientists from the University of Konstanz and Paderborn University have succeeded in producing and demonstrating what is known as Wannier-Stark localization for the first time. In doing so, the physicists managed to overcome obstacles that had so far been considered insurmountable in the field of optoelectronics and photonics. Wannier-Stark localization causes extreme imbalance within the electric system of crystalline solids. “This fundamental effect was predicted more than 80 years ago. But it has remained unclear ever since whether this state can be realized in a bulk crystal, that is, on the level of chemical bonds between atoms,” says Professor Alfred Leitenstorfer, Professor of Experimental Physics at the University of Konstanz. Analogues of the effect have so far been demonstrated only in artificial systems like semiconductor superlattices or ultracold atomic gases. In a bulk solid, Wannier-Stark localization can only be maintained for an extremely short period of time, shorter than a single oscillation of infrared light. Using the ultrafast laser systems at the University of Konstanz, Wannier-Stark localization has now been demonstrated for the first time. The experiment was conducted in a high-purity gallium arsenide crystal grown at ETH Zurich using epitaxial growth. The research results were published in the scientific journal Nature Communications on 23 July 2018.

What is Wannier-Stark localization?

If we tried to picture the atoms of a crystal, it would have to be as a three-dimensional grid composed of small beads that repel each other and are only kept together by rubber bands. The system remains stable as long as the rubber band is as strong as the repulsion is. If this is the case, the beads neither move closer to each other, nor do they move away from each other – the distance between them remains about the same. Wannier-Stark localization occurs when the rubber bands are removed abruptly. It is the electronic state that happens at the precise moment in time when the rubber bands have already gone but the beads still remain in place: The chemical bonds that hold the crystal together have been suspended.

If this state is maintained for too long, the beads will break apart and the crystal dissolves. To analyze Wannier-Stark localization, the physicists had to remove the stabilizing structures, capture the system within a fraction of a light oscillation using light pulses, and finally to stabilize it again to prevent the atoms from breaking apart. The experiment was made possible through the highly intense electric field of an ultrashort infrared light pulse, which is present in the crystal for a few femtoseconds only. “This is what we specialize in: studying phenomena that only exist on very short time scales,” explains Alfred Leitenstorfer.

“In perfect insulators and semiconductors, electronic states expand throughout the entire crystal. According to an 80-year-old prediction, this changes as soon as electrical voltage is applied,” says Professor Torsten Meier from Paderborn University. “If the electric field inside the crystal is strong enough, the electronic states can be localized to a few atoms. This state is called the Wannier-Stark ladder”, explains the physicist, who is also Vice-President for International Relations at Paderborn University.

New electronic characteristics

“A system that deviates so extremely from its equilibrium has completely new characteristics,” says Alfred Leitenstorfer about why this state is so interesting from a scientific perspective. The short-lived Wannier-Stark localization correlates with drastic changes to the electronic structure of the crystal and results, for example, in extremely high optical nonlinearity. The scientists also assume that this state is chemically particularly reactive.

The first-ever experimental realization of Wannier-Stark localization in a gallium arsenide crystal was made possible through highly intense Terahertz radiation with field intensities of more than ten million volts per centimetre. The application of more ultrashort optical light pulses resulted in changes to the crystal’s optical characteristics, which was instrumental to proving this state. “If we use suitably intense light pulses consisting of a few oscillations lasting some ten femtoseconds only, we can realize the Wannier-Stark localization for a short period of time,” says Alfred Leitenstorfer. “Our readings match the theoretical considerations and simulations carried out both by my own research team and by that of my colleague, Professor Wolf Gero Schmidt,” adds Torsten Meier. The researchers are planning to study the extreme state of Wannier-Stark localization on the atomic scale in more detail in the future and intend to make its particular characteristics usable.

Reaching their highest recorded quarterly level ever on robust demand, worldwide silicon wafer area shipments rose 2.5 percent in the second quarter of 2018 to 3,160 million square inches from 3,084 million square inches the previous quarter, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. New quarterly total area shipments are 6.1 percent higher than second quarter 2017 shipments.

“The second calendar quarter of the year typically enjoys a volume increase over the first quarter,” said Neil Weaver, chairman SEMI SMG and Director, Product Development and Applications Engineering of Shin Etsu Handotai America. “This quarter is no exception. Continued solid demand is driving record wafer volume shipments.”

Silicon* Area Shipment Trends

Millions of Square Inches
1Q2017
2Q2017
3Q2017
4Q2017
1Q2018
2Q2018
Total
2,858
2,978
2,997
2,977
3,084
3,160
*Semiconductor applications only
Source: SEMI, (www.semi.org), July

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices, or chips, are fabricated.

All data cited in this release includes polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to end users.

By Jay Chittooran, Public Policy Manager, SEMI 

Two months after opposing $34 billion in U.S. trade tariffs on behalf of the U.S. semiconductor manufacturing industry, Jonathan Davis, global vice president of industry advocacy at SEMI, this week spoke out against an additional $16 billion duties on Chinese goods. Testifying before the same U.S. interagency panel mulling the merits of the tariffs, Davis called for the removal of 29 tariff lines covering items critical to semiconductor manufacturing including machines and spare parts used to make, wafers, flat panel displays and masks.

In his testimony to the panel, Davis stressed that while SEMI supports stronger protections against the theft of valuable intellectual property (IP), tariffs do little to address U.S. concerns over IP loss. Over the past month, SEMI has also submitted written comments and opposed the tariffs in public testimony. The panel includes representatives from the U.S. Trade Representative (USTR), Departments of Treasury, Commerce, State and Defense, and the Council of Economic Advisers.

Also testifying, Joe Pon, corporate vice president at Applied Materials, explained that the proposed tariffs will harm small and midsized companies and other U.S. business interests. Describing the tariffs as a tax on exports of high-value U.S. goods, Pon said the duties give non-U.S. firms an unfair competitive advantage.

In a parallel push to Davis’s testimony, SEMI, with more than 10 representatives from six member companies, met with 16 congressional offices this week to underscore the damage the tariffs would wreak on the U.S. semiconductor industry. The fallout would include higher operating costs, fewer exports and slower innovation. The tariffs would also curb industry growth and put thousands of high-paying, high-skill jobs at risk. SEMI pressed congressional leaders to reject the tariffs and support a push for congress to re-assert itself on trade policy.

Tariffs to cost U.S. SEMI members more than $500 million

SEMI estimates that the second list of proposed tariffs, covering about $16 billion in Chinese goods, will cost its 400 U.S. members more than $500 million annually in additional duties.

The tariffs on $34 billion in Chinese goods, which took effect July 6, impact products such as test and inspection equipment as well as spare parts that enter the U.S. from China. That round of tariffs will cost SEMI member companies and estimated tens of millions of dollars annually.

SEMI public policy team asks members to review tariff list

Looking ahead, SEMI encourages members to review the newly released $200 billion tariff list, determine any impact to their businesses and share their findings with SEMI’s public policy team.

The U.S. Trade Representative (USTR) has published the exclusion process for products subject to the China 301 tariffs. If your company’s products are subject to tariffs, you can request an exclusion.

In evaluating product exclusion requests, the USTR will consider whether a product is available from a source outside of China, whether the additional duties would cause severe economic harm to the requestor or other U.S. interests, and whether the product is strategically important or related to Chinese industrial programs (such as “Made in China 2025”).

The deadline for submitting product exclusion requests to USTR is October 9, 2018. Approved exclusions will be effective for one year upon approval and retroactive to July 6, 2018.

More information including the process for submitting the product exclusion request can be found here.

Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

SiFive, the provider of commercial RISC-V processor IP, today welcomed Chipus Microelectronics, a semiconductor company with proven expertise in the development of ultra-low-power (ULP), low-voltage, analog and mixed-signal integrated circuits, to the growing DesignShare ecosystem. Through the partnership, Chipus will provide ULP IP for power management and ULP RF Front-Ends.

Chipus’ customizable technology will make it easier for SiFive customers to save power and extend battery life for IoT edge devices. Chipus also plans to add temperature sensors and switched regulators to the DesignShare program in the near future.

“Chipus is thrilled to partner up with SiFive to bring more chip design opportunities to reality, enabling innovation with our Ultra-Low-Power and simple-to-customize IP solutions,” said Murilo Pilon Pessatti, CEO and co-founder of Chipus. “Our mission, together with SiFive, is to enable innovation. With our expertise, Chipus looks forward to contributing to new IoT applications and edge devices.”

The availability of Chipus’ ULP IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, Chipus and other DesignShare partners provide low- or no-entry fee IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization.

“Startups today go through extensive processes, from sourcing viable IP to negotiating legal contracts, before they can even develop a prototype,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With Chipus joining our growing DesignShare economy, we continue to simplify the prototyping process and spur innovation across the industry.”

Since DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL. For more information on DesignShare and to see the complete list of available technologies, visit www.sifive.com/designshare.

In a key move to inspire the next generation of innovators, the School District of Osceola County (SDOC) today became the first school district to join the SEMI High Tech U (HTU) Certified Partner Program (CPP), a curriculum that prepares high-school students to pursue careers in STEM fields.

Under the program sponsored by the SEMI Foundation, SDOC will independently deliver HTU programs to local students at the Osceola Technical College Campus, in Kissimmee, Florida. SEMI Foundation awarded SDOC the certification today at a graduation ceremony for HTU students.

“SDOC’s partnership with the SEMI Foundation gives young people and families in our community exposure to high-tech career opportunities and the educational pathways to reach their goals,” said Debra Pace, superintendent of School District of Osceola County. “Our industry partners – including Mercury, University of Central Florida, BRIDG, Osceola Technical College, imec, Neo City and the Osceola County Education Foundation – have all made it possible for SDOC to offer this amazing opportunity to students.”

“We are delighted to partner with SDOC in our common goal to motivate the next generation of innovators,” said Leslie Tugman, executive director of the SEMI Foundation. “The School District of Osceola County is well-positioned to put college-bound high school students on a track that speeds the time from graduation to employment in high technology. SDOC’s certification is a tremendous benefit for it students, the community and employers in the fast-growing Central Florida tech corridor.”

To win the certification, SDOC delivered HTU over the past three years with guidance and instruction from SEMI. SDOC is only the second organization to receive the certification.

The nonprofit SEMI Foundation has been delivering its flagship program, SEMI High Tech U, at industry sites around the world since 2001 to emphasize the importance of STEM skills and inspire young people to pursue careers in high-technology fields. HTU students meet engineers and STEM volunteer instructors from industry for site tours and hands-on classroom activities such as etching wafers, making circuits, coding and training for professional interviews.

SEMI’s Certified Partner Program identifies organizations that provide quality training and can recruit and educate local high-school students in the value of careers in science, technology, engineering and math (STEM). Participating organizations are trained to deliver the unique SEMI curriculum with the support of volunteer instructors from the high-tech and STEM industries. SEMI High Tech U is the longest-running STEM career exploration program in the United States with documented student impact. Since inception, SEMI has reached over 8,000 high-school students in 12 states and nine countries with its award-winning program.

SEMI Foundation is a 501(c)(3) nonprofit charitable organization founded in 2001 to support education and career awareness in the electronics and high-tech fields through career exploration programs and scholarships. For more information, visit www.semifoundation.org.

Semiconductor Research Corporation (SRC), today announced the release of $26 million in added research funding for its New Science Team (NST) Joint University Microelectronics Program (JUMP). JUMP will fund 24 additional research projects spanning 14 unique U.S. universities. The new projects will be integrated into JUMP’s six existing research centers. NST will continue to distribute funds over its five-year plan, and industrial sponsors are welcome to join to further accentuate those plans.

The awards have been given to 27 faculty and will enhance the program’s expertise in technical areas such as atomic layer deposition (ALD), novel ferroelectric and spintronic materials and devices, 3D and heterogeneous integration, thermal management solutions, architectures for machine learning and statistical computing, memory abstractions, reconfigurable RF frontends, and mmWave to THz arrays and systems for communications and sensing.

“The goal of the NST project is not only to extend the viability of Moore’s Law economics through 2030, but to also change the research paradigm to one of co-optimization across the design hierarchy stack through multi-disciplinary teams,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “Our strategic partnerships with industry, academia, and government agencies foster the environment needed to realize the next wave of semiconductor technology innovations.”

“A new wave of fundamental research is required to unlock the ultimate potential of autonomous vehicles, smart cities, and Artificial Intelligence (AI),” said Dr. Michael Mayberry, Senior Vice President and Chief Technology Officer of Intel and the elected Chairman of the NST Governing Council. “Such advances will be fueled by novel and far-reaching improvements in the materials, devices, circuits, architectures, and systems used for computing and communications.”

The JUMP program, a consortium consisting of 11 industrial participants and the Defense Advanced Research Projects Agency (DARPA), is one of two complementary research programs for the NST project—a 5-year, greater than $300 million SRC initiative launched this January. JUMP and its six thematic centers will advance a new wave of fundamental research focused on the high-performance, energy-efficient microelectronics for communications, computing, and storage needs for 2025 and beyond.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today welcomed newly announced research partnerships between the Defense Department’s Defense Advanced Research Projects Agency (DARPA) and research teams from industry and academia that aim to bolster long-term semiconductor research. The research partnerships, part of new programs within DARPA’s Electronics Resurgence Initiative (ERI), will target advances in semiconductor circuit design, materials, and systems architectures. The selected research teams were unveiled yesterday in San Francisco during the first annual DARPA ERI Summit, a three-day event bringing together hundreds of members of the microelectronics community.

“As the brains of modern electronics, semiconductors are central to America’s economy, national security, and global competitiveness,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The DARPA research partnerships announced yesterday will help catalyze transformational advances in semiconductor technology and enhance semiconductors’ positive impacts on our country.”

The ERI is divided into three main research thrust areas – Design, Materials & Integration, and Architectures. Each thrust area will feature two new research programs. The Design research thrust area will include the Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program. The Materials & Integration research thrust area will include the Three-Dimensional Monolithic System-on-a-Chip (3DSoC) program and the Foundations Required for Novel Compute (FRANC) program. The ERI Architectures research thrust area will include the Software Defined Hardware (SDH) program and the Domain-specific System on Chip (DSSoC) program.

“The semiconductor industry plows about one-fifth of its revenues into R&D – among the highest shares of any sector – and has a long record of partnering with our government to advance early-stage research,” Neuffer said. “The new DARPA research partnerships mark a major commitment to furthering semiconductor technology and keeping America at the tip of the spear globally in semiconductor innovation.”

Neuffer also noted SIA’s longstanding support for basic scientific research funded through other federal agencies such as the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), and the Department of Energy (DOE) Office of Science. He expressed the semiconductor industry’s eagerness to work with the Administration and Congress to advance research investments that will promote America’s economic and national security and technological leadership.

In total, the ERI will invest upwards of $1.5 billion over five years to jumpstart innovation in the electronics industry. In addition to fostering advancements in semiconductor technologies used for national security, the ripple effect from this research will be felt across the full range of semiconductor applications: communications, computing, health care, transportation, clean energy, and countless others. For more information about the Electronics Resurgence Initiative and the first annual ERI Summit, please visit http://www.eri-summit.com/.

SiFive, a provider of commercial RISC-V processor IP, today announced Brad Holtzinger as Vice President of Worldwide Sales, where he will work with the existing global portfolio of SiFive customers and onboard new clients seeking to take advantage of the company’s market-leading Core IP.  Holtzinger brings more than 30 years of embedded industry experience in sales, marketing and engineering.

“It is rare to see a company rapidly disrupting the silicon sector,” Holtzinger said. “I look forward to joining the SiFive team and supporting our customers and partners globally in adopting RISC-V and SiFive’s IP to move the industry forward.”

Previously, Holtzinger was the Vice President of Worldwide Sales for MIPS Technologies where he led licensing and sales of its global IP portfolio.  While at MIPS, Holtzinger drove the company to record sales and negotiated the sale and licensing of the MIPS patent portfolio to Bridge Crossing for $350 million and the sale of the remaining company to Imagination.

Prior to MIPS, he led the sales, operations and business development efforts as well as held the position of CEO for a number of privately funded and venture backed startups. He also founded the OEM Systems division of Force Computers, which was sold to Solectron for approximately $190 million.

Holtzinger started his career at Motorola as an embedded hardware and software design engineer, where he authored Motorola’s Technical Training class on Unix® System V and eventually was one of the founding members of Motorola’s Microcomputer Group, (MCG), that sold OEM systems and VME boards.  Holtzinger received his bachelor’s degree in electrical engineering from Purdue University and was an instructor at University of California, Berkeley.

“SiFive is excited to bring someone with Brad’s decades-long silicon sales leadership to the SiFive executive team,” said Naveed Sherwani, CEO of SiFive. “His experience leading a world-class sales organization and embedded hardware expertise will help continue to propel SiFive customer adoption.”

Semiconductor revenues are expected to increase 12.8% in 2018 as a result of continued strong memory prices. Units are expected to grow 7.2%. The forecast is based on moderate smartphone sales with a possible return to lower memory prices in the second half of the year. This, among other market issues, will push 2018 wafer demand to over 115 million units in 300mm equivalents according to Semico Research’s newest report, Semico Wafer Demand Update Q2 2018 (MA111-18).

“Semiconductor manufacturers are rolling out new products targeted at artificial intelligence applications. Products require both the most advanced technologies for AI training functions as well as potentially high-volume products for edge devices,” says Joanne Itow, Manager Manufacturing Research for Semico. “On the other side of the technology spectrum, mature processes for sensors and analog products such as biometric sensors, RF and power management continue to be in high demand aided by growth in Internet of Things (IoT) applications along with more ‘smart devices’ that are beginning to build in algorithms that are the precursor to full-fledged AI devices.”

Key findings include:

  • 2018 NAND revenues are expected to increase 18.9%.
  • MCU revenues are expected to exceed $17 billion in 2018.
  • Total Communication MOS Logic wafer demand is expected to increase 4.0% in 2018.
  • Sensor units are expected to grow 20.4% in 2018.