Category Archives: Wafer Processing

North America-based manufacturers of semiconductor equipment posted $2.49 billion in billings worldwide in June 2018 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 8.0 percent lower than the final May 2018 level of $2.70 billion, and is 8.1 percent higher than the June 2017 billings level of $2.30 billion.

“Global billings of North American equipment manufacturers declined for the current month by 8 percent from the historic high but is still 8 percent higher than billings for the same period last year,” said Ajit Manocha, president and CEO of SEMI. “Billings remain robust.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
January 2018
$2,370.1
27.5%
February 2018
$2,417.8
22.5%
March 2018
$2,431.8
16.9%
April 2018
$2,689.9
25.9%
May 2018 (final)
$2,702.3
19.0%
June 2018 (prelim)
$2,485.7
8.1%

Source: SEMI (www.semi.org), July 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

Toshiba Memory Corporation today announced that it has developed a prototype sample of 96-layer BiCS FLASH, its proprietary 3D flash memory, with 4-bit-per-cell (quad level cell, QLC) technology that boosts single-chip memory capacity to the highest level yet achieved.

Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September, and expects to start mass production in 2019.

The advantage of QLC technology is pushing the bit count for data per memory cell from three to four and significantly expanding capacity. The new product achieves the industry’s maximum capacity [1] of 1.33 terabits for a single chip which was jointly developed with Western Digital Corporation.

This also realizes an unparalleled capacity of 2.66 terabytes with a 16-chip stacked architecture in one package. The huge volumes of data generated by mobile terminals and the like continue to increase with the spread of SNS and progress in IoT, and the need to analyze and utilize that data in real time is expected to increase dramatically. That will require even faster than HDD, larger capacity storage and QLC products using the 96-layer process will contribute a solution.

A packaged prototype of the new device will be exhibited at the 2018 Flash Memory Summit in Santa Clara, California, USA from August 6th to 9th.

Looking to the future, Toshiba Memory will continue to improve memory capacity and performance and to develop 3D flash memories that meet diverse market needs, including the fast expanding data center storage market.

Rahul Goyal of Intel has been elected to a one-year term as board chair of Silicon Integration Initiative, a research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations.

Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science, Pilani, India, and a master’s degree in computer engineering from Syracuse University, Syracuse, N.Y.

In its upcoming Mid-Year Update to The McClean Report 2018 (to be released at the end of July), IC Insights forecasts that the 2018 global electronic systems market will grow 5% to $1,622 billion while the worldwide semiconductor market is expected to surge by 14% this year to $509.1 billion, exceeding the $500.0 billion level for the first time.  If the 2018 forecasts come to fruition, the average semiconductor content in an electronic system will reach 31.4%, breaking the all-time record of 28.8% that was set in 2017 (Figure 1).

Figure 1

Historically, the driving force behind the higher average annual growth rate of the semiconductor industry as compared to the electronic systems market is the increasing value or content of semiconductors used in electronic systems.  With global unit shipments of cellphones (-1%), automobiles (3%), and PCs (-1%) forecast to be weak in 2018, the disparity between the moderate growth in the electronic systems market and high growth of the semiconductor market is directly due to the increasing content of semiconductors in electronic systems.

While the trend of increasing semiconductor content has been evident for the past 30 years, the big jump in the average semiconductor content in electronic systems in 2018 is expected to be primarily due to the huge surge in DRAM and NAND flash ASPs and average electronic system sales growth this year. After slipping to 30.2% in 2020, the semiconductor content percentage is expected to climb to a new high of 31.5% in 2022.  IC Insights does not anticipate the percentage will fall below 30% any year through the forecast period.

The trend of increasingly higher semiconductor value in electronic systems has a limit.  Extrapolating an annual increase in the percent semiconductor figure indefinitely would, at some point in the future, result in the semiconductor content of an electronic system reaching 100%.  Whatever the ultimate ceiling is, once it is reached, the average annual growth for the semiconductor industry will closely track that of the electronic systems market (i.e., about 4%-5% per year).

Silicon Labs (NASDAQ: SLAB), a provider of silicon, software and solutions for a smarter, more connected world, announces two new executive appointments. Daniel Cooley has been named Senior Vice President and Chief Strategy Officer. In this new role, Mr. Cooley will focus on Silicon Labs’ overall growth strategy, business development, new technologies and emerging markets. Matt Johnson, a semiconductor veteran with more than 15 years of industry experience, joins Silicon Labs as Senior Vice President and General Manager of IoT products. Both executives will report to Tyson Tuttle, CEO.

Mr. Cooley has led Silicon Labs’ IoT business for the past four years. Under his leadership, the company built an industry-leading portfolio of secure connectivity solutions, with IoT revenue now exceeding a $100 million per quarter run rate. Mr. Cooley joined Silicon Labs in 2005 as a chip design engineer developing broadcast audio products and short-range wireless devices. Over the years, he has served in various senior management, engineering and product management roles at the company’s Shenzhen, Singapore, Oslo and Austin sites. The new role leverages Mr. Cooley’s proven talents in strategy and business development.

Mr. Johnson will lead Silicon Labs’ IoT business including the development and market success of the company’s broad portfolio of wireless products, microcontrollers, sensors, development tools and wireless software. Mr. Johnson has a track record of growing revenue and leading large global teams, and he brings a deep understanding of analog, MCU and embedded software businesses to Silicon Labs. Previously, he served as Senior Vice President and General Manager of automotive processing products and software development at NXP Semiconductors/Freescale, as well as SVP and General Manager of mobile solutions at Fairchild Semiconductor.

“With these executive appointments, we are expanding our ability to execute on large and growing market opportunities in the IoT,” said Tyson Tuttle, CEO of Silicon Labs. “Together, these two talented leaders will help Silicon Labs scale the business to the next level and focus on future growth.”

By Ed Korczynski

To fulfill the promise of the Internet of Things (IoT), the world needs low-cost high-bandwidth radio-frequency (RF) chips for 5th-generation (5G) internet technology. Despite standards not being completely defined yet it is clear that 5G hardware will have to be more complex than 4G kit, because it will have to provide a total solution that is ultra-reliable with at least 10 Gb/second bandwidth. A significant challenge remains in developing new high-speed transistor technologies for RF communications with low power to allow IoT “edge” devices to operate reliably off of batteries.

At the most recent Imec Technology Forum in Antwerp, Belgium, Nadine Collaert, Distinguished MTS of imec, discussed recent research results from the consortium’s High-Speed Analog and RF Program. In addition to working on core transistor fabrication technology R&D, imec has also been working on system-technology co-integration (STCO) and design-technology co-integration (DTCO) for RF applications.

Comparing the system specifications needed for mobile handsets to those for base-stations, transmitter power consumption should be 10x lower, while the receiver power consumption needs to be 2x lower. Today using silicon CMOS transistors, four power amplifiers alone consume 65% of a transmitter chip’s power. Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) built using compound semiconductors such as gallium-arsenide (GaAs), gallium-nitride (GaN), or indium-phosphide (InP) provide excellent RF device results. However, compared to making CMOS chips on silicon, HBT and HEMT manufacturing on compound semiconductor substrates is inherently expensive and difficult.

Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) both rely upon the precise epitaxial growth of semiconductor layers, and such growth is easier when the underlying substrate material has similar atomic arrangement. While it is much more difficult to grow epi-layers of compound semiconductors on silicon wafers, imec does R&D using 300-mm diameter silicon substrates with a goal of maintaining device quality while lowering production costs. The Figure shows cross-sections of the two “tracks” of III-V and GaN transistor materials being explored by imec for future RF chips.

III-V on Silicon and GaN-on-Silicon RF device cross-sections, showing work on both Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) for 5G applications. (Source: imec)

Imec’s High-Speed Analog/RF Program objectives include the following:

  • High-speed III-V RF devices using low-cost, high-volume silicon-compatible processes and modules,
  • Co-optimization with advance silicon CMOS to reduce form factor and enable power-efficient systems with higher performance, and
  • Technology-circuit design co-optimization to enable complex RF-FEM modules with heterogeneous integration.

5G technology deployment will start with speeds below 6GHz,  because technologies in that range have already been proven and the costs are known. However, after five years the frequency will change to the “mm-wave” range with the first wavelength band at ~28GHz. GaN material with a wide bandgap and high charge-density has been a base-station technology, and it could be an ideal material for low-power mm-wave RF devices for future handsets.

This R&D leverages the III-V on silicon capability that has been developed by imec for CMOS:Photonic integration. RF transistors could be stacked over CMOS transistors using either wafer- or die-stacking, or both could be monolithically co-integrated on one silicon chip. Work on monolithic integration of GaN-on-Silicon is happening now, and could also be used for photonics where faster transistors can improve the performance of optical links.

The Mid-Year Update to the 2018 McClean Report revises IC Insights’ worldwide economic and IC industry forecasts through 2022 that were originally presented in The 2018 McClean Report issued in January.

The Figure shows that IC Insights forecasts that China-headquartered companies will spend $11.0 billion in semiconductor industry capex in 2018, which would represent 10.6% of the expected worldwide outlays of $103.5 billion.  Not only would this amount be 5x what the Chinese companies spent only three years earlier in 2015, but it would also exceed the combined semiconductor industry capital spending of Japan- and Europe-headquartered companies this year.

Since adopting the fab-lite business model, the three major European producers have represented a very small share of total semiconductor industry capital expenditures and are forecast to account for only 4% of global spending in 2018 after representing 8% of worldwide capex in 2005.  Although there may be an occasional spike in capital spending from European companies (e.g., the surge in spending from ST and AMS in 2017), IC Insights believes that Europe-headquartered companies will represent only 3% of worldwide semiconductor capital expenditures in 2022.

It should be noted that several Japanese semiconductor companies have also transitioned to a fab-lite business model (e.g., Renesas, Sony, etc.).  With strong competition reducing the number and strength of Japanese semiconductor manufacturers, the loss of its vertically integrated businesses and thus missing out on supplying devices for several high-volume end-use applications, and its collective shift toward fab-lite business models, Japanese companies have greatly reduced their investment in new wafer fabs and equipment. In fact, Japanese companies are forecast to represent only 6% of total semiconductor industry capital expenditures in 2018, a big decline from the 22% share they held in 2005 and an even more precipitous drop from the 51% share they held in 1990.

Although China-headquartered pure-play foundry SMIC has been part of the list of major semiconductor industry capital spenders for quite some time, there are four additional Chinese companies that are forecast to become significant semiconductor industry spenders this year and next—memory suppliers XMC/YMTC, Innotron, JHICC, and pure-play foundry Shanghai Huali.  Each of these companies is expected to spend a considerable amount of money equipping and ramping up their new fabs in 2018 and 2019.

Due to the increased spending by startup China-based memory manufacturers, IC Insights believes that the Asia-Pac/Others share of semiconductor industry capital spending will remain over 60% for at least the next couple of years.

HEIDENHAIN announced the appointment of David Doyle as CEO of HEIDENHAIN CORPORATION, effective Oct. 1, 2018.  At that time, Doyle will assume full responsibility for the HEIDENHAIN CORPORATION customer-focused operations for the U.S., Canada and Mexico. This change will complete the succession plan for Rick Korte, current CEO of HEIDENHAIN CORPORATION who will be retiring at that time after more than 34 years of service.

“I am happy to announce the next phase of the succession plan for our North American operations, with the promotion of David Doyle to CEO,” said Korte. “I have the utmost confidence in David and trust he will continue to grow our business and support our customers with World Class service in all areas.”

Doyle started with HEIDENHAIN CORPORATION in 2016 as Vice President of Sales & Marketing, bringing with him more than twenty-five years of experience in international capital equipment business and technical support management.  He currently serves as its President and Managing Director.

“I want to thank Rick Korte for leading HEIDENHAIN CORPORATION in tremendous growth over these many years, and for the guidance he has provided to not only myself, but to the many staff members who have called HEIDENHAIN home for so long,” said Doyle.  “I am looking forward to leading the HEIDENHAIN CORPORATION team through the next phase of development and to reaching our growth objectives in North America by continuing to put our Customers First.”

DR. JOHANNES HEIDENHAIN GmbH, headquartered in Traunreut, Germany, develops and supports motion control feedback solutions for the machine tool, semiconductor, electronics assembly and test, metrology, automation, medical, energy, biotechnology and other global markets. HEIDENHAIN employs approximately 6,000 people worldwide in its core business activities.

Leti, a research institute of CEA Tech, and Soitec, a designer and manufacturer of innovative semiconductor materials, today announced a new collaboration and five-year partnership agreement to drive the R&D of advanced engineered substrates, including SOI and beyond. This agreement brings the traditional Leti-Soitec partnership to a whole new dimension and includes the launch of a world-class prototyping hub associating equipment partners to pioneer with new materials, The Substrate Innovation Center will feature access to shared Leti-Soitec expertise around a focused pilot line. Key benefits for partners include access to early exploratory sampling and prototyping, collaborative analysis, and early learning at the substrate level, eventually leading to streamlined product viability and roadmap planning at the system level.

Leading chip makers and foundries worldwide use Soitec products to manufacture chips for consumer applications targeting performance, connectivity, and efficiency with extremely low energy consumption. Applications include smart phones, data centers, automotive, imagers, and medical and industrial equipment, but this list is always growing, along with the need for flexibility to explore new applications starting at the substrate level. At the Substrate Innovation Center, located on Leti’s campus, Leti and Soitec engineers will explore and develop innovative substrate features, expanding to new fields and applications with a special focus on 4G/5G connectivity, artificial intelligence, sensors and display, automotive, photonics, and edge computing.

“Material innovation and substrate engineering make entire new horizons possible. The Substrate Innovation Center will unleash the power of substrate R&D collaboration beyond the typical product road maps, beyond the typical constraints,” said Paul Boudre, Soitec CEO. “The Substrate Innovation Center is a one-of-a-kind opportunity open to all industry partners within the semiconductor value chain.”

Whereas a typical manufacturing facility has limited flexibility to try new solutions and cannot afford to take risks with prototyping, the mission of the Substrate Innovation Center is to become the world’s preferred hub for evaluating and designing engineered substrate solutions to address the future needs of the industry, inclusive of all the key players, from compound suppliers to product designers. Using state of the art, quality-controlled clean room facilities, and the latest industry-grade equipment and materials, Leti and Soitec engineers will conduct testing and evaluation at all levels of advanced substrate R&D.

“Leti and Soitec’s collaboration on SOI and differentiated materials, which extends back to Soitec’s launch in 1992, has produced innovative technologies that are vital to a wide range of consumer and industrial products and components,” said Emmanuel Sabonnadière, Leti CEO. “This new common hub at Leti’s campus marks the next step in this ongoing partnership. By jointly working with foundries, fabless, and system companies, we provide our partners with a strong edge for their future products.”

BY PAUL VAN DER HEIDE, director of materials and components analysis, imec, Leuven, Belgium

To keep up with Moore’s Law, the semiconductor industry continues to push the envelope in developing new device architectures containing novel materials. This in turn pushes the need for new solid-state analytical capabilities, whether for materials characterization or inline metrology. Aside from basic R&D, these capabilities are established at critical points of the semiconductor device manufacturing line, to measure, for example, the thickness and composition of a thin film, dopant profiles of transistor’s source/drain regions, the nature of defects on a wafer’s surface, etc. This approach is used to reduce “time to data”. We cannot wait until the end of the manufacturing line to know if a device will be functional or not. Every process step costs money and a fully functional device can take months to fabricate. Recent advances in instrumentation and computational power have opened the door to many new, exciting analytical possibilities.

One example that comes to mind concerns the development of coherent sources. So far, coherent photon sources have been used for probing the atomic and electronic structure of materials, but only within large, dedicated synchrotron radiation facilities. Through recent developments, table top coherent photon sources have been introduced that could soon see demand in the semiconductor lab/fab environment.

The increased computational power now at our finger tips is also allowing us to make the most of these and other sources through imaging techniques such as ptychography. Ptychog- raphy allows for the complex patterns resulting from coherent electron or photon interaction with a sample to be processed into recognizable images to a resolution close to the sources wavelength without the requirement of lenses (lenses tend to introduce aberrations). Potential application areas extend from non-destructive imaging of surface and subsurface structures, to probing chemical reactions at sub femto-second timescales.

Detector developments are also benefiting many analytical techniques presently used. As an example, transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) can now image, with atomic resolution, heavy as well as light elements. Combining this with increased computational power, allows for further devel- opment of imaging approaches such as tomography, holography, ptychography, differential phase contrast imaging, etc. All of which allow TEM/STEM to not only look at atoms in e.g. 2D materials such as MoS2 in far greater detail, but also opens the possibility to map electric fields and magnetic domains to unprecedented resolution.

The semiconductor industry is evolving at a very rapid pace. Since the beginning of the 21st century, we have seen numerous disruptive technologies emerge; technologies that need to serve is an increasingly fragmented applications space. It’s no longer solely about ‘the central processing unit (CPU)’. Other applications ranging from the internet of things, autonomous vehicles, wearable human-electronics interface, etc., are being pursued, each coming with unique requirements and analytical needs.

Looking ten to fifteen years ahead, we will witness a different landscape. Although I’m sure that existing techniques such as TEM/STEM will still be heavily used – probably more so than we realize now (we are already seeing TEM/STEM being extended into the fab). We will also see developments that will push the boundaries of what is possible. This would range from the increased use of hybrid metrology (combining results from multiple different analytical techniques and process steps) to the development of new innovative approaches.

To illustrate the latter, I take the example of secondary ion mass spectrometry (SIMS). With SIMS, an energetic ion beam is directed at the solid sample of interest, causing atoms in the near surface region to leave this surface. A small percentage of them are ionized, and pass through a mass spectrometer which separates the ions from one another according to their mass to charge ratio. When this is done in the dynamic-SIMS mode, a depth profile of the sample’s composition can be derived. Today, with this technique, we can’t focus the incoming energetic ion beam into a confined volume, i.e. onto a spot that approaches the size of a transistor. But at imec, novel concepts were intro- duced, resulting in what are called 1.5D SIMS and self-focusing SIMS (SF-SIMS). These approaches are based on the detection of constituents within repeatable array structures, giving averaged and statistically significant information. This way, the spatial resolution limit of SIMS was overcome.

And there are exciting developments occurring here at imec in other analytical fields such as atom probe tomography (APT), photoelectron spectroscopy (PES), Raman spectroscopy, Rutherford back scattering (RBS), scanning probe microscopy (SPM), etc. One important milestone has been the development of Fast Fourier Transform-SSRM (FFT-SSRM) at imec. This allows one to measure carrier distributions in FinFETs to unparalleled sensitivity.

Yet, probably the biggest challenge materials characterization and inline metrology face over the next ten to fifteen years will be how to keep costs down. Today, we make use of highly specialized techniques developed on mutually exclusive and costly platforms. But why not make use of micro-electro-mechanical systems (MEMS) that could simultaneously perform analysis in a highly parallel fashion, and perhaps even in situ? One can imagine scenarios in which an army of such units could scan an entire wafer in the fraction of the time it takes now, or alternatively, the incorporation of such units into wafer test structure regions.