Category Archives: Wafer Processing

BY DEBRA VOGLER, SEMI, Milpitas, CA

With chipmakers looking toward 5nm manufacturing, it’s clear that traditional scaling is not dead but continuing in combination with other technologies. The industry sees scaling enabled by 3D architectures such as die stacking and the stacking of very small geometry wafers. Interconnect scaling also comes into play. This year’s Scaling Technologies TechXPOT at SEMICON West (Scaling Every Which Way! – Thursday, July 12, 2:00PM-4:00PM) will provide an update on the evolution of scaling and describe how the various players (foundry, IDM, fabless, and application developers) are jockeying for innovation leadership. As a prelude to the event, SEMI asked speakers to provide insights on important scaling trends. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/scaling-every-which-way.

Challenges for gate-all-around (GAA) and FinFET devices

Common performance boosters for gate-all-around (GAA) FETs and FinFETs include lower access resistance, lower parasitic capacitance, and stress. “However, one specific performance booster that only applies to GAA is the reduction of the spacing between the vertical wires or sheets,” says Diederik Verkest, imec distinguished member of technical staff, Semiconductor Technology and Systems.

“This reduces parasitic capacitance without affecting drive current and hence benefits both performance and power.” He further notes that imec demonstrated the first stacked gate-all-around (GAA) devices in scaled nodes. “In fact, we are the only ones that published working circuits – ring oscillators in a scaled node using industry-standard processes – in our case replacement metal gate (RMG), and embedded in situ doped source/drain (S/D) epitaxy.”

“There are two elements of the stacked GAA architecture that need to be addressed,” says Verkest. “The first is that this architecture uses epitaxially-grown layers of Si and SiGe to define the device channel. The use of grown materials for the channel and the lattice mismatch between the two materials represent a departure from the traditional fabrication of CMOS devices, so the industry needs to develop and gain confidence in novel metrology that allows for good control of the layers and also proves their low defectivity.” The second aspect is the three-dimensional nature of the GAA devices. “During the processing of these devices, we have ‘non-line-of-sight’ hidden features that are difficult to control and characterize and may also lead to new defect mechanisms that would impact yield, and possibly product reliability.”

Huiming Bu, director, Advanced Logic/Memory Research – Integration and Device, IBM Research, Semiconductor Group, says that naming of technology nodes has been used extensively for marketing strategies in “foundry land,” but the designations have lost much of their meaning as technology scaling differentiators. “That said, when it comes to technology innovation and value proposition, IBM, in conjunction with Samsung and GLOBALFOUNDRIES, has developed the GAA NanoSheet transistor for 5nm to provide a full technology node scaling benefit in density, power and performance,” says Bu (FIGURE 1). The key parameters for intrinsic device optimization when scaling to the 3nm node, explains Bu, are the NanoSheet width for better electrostatic characteristics, and the number of sheets for increased current density. Also necessary are strain engineering for carrier transport enhancement, and interconnect innovations for parasitic RC reduction.

“Beyond that, the industry needs to look into something different, something more disruptive.”

Materials challenges

Materials challenges are also a concern as the industry moves to 5nm and below. “We see increasing complexity in the material systems that are being used,” explains Verkest. One example he cites in scaled FinFET or GAA technologies is the use of two to three layers of different materials–typically metals such as TiN – to which small amounts of other elements are added to set device characteristics such as the threshold voltage. “At the same time, the requirements for the thickness of these materials, driven by gate dimensions for example, or the distance between the wires, are increasingly challenging.” Other examples of materials challenges are the use of two to three different types of insulators in the middle-of-the- line, each with different etch contrasts. “We use novel materials such as carbon containing oxides or oxynitrides that have lower dielectric constants in order to boost the performance of circuits,” he says, noting that the materials list “is quite long.”

Several critical dimensions in transistors at advanced technology nodes have already reached a few monolayers of atoms, fueling expectations for innovation at the material level for transistor scaling, Bu notes. “The other argument is that there is a growing gap between computing demand and the slowdown of technology advancement driven by conventional scaling,” says Bu. One trend that addresses this gap is integrating more computing functions that make the technology solution more modular, which naturally leads to the incorporation of more materials for more applications. Bu cautions, however, that intro- ducing new materials in semiconductor technology has never been easy. “It takes many years of R&D to reach this implementation point, if it ever happens. So, do we need new materials when the industry moves to 5nm and 3nm? Yes, though I expect new material implementation to be a lot faster in interconnect and packaging at these nodes rather than intrinsic to the transistor.”

Challenges in developing atomic-level processes

There will be challenges in developing atomic-level processes used in scaling, such as atomic layer depositions (ALD) and atomic layer etches, notes Verkest. “These classes of processes are both required to handle the scaled dimensions at the 5nm and 3nm nodes, and also the 3D nature of the scaled technologies – and here we are talking about logic and memories,” Verkest says. “With respect to depositions, we would need to develop thermal ALD processes (not plasma-based) that enable accurate and conformal depositions in non-line-of-sight structures.”

Adhesion and wetting, smoothness, and throughput would also need to be addressed. “Longer term, these processes need to facilitate selectivity and self-alignment to address gap-fill challenges in highly scaled structures,” he says. Other concerns he notes with respect to atomic layer etches are selectivity to various materials, and fidelity requirements that increase the requirements for metrology accuracy. “Throughput is also a concern.”

Bu believes that a new device architecture beyond FinFET is required to provide a full technology node scaling benefit (i.e., density, power and performance) at 5nm and 3nm.
“Beyond 3nm, we may need to continue the transistor scaling in the vertical direction and start to stack them together,” Bu says. He also cites the need for parasitic R/C reduction in the interconnect to take advantage of the intrinsic transistor benefit at the circuit and chip levels. “We see a lot of opportunity in atomic-level processes, especially in atomic layer etch and selective material deposition, to address these challenges in the transistor and the interconnect.”

By Pete Singer

Increasingly complicated 3D structures such finFETs and 3D NAND require very high aspect ratio etches. This, in turn, calls for higher gas flow rates to improve selectivity and profile control. Higher gas flow rates also mean higher etch rates, which help throughput, and  higher rates of removal for etch byproducts.

“Gas flow rates are now approaching the limit of the turbopump,” said Dawn Stephenson, Business Development Manager – Chamber Solutions at Edwards Vacuum. “No longer is it only the process pressure that’s defining the size of the turbopump, it’s now also about how much gas you can put through the turbopump.”

Turbopumps operate by spinning rotors at very high rates of speed (Figure 1). These rotors propel gases and process byproducts down and out of the pump. The rotors are magnetically levitated (maglev) to reduce friction and increase rotor speed.

Figure 1. Spinning rotors propel gases and process byproducts out of the pump.

The challenge starts with processes that have high gas flow rates, over a thousand sccm, and lower chamber pressures, below 100 mTorr.  Such processes include chamber clean steps where high flows of oxygen-containing gases are used to remove and flush the process byproducts from inside the chamber, through Silicon via (TSV) in which SF6is widely used at high gas flowrates for deep silicon reactive ion etch (RIE) and more recently, gaseous chemical oxide removal (COR) which typically uses HF and NH3to remove oxide hard masks.

However, the challenge is intensified with the more general trend to higher aspect ratio etch across all technologies.

Stephenson said the maximum amount of gas you can put through a maglev turbo is determined by two things: the motor power and the rotor temperature. Both of these are affected adversely by the molecular weight of the gas. “The heavier the molecule, the lower the limit. For motor power, if the gas flow rate is increased, the load on the rotor is increased, and then you need more power. Eventually you reach a gas flow at which you exceed the amount of power you have to keep the rotor spinning and it will slow down,” she said.

The rotor temperature is an even bigger limiting factor. “As gas flow rates increase, the number of molecules hitting the rotor are increased. The amount of energy transferred into the rotors is also increased which elevates the temperature of the rotor. Because the rotor is suspended in a vacuum and because it’s levitated, it’s not very easy to remove that heat from the rotor because its primary thermal transfer is through radiation,” she explained.

Pumping heavier gases, particularly ones that have poor thermal conductivity, cause the rotor temperature to rise, leading to what is known as “rotor creep.”Rotor creep is material growth due to high temperature and centrifugal force (stress).  Rotor creep deformation over time narrows clearances between rotor and stator and can eventually lead to contact and catastrophic failure (Figure 2).

Figure 2. Edwards pumps have the highest benchmark for rotor creep life temperature in the industry, due to the use of a premium aluminum alloy as the base material for its mag-lev rotors, combined with a low stress design.

Where it gets even worse are in applications where the turbopump is externally heated to reduce byproduct deposition inside the pump. Such a heated pump will have a higher baseline rotor temperature and significantly lower allowable gas flowrates than an unheated one. This becomes a challenge particularly for the heated turbopumps on semiconductor etch and flat panel display processes using typical reactant gases such as HBr and SF6.  “Those are very heavy gases with low thermal conductivity and the maximum limit of the turbopump is actually quite low,” Stephenson said.

The good news is that Edwards has been diligently working to overcome these challenges. “What we have done to maximize the amount of gas you can put into our turbopumps is to  ensure our rotors can withstand the highest possible temperature design limit for a 10 year creep lifetime.   We use a premium alloy for the base rotor material and then beyond that we have done a lot of work with our proprietary modeling techniques to design a very low stress rotor because the creep is due to two factors: the temperature and the centrifugal stress. Because of those two things combined, we’re able to achieve the highest benchmark for rotor creep life temperature in the industry,” she said.

Furthermore, the company has worked on thermal optimization of the turbopump platform. “That means putting in thermal isolation where needed to try to help keep the rotor and motor cool. At the same time, we also need to keep the gas path hot to stop byproducts from depositing. We have also released a high emissivity rotor coating that helps keep the rotor cool,” Stephenson said. A corrosion resistant, black ceramic rotor coating is used to maximize heat radiation, which helps keep the rotor cool and gives more headroom on gas flowrate before the creep life temperature is reached.

Edwards has also developed a unique real-time rotor temperature sensor: Direct, dynamic rotor temperature reporting eliminates over-conservative estimated max gas flow limits and allows pump operation at real maximum gas flow in real duty cycle while maintaining safety and lifetime reliability.

In summary, enabling higher flows at lower process pressures is becoming a critical capability for advanced Etch applications, and Edwards have addressed this need with several innovations, including optimized rotor design to minimize creep, high emissivity coating, and real time temperature monitoring.

By Dave Lammers

The semiconductor industry is collecting massive amounts of data from fab equipment and other sources. But is the trend toward using that data in a Smart Manufacturing or Industry 4.0 approach happening fast enough in what Mike Plisinski, CEO of Rudolph Technologies, calls a “very conservative” chip manufacturing sector?

“There are a lot of buzzwords being thrown around now, and much of it has existed for a long time with APC, FDC, and other existing capabilities. What was inhibiting the industry in the past was the ability to align this huge volume of data,” Plisinskisaid.

While the industry became successful at adding sensors to tools and collecting data, the ability to track that data and make use of it in predictive maintenance or other analytics thus far “has had minimal success,” he said. With fab processes and manufacturing supply chains getting more complex, customers are trying to figure out how to move beyond implementing statistical process control (SPC) on data streams.

What is the next step? Plisinski said now that individual processes are well understood, the next phase is data alignment across the fab’s systems. As control of leading-edge processes becomes more challenging, customers realize that the interactions between the process steps must be understood more deeply.

“Understanding these interactions requires aligning these digital threads and data streams. When a customer understands that when a chamber changes temperature by point one degrees Celsius, it impacts the critical dimensions of the lithography process by X, Y, and Z. Understanding those interactions has been a significant challenge and is an area that we have focused on from a variety of angles over the last five years,” Plisinski said.

Rudolph engineers have worked to integrate multiple data threads (see Figure), aligning various forms of data into one database for analysis by Rudolph’s Yield Management System (YMS). “For a number of years we’ve been able to align data. The limitation was in the database: the data storage, the speed of retrieval and analysis were limitations. Recently new types of databases have come out, so that instead of relational, columnar-type databases, the new databases have been perfect for factory data analysis, for streaming data. That’s been a huge enabler for the industry,” he said.

Rudolph engineers have worked to integrate multiple data threads into one database.

Leveraging AI’s capabilities

A decade ago, Rudolph launched an early neural-network based system designed to help customers optimize yields. The software analyzed data from across a fab to learn from variations in the data.

“The problem back then was that neural networks of this kind used non-linear math that was too new for our conservative industry, an industry accustomed to first principle analytics. As artificial intelligence has been used in other industries, AI is becoming more accepted worldwide, and our industry is also looking at ways to leverage some of the capabilities of artificial intelligence,” he said.

Collecting and making use of data with a fab is “no small feat,” Plisinskisaid, but that leads to sharing and aligning data across the value chain: the wafer fab, packaging and assembly, and others.

“To gain increased insights from the data streams or digital threads, to bring these threads all together and make sense of all of it. It is what I call weaving a fabric of knowledge: taking individual data threads, bringing them together, and weaving a much clearer picture of what’s going on.”

Security concerns run deep

One of the biggest challenges is how to securely transfer data between the different factories that make up the supply chain. “Even if they are owned by one entity, transferring that large volume of data, even if it’s over a private dedicated network, is a big challenge. If you start to pick and choose to summarize the data, you are losing some of the benefit. Finding that balance is important.”

The semiconductor industry is gaining insights from companies analyzing, for instance, streaming video. The network infrastructures, compression algorithms, transfers of information from mobile wireless devices, and other technologies are making it easier to connect semiconductor fabs.

“Security is perhaps the biggest challenge. It’s a mental challenge as much as a technical one, and by that I mean there is more than reluctance, there’s a fundamental disdain for letting the data out of a factory, for even letting data into the factory,” he said.

Within fabs, there is a tug of war between equipment vendors which want to own the data and provide value-add services, and customers who argue that since they own the tools they own the data. The contentious debate grows more intense when vendors talk about taking data out of the fab. “That’s one of the challenges that the industry has to work on — the concerns around security and competitive information getting leaked out.” Developing a front-end process is “a multibillion dollar bet, and if that data leaks out it can be devastating to market-share leadership,” Plisinski said.

Early adopter stories

The challenge facing Rudolph and other companies is to convince their customers of the value of sharing data; that “the benefits will outweigh their concerns. Thus far, the proof of the benefit has been somewhat limited.”

“At least from a Rudolph perspective, we’ve had some early adopters that have seen some significant benefits. And I think as those stories get out there and as we start to highlight what some of these early adopters have seen, others at the executive level in these companies will start to question their teams about some of their assumptions and concerns. Eventually I think we’ll find a way forward. But right now that’s a significant challenge,”Plisinski said.

It is a classic chicken-and-egg problem, making it harder to get beyond theories to case-study benefits. “What helped us is that some of the early adopters had complete control of their entire value chain. They were fully integrated. And so we were able to get over the concerns about data sharing and focus on the technical challenges of transferring all that data and centralizing it in one place for analytical purposes. From there we got to see the benefits and document them in a way that we could share with others, while protecting IP.”

Aggregating data, buying databases and analytical software, building algorithms – all cost money, in most cases adding up to millions of dollars. But if yields improve by .25 or half a percent, the payback comes in six to eight months, he said.

“It’s a very conservative industry, an applied science type of industry. Trying to prove the value of software — a kind of black magic exercise — has always been difficult. But as the industry’s problems have become so complex, it is requiring these sophisticated software solutions.”

“We will have examples of successful case studies in our booth during SEMICON West. Anyone wanting further information is invited to stop by and talk to our experts,” adds Plisinski.

SEMI today announced the re-election of 10 current members to the SEMI International Board of Directors in accordance with the association’s by-laws.

The 10 board members were re-elected for two-year terms:

  • Martin Anstice, CEO, Lam Research Corporation
  • Kevin Crofton, president, SPTS Technologies, and corp. V.P., Orbotech
  • Jon D. Kemp, vice president, DuPont
  • Mitsunobu Koshiba, president and representative director, JSR Corporation
  • Yong Han Lee, chairman, Wonik
  • Sue Lin, vice chairman, Hermes Epitek
  • Tadahiro Suhara, president, SCREEN Semiconductor Solutions Co., Ltd.
  • Tetsuo Tsuneishi, executive chairman of the board and representative director, TEL
  • Tien Wu, management director and chief operating officer, ASE Group
  • Guoming Zhang, senior V.P. and chief strategy officer, NAURA Technology Group Co., Ltd.

The SEMI Executive Committee confirmed Tetsuo Tsuneishi, chairman of the board of TEL, as chairman of the SEMI Executive Committee. SEMI also confirmed Bertrand Loy, president and CEO of Entegris, as vice-chairman.

The leadership appointments and the elected board members’ tenure become effective at the annual SEMI membership meeting on July 11, during SEMICON West 2018 in San Francisco, California.

“The SEMI Board of Directors is comprised of global business leaders who represent SEMI members and the industry, ensuring that SEMI develops and delivers member value in all regions,” said SEMI president and CEO Ajit Manocha. “We congratulate the re-elected members and greatly appreciate all of our board members’ contributions to the industry.”

SEMI’s 19 voting directors and 11 emeritus directors represent companies from Europe, China, Japan, Korea, North America, and Taiwan, reflecting the global scope of the association’s activities. SEMI directors are elected by the general membership as voting members of the board and can serve a total of five two-year terms.

BY PETE SINGER, Editor-in-Chief

Increasingly, the ability to stay on the path defined my Moore’s Law will depend on advanced packaging and heterogeneous integration, including photonics integration.

At The ConFab in May, Bill Bottoms, chair of the integrated photonics technical working group, and co-chair of the heterogeneous integration roadmap (HIR) spoke about the changing nature of the industry and specifically the needs of photonic integration.

Bottoms said the driving force behind photonics integration is pretty straightforward: “The technology we have today can’t keep up with the expanding generation of transport and storage of data,” he said. But doing so will be a challenge.

The integration of photonics, electronics and plasmonics at a system level is necessary.

“These require heteroge- neous integration by architecture, by device type, by materials and by manufacturing processes,” Bottoms said. “We’re changing the way we’re doing things.”
These kinds of changes are best thought of not as packaging but system level integration. “As we move the photons as close as to the transistors as possible, we’re going to be faced with integrating everything on a simple substrate,” he said.

There are a large number of devices that involve photons which share the common requirement of providing a photon path either into or out of the package or both. They include: Light emitting diodes (LEDs), laser diodes, plasmonic photon emitters, photonic Integrated circuits (PICs), MEMS optical switching devices, camera modules, optical modulators, active optical cables, E to O and O to E converters, optical sensors (photo diodes and other types), and WDM multiplexers and de‐multi- plexers. Many of these devices have unique thermal, electrical and mechanical characteristics that will require specialized materials and system integration (packaging) processes and equipment, Bottoms noted.

Of the biggest challenges might be thermal management: “We have things that make a lot of heat and things that can’t have their temperature change by more than a degree without losing their functionality,” Bottoms said.

The scope of the HIR Photonics Chapter includes defining difficult challenges and, where possible, potential solutions associated with: data systems and the global network, photonic components, integrating these components and subsystems into systems with the smallest size, lowest weight, smallest volume, lowest power and highest performance.

It will also address supply chain requirements, which may turn out to be the biggest challenge. “We will not beat the challenge of cost pressures unless we develop the supply chain that can justify high volume. It’s the only way we know how to bring down costs,” Bottoms said. Sounds like a great opportunity for today’s equipment and materials suppliers to me!

BY GRIGORI BOKERIA, MATTHIAS FRAHM, SASCHA RAHMAN, and XI BING ANG, Simon-Kucher

The semiconductor industry is facing key challenges. In recent years, M&A mega deals have led to consolidations within the market, while the industry continues to mature. This leaves rather moderate growth prospects for the next three years. Semiconductor companies will have to consistently farm limited organic growth sources whilst at the same time tapping into new and growing macrotrends. To be successful in the long term, they must recognize the potential of the disruptive technologies and new markets that the Internet of Things will bring.

How can companies relive the previous successes in the mobile consumer segment?

In the 1990s and even early 2000s, growth booms in the industry with annual sales growth of 30 to 40 percent were the norm. Thanks to the sharply increasing demand in the consumer market for PCs, laptops and mobile phones, many smaller technology companies were able to grow into giants in the semiconductor business (FIGURE 1). However, since 2011, the industry has had to manage its growth expectations for the consumer market. With an average annual growth rate of 3.4 percent expected from 2015 to 2020, the strong growth period seems to be over and the dynamic start-up atmosphere of the past appears to be more or less history. The entire industry already has a market size of over 350 billion euros, with intense rigid competition among existing players. M&A mega deals (FIGURE 2) such as Qualcomm-NXP, Avago-Broadcom, Softbank-ARM and Western Digital-SanDisk have severely consolidated the market and now these companies are deep in operations integration and rationalization mode.

Is this the end of the period of constant growth outperformance? Not at all. Simon-Kucher project experience tells us that even organic growth sources based on dynamic market trends can be tapped, meaning companies can relive the successes in the mobile consumer sector. However, two fundamental strategic questions need to be answered: Where will these new growth waves come from?

And how can the imminent stagnation be avoided? We have identified three sources of organic growth that will play a pivotal role in the future of the semiconductor industry.

1.Exploit new disruptive technologies such as silicon carbide

Semiconductors based on silicon carbide (SiC) represent a strong area for future growth. Compared to semiconductors made of regular silicon, SiC-based semiconductors can operate at much higher frequency and temperature and convert electric power at lower losses, promising increased speed, robustness and efficiency. SiC devices are capable of managing the same power level as Si devices at half the size, boosting power density and reliability.

While a handful of players have already secured a favorable starting position in the market, there continues to be strong medium-term growth forecasts which means that the current market volume in this emerging product segment (~$200 million) still offers attractive entry potential for second and third movers. Several suppliers such as Dow Corning and Nippon Steel have entered and increased activity in the SiC market while companies such as Wolfspeed/Cree are experiencing decline in market share. This goes to show that there is still room to wrangle for territory.

We anticipate that hype will become mass reality within the next five to eight years, particularly driven by the growing demand in hybrid and electric mobility, regener- ative power generation and industrial applications. Notably, SiC may have a huge impact on the automotive industry, in particular on electric vehicles and e-mobility due to the high efficiency levels. In each of these markets, customers continue to demand and expect smaller wafers and devices with increasingly better performance profiles than Si-based devices, made possible by SiC technology. According to a recent Simon-Kucher study, global demand in the SiC technology segment and its sister technology gallium nitride (GaN) will amount to more than three billion euros by 2025, with double-digit annual growth rates. Industry analysts note that SiC has gradually emerged as “mainstream” material since 2016 which will result in drop in prices for devices from 2018 onwards. This would translate to possibly large increases in volume demand.

At the moment, the technology is still relatively cost-intensive and more complex in production primarily due to lack of scale. As such, SiC and GaN remain niche markets for now. However, having achieved first significant design-wins, first-moving companies are proof of the future market potential. The remaining semiconductor companies need to adapt their innovation strategies or risk trailing the pack. To successfully implement SiC and GaN system solutions, it is essential to closely orient new product development towards emerging market needs, starting from initial development phases.

Here, semiconductor companies have to identify the appli- cations where customers already demand high switching voltage and speed, low switching losses, and a small size and weight. Only in doing so can they expect customer- oriented market success from design-in to design-win.

2. Anticipate and seize new markets materializing from the Internet of Things

The Internet of Things (IoT) has now become the catch-all phrase that encapsulates an enormous spectrum of potential applications and markets revolving around interconnected physical devices and appliances. As it continues to evolve and numerous markets around it become commercially viable, semiconductor companies have a huge opportunity to capture the underlying profit pools. By some accounts, something like 3 billion new IoT-enabled devices are manufactured per year; at the most rudimentary level, each of these devices require microcontrollers, sensors, actuators and a whole host of other semiconductor-enabled parts. Another indirect area of growth for semiconductor companies will likely emerge from the fact that the exponentially increasing amount of data generated by IoT products need to be processed and stored. This will lead to demand for more server farms and greater storage capacities.

IoT products and applications would not be possible without the continued advancements in semiconductor technology, and the demand for inexpensive chips that can be mass- produced will only continue to increase. Rather than spectating and reacting to this market macrotrend from the sidelines, semiconductor companies should see the IoT as an integral part of the future market’s DNA.

The current challenge is the fragmented nature of the market, with no clear “killer application” or common platform; rather, there is a multitude of smaller niche opportunities that in its entirety promise overall attractive growth potential. No player has yet been able to establish a market-dominant position in this highly diversified market. There are, however, specific end-markets that have taken the lead (for now) in terms of showing promise of growth, such as smart home applications, consumer wearables (e.g. fitness bracelets, smart watches), medical electronics, and connected cars (FIGURE 3). The IoT will turn these individual niche segments into potential game-changers for the semiconductor industry.

Amid these fast-evolving segments, critical for the success of semiconductor companies is their agility in swiftly responding to emerging trends and integrating hardware and software components along the value chain and ultimately, offering a seamless IoT solution. Semiconductor companies already focusing on seamless security, communication intel- ligence and user-friendliness are a step ahead in strength- ening their position. To not be left behind, semiconductor companies need to make the strategic decision of prioritising resources and investments into IoT-related growth sources and resist the inertia and temptation to solely rely on existing “bread and butter” revenue streams, regardless of how healthy the current margins are. Related to this, to get serious about this emerging opportunity, semiconductor companies should not view the IoT markets as a nebulous concept with opportunistic revenue streams, but rather conduct in-depth analyses of their current position within the changing value chains and competitive landscape to formulate concrete go-to-market plans.

3. Shift from component-centric sales to supplying system solutions

Finally, a third dimension of growth beyond new products and new markets for semiconductor companies is to move up the value chain. Increasingly, leading market players are integrating chips, drivers, software and sensors to offer partial system solutions, with the ultimate objective of being ecosystem enablers. Naturally, this requires the capability to not only sell hardware (semiconductors, wafers, etc.) but an entire system and services around it that several entities from different industries can utilise to establish their own IoT products. However, for companies traditionally built around selling components, doing this successfully is not a straightforward undertaking. Many sales forces are finding themselves lacking the organizational setup and solution-selling approach critical for success. In addition, in order to integrate products in the portfolio into systems solutions, companies have to establish effective cross-industry channel management on the sales front and at the same time develop strong alliances with partners along the value chain to ensure a stable ecosystem. Successful players will be those in the market with the capability to provide modular solutions that can readily interlink products with security, software and system consulting services.

As a result, we believe that the desire of companies to move towards being system suppliers and ecosystem enablers will further increase M&A activity due to the need to acquire specialised knowledge. Notably, Intel has acquired three companies within the space of a year from different parts of the industry to assimilate specific expertise related to IoT i.e. Altera (designer and manufacturer of program- mable logic devices), Nervana Systems (artificial intelligence software developer) and Itseez (specialist in computer vision technology and algorithms).

In summary, despite some notions otherwise, we are bullish about the imminent growth potential in the semiconductor market driven by very powerful macrotrends in product technology, emerging applications and also value chain shifts. Semiconductor companies thirsty for new waves of exponential growth would do well to heed the signposts from these trends and re-orient their product development, industry alliances and sales approaches rapidly in order to capitalise on these opportunities before the winner takes all.

Grigori Bokeria is a Partner in Simon-Kucher’s Cologne office, where Sascha Rahman is a Director; Matthias Frahm is a Senior Director in the Bonn office and Xi Bing Ang is a Director based in the London office. All four authors work within Simon-Kucher’s Global Technology & Industrial practice.

The development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

BY KIM YESS, Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Fan-out (FO) packaging is one of the most talked- about advanced packaging solutions for heterogeneous integration. Although it has been available for nearly a decade for the chips used in mobile devices, its popularity has spiked in the past two years, thanks to Apple’s adoption of TSMC’s integrated fan-out package-on-package (InFO PoP) for its A10 and A11 processors, and the Apple Watch. As a result, FO has quickly progressed to the mainstream, with outsourced semiconductor and test service providers (OSATs), foundries and integrated device manufacturers (IDMs) vying for market share.

What’s driving FO innovation?

According to Yole Développement, smartphone appli- cation processors are the main beneficiaries of high- density fan-out (HDFO)’s excellent performance and thin profile. As a result, as shown in FIGURE 1, the HDFO market was worth $500 million in 2017 and was predicted to exceed $1 billion if other players, namely Qualcomm, Samsung and Huawei switch to HDFO [1].

Jan Vardaman, TechSearch International, said Apple selected InFO PoP for its A10 processor because of power noise reduction and signal integrity improvement, in addition to being thin enough to enable a low-profile PoP solution as small as 15 x 15 mm.

In addition to HDFO, the market is growing for conventional FO, driven by new applications such as audio CODECs, power management ICs, radar modules and RF[2].

The automotive electronics market—particularly advanced driver assistance systems (ADAS) and autonomous vehicles—is also being explored as a viable application for FO because of the flexibility and fast time to market it provides, as well as the ability to adapt to new sensor system protocols.

Exploring new processes

In this race to provide the most reliable, highest-density solution, many manufacturing approaches have emerged. FO is not only becoming more versatile, it is also reaching high enough densities to offer a cost-effective alternative to 2.5D interposers. As the demand for FO increases, packaging processes are being explored in both the wafer and panel formats. This is driving a need for new and better-performing materials that address more stringent specifications to meet, for example, finer line and space requirements, as well as the improved elongation needed for advanced high-density FO.

Thanks to recent innovations in packaging materials, three new process approaches have been developed to bridge these gaps. One approach involves new carrier- assist release-layer materials for creation of the redistribution layer (RDL)-first/chip-last buildup processes. Another important development is an alternative to lithography dielectric patterning that uses laser-ablated dielectric materials. Lastly, an alternative to the molding process in the chip-first approach that uses a laminated die stencil and gap-fill materials is under development.

Carrier-assist release layer for chip-last FO

Low-density FO is built using a chip-first approach, which involves first placing the chips on a substrate wafer followed by over-mold to create a reconstituted wafer, with subsequent RDL and solder-ball placement. On the other hand, HDFO processes like TSMC’s InFO technology use a chip-last approach. Also known as RDL-first, this approach (with target features of ≤2 μm l/s) begins with a layer-by-layer buildup of the RDL on a carrier wafer, followed by die placement and over-mold.

Currently, manufacturers turn to permanent bonding, followed by backgrinding to remove the carrier wafer. This is because conventional temporary bond/debond materials cannot withstand the downstream RDL processes that subject the build-up layers to high temperatures and vacuum conditions, as well as harsh chemical environments. However, backgrinding is a destructive process, creating debris that can cause damage to the device itself.

The new approach uses neither a temporary nor a permanent bonding process. Instead, it utilizes a release layer on the carrier substrate to allow separation of the FO wafer from the carrier at the end of the process flow.

The challenge with this new method is designing a material that withstands high- temperature process steps as well as strong mechanical stresses without delaminating or distorting the reconstituted wafer. Additionally, the material must be adaptable to the new FO panel-level processes (FOPLP) along with existing round wafers, as the industry innovates in that direction.

Manufacturers are investigating the use of copper foil lamination, as an alternative to physical vapor deposition of the seed layer. The copper laminating process requires a material that is flexible enough to sufficiently laminate layers on top of the substrate, and that can be cured using UV radiation or heat to yield a structurally stable base that meets the thermomechanical and chemical resis- tance requirements of the build-up process.

Additionally, it must be releasable by ultraviolet(UV) laser ablation or other UV exposure. To meet these needs, a new class of so-called “triangle” polymeric materials has been conceived that have advantages over standard-application release layers because they are multi functional. Specifically, these “triangle” materials can be laminated, cured and debonded, adding flexibility to the carrier-assisted process (FIGURE 2).

Dielectric RDL patterning

Traditional RDL patterning uses a complicated, 24-step photolithography process that employs photosensitive dielectric materials and masks to create trace patterns, followed by Cu plating to route the signal from the chip out of the package to the solder balls. This process, developed with round wafers in mind, uses spin-coated dielectrics. Unfortunately, these lithography processes are too costly to utilize in innovative package designs that must meet the stringent requirements for most markets [3].

As the industry moves to HDFO and begins to investigate panel-level processes to reduce cost and improve yield, alternative patterning approaches are being developed that can achieve resolutions down to 5 μm with an ultimate goal of 2 μm l/s. Laser ablation is one alter- native to photolithography for creating finer-featured RDL patterns while achieving all these goals.

The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet processing. In addition, with excimer laser patterning technology, the industry gains a much wider choice of dielectric materials (photopatternable and non-photopatternable) to help achieve further reductions in manufacturing costs as well as enhancements in chip or package performance [4].

By using excimer laser ablation, many process steps and costly materials can be eliminated from the manufacturing flow, including resist coating, baking, developing and resist stripping and etching using harsh chemicals [5].

FIGURE 3 demonstrates the considerable cost savings of laser ablation over photolithography. Activity-based cost modeling was used to carry out the cost comparison between the two processes. With activity-based cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is calculated. The cost of each activity is determined by analyzing the following attributes: time, amount of labor and cost of material required (consumable and permanent), tooling cost, all capital costs, and yield loss associated with the activity.

Laser-ablated patterning is a room-temperature process that works by using a dielectric material to build up RDL fixtures, and excimer and solid-state lasers to ablate the material and direct-write a pattern. Laser ablation allows for depth and side-wall angle control, making it possible to create feature sizes <5 μm. It also reduces chemical waste streams. Additionally, fewer steps, fast removal rates and high throughput lead to a lower-cost solution in comparison with traditional photolithography (Fig. 3).

Photosensitive dielectric materials often fall short of meeting the required mechanical and thermal properties, and therefore need a variety of process “work-arounds” that add to the cost of ownership. Alter- natively, non-photopatternable dielectric materials can be designed using a vast selection of chemical platforms, which improves the possibility of meeting the thermal and mechanical property requirements.

As with all new approaches, laser ablation is not without some challenges. Post-laser-ablation cleaning and debris removal, along with surface roughness as a result of the ablation step, need to be addressed. Additionally, the laser system needs to achieve a high ablation rate for high throughput. While the process costs of laser ablation are lower than photolithography, there is still a significant equipment capacity investment required to add laser tools to the manufacturing line. This may delay overcoming the most critical challenge: convincing the industry to embrace laser ablation patterning over conventional approaches.

Development of the dielectric material is ongoing to further push the resolution of laser-ablated materials. In addition to spin and spray coating, other deposition methods being investigated include slot-die coating, ink-jet printing, Vermeer coating, spray coating and laminate film.

Laminated polymeric die-stencil fill concept

Chip-first is the standard approach for conventional FO packages, including embedded wafer level ball grid arrays (eWLBs), redistributed chip packages (RCPs), M-Series and others. It calls for placing die into the mold compound before the RDL processing steps. One of the challenges of this approach that impacts final yield is the die shift that can occur during the RDL processes. Additionally, in multi-die FOWLP configurations that combine disparate technologies to essen- tially form a system-in-package (SiP), the dies may be of different sizes and heights. Additionally, the mismatch in coefficient of thermal expansion (CTE) between all of the materials involved leads to severe warpage of the reconstituted wafer.

A new carrier-based approach developed to combat this problem replaces the over-mold structure around the dies with a laminated die stencil (FIGURE 4). A release layer is first applied to a carrier, followed by a curable adhesive backing layer. Next, the die stencil film is laminated to the curable adhesive backing layer. The dies are then placed in the stencil openings and attached to the adhesive backing layer during thermal curing. The gaps between the dies and stencil are then filled with a flexible yet curable polymeric material, yielding a stable reconstituted substrate. This is followed by construction of the RDLs while still supported on the carrier. Finally, the reconsti- tuted substrate is released from the carrier.

The stencil can be fabricated as a sheet from a variety of high-temperature-stable thermoplastics including, for example, carbon-fiber-filled polyetheretherketone (PEEK), which has an in-plane CTE of <10 ppm/K.

The pre-formed cavities can be configured for different die sizes and types to fabricate SiP components. The curable adhesive backing layer is comparatively soft and tacky before it is cured. This property allows the die-stencil film to be laminated to the structure at low temperatures.

This process not only addresses the die shift issue that plagues the chip-first approach, it also enables varying levels of die thickness. When placed in the stencil, the polymeric material allows the dies to sink and adjusts itself within the stencil. Once the dies are set, the material is cured, which locks them in place. Additionally, the process offers high-temperature stability, better CTE matching for warpage control, and high throughput.

Summary and conclusion

Fan-out packaging is on track to be a game-changing advanced packaging technology that will enable heterogeneous integration architectures. Applications have already expanded beyond smartphones, with HDFO targeting emerging applications.

Substrate handling and RDL strategies will be increasingly important, if not critical, for both conventional and HDFO technologies. To this end, the development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

The gamut of application needs for wafer support includes simple thinning processes during the backside processing of ultrathin, 300-mm silicon wafers, as well as reconstituted substrates for RDL fabrication. In addition to new materials, novel manufacturing approaches are also needed to further optimize the FO process flow.

KIM YESS is Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Acknowledgements

The author would like to thank Amy Lujan, SavanSys, for her contribution to this article regarding activity- based cost modeling.

References

1. Yole Developpement, “Fan-out Packaging Confirms its Success Story,” 3D InCites, September 14, 2017.
2. P. Garrou, “ITLE 356 SEMI Taiwan Part 1: Fan-out Packaging Players, Applications, and Market Growth,” Solid State Technology, October 2017.
3. H.Hichri,M.Arendt,andM.Gingerella,“Novel Process of RDL Formation for Advanced Packaging by Excimer Laser Ablation,” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1733-1739. doi: 10.1109/ECTC.2016.225
4. H. Hichri, Ibid.
5. R. Zoberbier, M. Souter, “Laser Ablation, Emerging Patterning Technology for Advanced Packaging,” SUSS MicroTec Lithography GmbH, January 2010

Market shares of semiconductor equipment manufacturers shifted significantly in Q1 2018 as Applied Materials, the top supplier dropped, according to the report “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, a New Tripoli-based market research company.

The chart below shows shares for the first quarter (Q1) of calendar year 2017 and 2018. Market shares are for equipment only, excluding service and spare parts, and have been converted for revenues of foreign companies to U.S. dollars on a quarterly exchange rate.

Applied Materials lost significant market share YoY, from 18.4% of the $13.1 billion Q1 2017 market to 17.7% of the $17.0 billion Q1 2018 market. This drop follows a 1.8 share-point loss by Applied Materials for CY 2017 compared to 2016. The company competes with Lam Research and TEL in the deposition and etch market, and both gained share at the expense of Applied Materials.

At the other end of the spectrum, smaller semiconductor companies making up the “other” category lost 2.4 share points as a whole.

Much of the equipment revenue growth was attributed to strong growth in the DRAM and NAND sectors, as equipment was installed in memory manufacturers Intel, Micron Technology, Samsung Electronics, SK Hynix, Toshiba, and Western Digital. The memory sector, which grew grown 61.5% in 2017, is forecast to add another 28.5% in 2018 according to industry consortium WSTS (World Semiconductor Trade Statistics).

TEL recorded growth of 120.3% YoY in Korea, much of it on NAND and DRAM sales to Samsung Electronics and SK Hynix, and 69.5% YoY in Japan, much of it on NAND sales to Toshiba at its Fab 6 in Kitakami, Japan. Lam Research gained 42.2% and 70.5% YoY, respectively, in Korea and Japan.

Following the strong growth in the semiconductor equipment market, The Information Network projects another 11.5% growth in 2018 for semiconductor equipment.

Smart technologies take center stage tomorrow as SEMICON West, the flagship U.S. event for connecting the electronics manufacturing supply chain, opens for three days of insights into leading technologies and applications that will power future industry expansion. Building on this year’s record-breaking industry growth, SEMICON West – July 10-12, 2018, at the Moscone Center in San Francisco – spotlights how cognitive learning technologies and other disruptors will transform industries and lives.

Themed BEYOND SMART and presented by SEMI, SEMICON West 2018 features top technologists and industry leaders highlighting the significance of artificial intelligence (AI) and the latest technologies and trends in smart transportation, smart manufacturing, smart medtech, smart data, big data, blockchain and the Internet of Things (IoT).

Seven keynotes and more than 250 subject matter experts will offer insights into critical opportunities and issues across the global microelectronics supply chain. The event also features new Smart Pavilions to showcase interactive technologies for immersive, virtual experiences.

Smart transportation and smart manufacturing pavilions: Applying AI to accelerate capabilities

Automotive leads all new applications in semiconductor growth and is a major demand driver for technologies inrelated segments such as MEMS and sensors. The SEMICON West Smart Transportation and Smart Manufacturing pavilions showcase AI breakthroughs that are enabling more intelligent transportation performance and manufacturing processes, increasing yields and profits, and spurring innovation across the industry.

Smart workforce pavilion: Connecting next-generation talent with the microelectronics industry

SEMICON West also tackles the vital industry issue of how to attract new talent with the skills to deliver future innovations. Reliant on a highly skilled workforce, the industry today faces thousands of job openings, fierce competition for workers and the need to strengthen its talent pipeline. Educational and engaging, the Smart Workforce Pavilion connects the microelectronics industry with college students and entry-level professionals.

In the Workforce Pavilion “Meet the Experts” Theater, recruiters from top companies are available for on-the-spot interviews, while career coaches offer mentoring, tips on cover letter and resume writing, job-search guidance, and more. SEMI will also host High Tech U (HTU) in conjunction with the SEMICON West Smart Workforce Pavilion. The highly interactive program supported by Advantest, Edwards, KLA-Tencor and TEL exposes high school students to STEM education pathways and useful insights about careers in the industry.

Releasing its Mid-Year Forecast at the annual SEMICON West exposition, SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase 10.8 percent to $62.7 billion in 2018, exceeding the historic high of $56.6 billion set last year. Another record-breaking year for the equipment market is expected in 2019, with 7.7 percent forecast growth to $67.6 billion.

The SEMI Mid-Year Forecast predicts wafer processing equipment will rise 11.7 percent in 2018 to $50.8 billion. The other front-end segment, consisting of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to jump 12.3 percent to $2.8 billion this year. The assembly and packaging equipment segment is projected to grow 8.0 percent to $4.2 billion in 2018, while semiconductor test equipment is forecast to increase 3.5 percent to $4.9 billion this year.

In 2018, South Korea will remain the largest equipment market for the second year in a row. China will rise in the rankings to claim the second spot for the first time, dislodging Taiwan, which will fall to the third position. All regions tracked except Taiwan will experience growth. China will lead in growth with 43.5 percent, followed by Rest of World (primarily Southeast Asia) at 19.3 percent, Japan at 32.1 percent, Europe at 11.6 percent, North America at 3.8 percent and South Korea at 0.1 percent.

SEMI forecasts that, in 2019, equipment sales in China will surge 46.6 percent to $17.3 billion. In 2019, China, South Korea, and Taiwan are forecast to remain the top three markets, with China rising to the top. South Korea is forecast to become the second largest market at $16.3 billion, while Taiwan is expected to reach $12.3 billion in equipment sales.

The following results are in terms of market size in billions of U.S. dollars:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Mid-year Forecast, which provides an outlook for the semiconductor equipment market. For more information or to subscribe, please contact SEMI customer service at 1.877.746.7788 (toll free in the U.S.). For more information online, visit: http://info.semi.org/semi-equipment-market-data-subscription