Category Archives: Wafer Processing

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $38.7 billion for the month of May 2018, an increase of 21.0 percent compared to the May 2017 total of $32.0 billion. Global sales in May were 3 percent higher than the April 2018 total of $37.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has posted consistent growth of greater than 20 percent for 14 consecutive months, and May 2018 marked the industry’s highest-ever monthly sales,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas led the way once again, with sales increasing by more than 30 percent compared to last year, and sales were up across all major semiconductor product categories on both a year-to-year and month-to-month basis.”

Year-to-year sales increased solidly across all regions: the Americas (31.6 percent), China (28.5 percent), Europe (18.7 percent), Japan (14.7 percent), and Asia Pacific/All Other (8.7 percent). Month-to-month sales increased more modestly across all regions: China (6.3 percent), Japan (2.6 percent), Asia Pacific/All Other (1.2 percent), the Americas (1.1 percent), and Europe (1.0 percent).

If your laptop or cell phone starts to feel warm after playing hours of video games or running too many apps at one time, those devices are actually doing their job.

Whisking heat away from the circuitry in a computer’s innards to the outside environment is critical: Overheated computer chips can make programs run slower or freeze, shut the device down altogether or cause permanent damage.

As consumers demand smaller, faster and more powerful electronic devices that draw more current and generate more heat, the issue of heat management is reaching a bottleneck. With current technology, there’s a limit to the amount of heat that can be dissipated from the inside out.

Researchers at the University of Texas at Dallas and their collaborators at the University of Illinois at Urbana-Champaign and the University of Houston have created a potential solution, described in a study published online July 5 in the journal Science.

Researchers at the University of Texas at Dallas and their collaborators have created and characterized tiny crystals of boron arsenide, like the one shown here imaged with an electron microscope, that have high thermal conductivity. Because the semiconducting material efficiently transports heat, it might be used in future electronics to help keep smaller, more powerful devices from overheating. The research is described in a study published online July 5, 2018 in the journal Science. Credit: University of Texas at Dallas

Bing Lv (pronounced “love”), assistant professor of physics in the School of Natural Sciences and Mathematics at UT Dallas, and his colleagues produced crystals of a semiconducting material called boron arsenide that have an extremely high thermal conductivity, a property that describes a material’s ability to transport heat.

“Heat management is very important for industries that rely on computer chips and transistors,” said Lv, a corresponding author of the study. “For high-powered, small electronics, we cannot use metal to dissipate heat because metal can cause a short circuit. We cannot apply cooling fans because those take up space. What we need is an inexpensive semiconductor that also disperses a lot of heat.”

Most of today’s computer chips are made of the element silicon, a crystalline semiconducting material that does an adequate job of dissipating heat. But silicon, in combination with other cooling technology incorporated into devices, can handle only so much.

Diamond has the highest known thermal conductivity, around 2,200 watts per meter-kelvin, compared to about 150 watts per meter-kelvin for silicon. Although diamond has been incorporated occasionally in demanding heat-dissipation applications, the cost of natural diamonds and structural defects in manmade diamond films make the material impractical for widespread use in electronics, Lv said.

In 2013, researchers at Boston College and the Naval Research Laboratory published research that predicted boron arsenide could potentially perform as well as diamond as a heat spreader. In 2015, Lv and his colleagues at the University of Houston successfully produced such boron arsenide crystals, but the material had a fairly low thermal conductivity, around 200 watts per meter-kelvin.

Since then, Lv’s work at UT Dallas has focused on optimizing the crystal-growing process to boost the material’s performance.

“We have been working on this research for the last three years, and now have gotten the thermal conductivity up to about 1,000 watts per meter-kelvin, which is second only to diamond in bulk materials,” Lv said.

Lv worked with postdoctoral research associate Sheng Li, co-lead author of the study, and physics doctoral student Xiaoyuan Liu, also a study author, to create the high thermal conductivity crystals at UT Dallas using a technique called chemical vapor transport. The raw materials — the elements boron and arsenic — are placed in a chamber that is hot on one end and cold on the other. Inside the chamber, another chemical transports the boron and arsenic from the hot end to the cooler end, where the elements combine to form crystals.

“To jump from our previous results of 200 watts per meter-kelvin up to 1,000 watts per meter-kelvin, we needed to adjust many parameters, including the raw materials we started with, the temperature and pressure of the chamber, even the type of tubing we used and how we cleaned the equipment,” Lv said.

David Cahill and Pinshane Huang’s research groups at the University of Illinois at Urbana-Champaign played a key role in the current work, studying defects in the boron arsenide crystals by state-of-the-art electron microscopy and measuring the thermal conductivity of the very small crystals produced at UT Dallas.

“We measure the thermal conductivity using a method developed at Illinois over the past dozen years called ‘time-domain thermoreflectance’ or TDTR,” said Cahill, professor and head of the Department of Materials Science and Engineering and a corresponding author of the study. “TDTR enables us to measure the thermal conductivity of almost any material over a wide range of conditions and was essential for the success of this work.”

The way heat is dissipated in boron arsenide and other crystals is linked to the vibrations of the material. As the crystal vibrates, the motion creates packets of energy called phonons, which can be thought of as quasiparticles carrying heat. Lv said the unique features of boron arsenide crystals — including the mass difference between the boron and arsenic atoms — contribute to the ability of the phonons to travel more efficiently away from the crystals.

“I think boron arsenide has great potential for the future of electronics,” Lv said. “Its semiconducting properties are very comparable to silicon, which is why it would be ideal to incorporate boron arsenide into semiconducting devices.”

Lv said that while the element arsenic by itself can be toxic to humans, once it is incorporated into a compound like boron arsenide, the material becomes very stable and nontoxic.

The next step in the work will include trying other processes to improve the growth and properties of this material for large scale applications, Lv said.

SEMICON West next week will host a White House-led discussion of the anticipated national leadership strategy for semiconductors, a multi-agency initiative led by top U.S. government national security and economic organizations.

On Wednesday, July 11, a panel of U.S. officials representing agencies involved in leading the strategy will address federal research and development (R&D), investment and acquisition priorities aimed at ensuring the U.S. remains the global leader in the semiconductor industry.

As global economic trends and technologies such as artificial intelligence evolve, and foreign governments increasingly lure microelectronics manufacturing investments overseas, the U.S. strategy for manufacturing advanced semiconductors and driving research and development (R&D) in technology innovation has become an economic priority.

The White House selected SEMICON West, organized by SEMI, as the site for the discussion and this urgent call to action because of the event’s central role in bringing together critical industries across the global electronics supply chain. The multi-agency panel will outline activities and new policies under development to ensure U.S. strategic leadership in microelectronics, including focused investment in innovations key to the next generation of devices for commercial and government use. The initiative also includes public-private partnerships to accelerate the capabilities of advanced semiconductors for critical applications such as artificial intelligence (AI), cyber, secure communications, the internet of things (IoT) and big data analytics.

PANEL:
National Strategy for Semiconductor and Microelectronic Innovation
TIME AND DATE:
10:30 to 11:30 a.m., Wednesday, July 11
LOCATION:
Yerba Buena Theater, 700 Howard St., San Francisco
MODERATOR:
Dr. Lloyd Whitman, Principal Assistant Director, Physical Sciences and Engineering, White House Office of Science and Technology Policy
PANELISTS:
Dr. Sankar Basu, Program Director, Computer and Information Science and Engineering, National Science Foundation
Dr. Eric W. Forsythe, Flexible Electronics Team Leader, U.S. Army Research Laboratory
Dr. Jeremy Muldavin, Deputy Director of Defense Software & Microelectronics Activities, Office of the Deputy Assistant Secretary of Defense for Systems Engineering
Dr. Robinson Pino, Acting Research Division Director, Advanced Scientific Computing Research, Office of Science, Department of Energy

 

SEMICON West is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry. Find more at www.semiconwest.org.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the new SmartView® NT3 aligner, which is available on the company’s industry benchmark GEMINI® FB XT integrated fusion bonding system for high-volume manufacturing (HVM) applications. Developed specifically for fusion and hybrid wafer bonding, the SmartView NT3 aligner provides sub-50-nm wafer-to-wafer alignment accuracy — a 2-3X improvement — as well as significantly higher throughput (up to 20 wafers per hour) compared to the previous-generation platform.

With the new SmartView NT3 aligner, the GEMINI FB XT provides integrated device manufacturers, foundries and outsourced semiconductor assembly and test providers (OSATs) with wafer bonding performance that is unmatched in the industry and can meet their future 3D-IC packaging requirements. Applications enabled by the enhanced GEMINI FB XT include memory stacking, 3D systems on chip (SoC), backside illuminated CMOS image sensor stacking, and die partitioning.

The new SmartView® NT3 aligner on EV Group’s GEMINI® FB XT fusion bonder enables a 2-3X improvement in wafer-to-wafer alignment accuracy over EVG’s previous-generation aligner.

Wafer Bonding an Enabling Process for 3D Device Stacking

Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices. The constant reduction in pitches that are needed to support component roadmaps is fueling tighter wafer-to-wafer bonding specifications with each new product generation.

“At imec, we believe in the power of 3D technology to create new opportunities and possibilities for the semiconductor industry, and we are devoting a great deal of energy into improving it,” stated Eric Beyne, imec fellow and program director 3D system integration. “One area of particular focus is wafer-to-wafer bonding, where we are achieving excellent results in part through our work with industry partners such as EV Group. Last year, we succeeded in reducing the distance between the chip connections, or pitch, in hybrid wafer-to-wafer bonding to 1.4 microns, which is four times smaller than the current standard pitch in the industry. This year we are working to reduce the pitch by at least half again.”

“EVG’s GEMINI FB XT fusion bonding system has consistently led the industry in not only meeting but exceeding performance requirements for advanced packaging applications, with key overlay accuracy milestones achieved with several industry partners within the last year alone,” stated Paul Lindner, executive technology director, EV Group. “With the new SmartView NT3 aligner specifically engineered for the direct bonding market and added to our widely adopted GEMINI FB XT fusion bonder, EVG once again redefines what is possible in wafer bonding — helping the industry to continue to push the envelope in enabling stacked devices with increasing density and performance, lower power consumption and smaller footprint.”

The GEMINI FB XT fusion bonder with new SmartView NT3 aligner is available for customer demonstrations and testing. More information on the product can be found on EVG’s website at https://www.evgroup.com/en/products/bonding/integrated_bonding/geminifb/.

EVG will showcase the GEMINI FB XT with new SmartView NT3 aligner, along with its complete suite of wafer bonding, lithography and resist processing solutions for advanced packaging applications, at SEMICON West, to be held July 10-12 at the Moscone Convention Center in San Francisco, Calif. Attendees interested in learning more can visit EVG at Booth #623 in the South Hall.

In addition, Dr. Thomas Uhrmann, director of business development at EV Group, will highlight the GEMINI FB XT and other developments in wafer bonding in his presentation “Collective Bonding for Heterogeneous Integration in Advanced Packaging” at the Meet the Experts Theater Smart Manufacturing Pavilion at SEMICON West on Thursday, July 12 from 3:00-3:30 p.m. in the South Hall.

Global semiconductor industry revenue declined 3.4 percent in the first quarter of 2018 falling to $115.8 billion. Semiconductor industry performance was negatively affected by the declining sales and first-quarter seasonality in the wireless communications market. Other sectors, such as automotive and consumer semiconductors, experienced nominal market growth, according to IHS Markit (Nasdaq: INFO).

The memory category experienced the highest growth of 1.7 percent in the first quarter, reaching $39.7 billion, as demand for memory components increased in the enterprise and storage markets. In fact, DRAM pricing and shipments both increased during the quarter, as strong demand for server DRAM continued to propel the semiconductor market. However, NAND began to show signs of softening, with slight revenue declines during the quarter, mainly due to single-digit price declines. “Even with the slight revenue decline during the quarter, the NAND market still achieved its second-highest revenue quarter on record, with strong demand coming from the enterprise and client solid-state drive markets,” said Craig Stice, senior director, memory and storage, IHS Markit.

Semiconductor market share

Led by its dominant position in the memory market, Samsung Electronics led the semiconductor industry in the first quarter of 2018, with 16.1 percent of the market, followed by Intel at 13.6 percent and SK Hynix at 7.0 percent. Quarter-over-quarter market shares were relatively flat, with no change in the top-three ranking list. However, on a year-over-year basis, Samsung supplanted Intel as the leading semiconductor company, compared to the first quarter of 2017.

Analog component sales for Texas Instruments, Maxim Integrated, ON Semiconductor and other companies with a strategic focus on industrial and automotive industries managed single-digit sales increases in the first quarter. In contrast, analog component revenue declined by double digits for Qualcomm, Skyworks Solutions, Oorvo and other companies targeting the wireless industry.

Memory IC companies — Samsung Electronics, SK Hynix, Micron Technologies and Toshiba — continued to dominate the top ten semiconductor companies. Micron achieved the highest growth rate in the top ten, recording 9.8 percent growth in the first quarter, compared to the previous quarter. Qualcomm revenue fell 13.6 percent, which was the largest sequential drop, due to the weakness in the wireless communication market. Qualcomm and nVidia were the only two fabless companies remaining in the top ten.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools have achieved certification for Samsung Foundry’s 7-nanometer (nm) Low Power Plus (LPP) process technology. The Cadence® tools were certified for the Process Design Kit (PDK) and foundation library on the 7LPP process and confirmed to meet Samsung Foundry’s accuracy requirements, enabling systems and semiconductor companies to accelerate the delivery of 7LPP designs.

The Cadence RTL-to-GDSII design flow that has been certified for the 7LPP process technology is based on the Design Methodology (DM) of Samsung Foundry using an OpenRISC OR1200 design.

The Cadence digital and signoff tools are available via a quick-start kit. The certified tools include the Innovus™ Implementation System, Genus™Synthesis Solution, Joules™ RTL Power Solution, Conformal® Equivalence Checking, Conformal Low Power, Modus™ DFT Software Solution, Voltus™IC Power Integrity Solution, Tempus™ Timing Signoff Solution, Quantus™ Extraction Solution, Cadence Physical Verification System (PVS), Cadence CMP Predictor (CCP) and Cadence Litho Physical Analyzer (LPA).

“Our 7LPP process provides the best power, performance and area that we have seen so far in advanced FinFET nodes, and we expect this will provide great benefits for our mutual customers’ next generation SoC designs,” said Ryan Sanghyun Lee, vice president of the Foundry Marketing at Samsung Electronics. “By working closely with Cadence, we have been able to ensure that our customers can get these benefits quickly and easily using the certified Cadence digital and signoff full flow.”

“Using our full RTL-to-GDSII reference flow, our customers can take advantage of the advanced-node innovation provided in the 7LPP process,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “Our ongoing collaboration with Samsung Foundry enables us to provide the tools our customers require to quickly complete the most complex designs.”

Fujitsu Semiconductor Limited (Fujitsu Semiconductor) and United Microelectronics Corporation (NYSE:UMC; TWSE:2303) (“UMC”), a global semiconductor foundry, today announced that UMC will acquire all of the shares of Mie Fujitsu Semiconductor Limited (MIFS), a 300mm wafer foundry joint venture between both companies.

In addition to the 15.9% of MIFS shares currently owned by UMC, Fujitsu Semiconductor will transfer the remaining 84.1% of its shares in MIFS to UMC, making MIFS a wholly-owned subsidiary of the Taiwan-based foundry. The consideration of the transaction will be around ¥ JPN 57.6 billion. The transfer is planned for January 1, 2019, pending approval by the relevant governmental authorities.

In 2014, both companies concluded an agreement for UMC to acquire a 15.9% stake in MIFS through progressive phases. Since then, besides equity investment, Fujitsu Semiconductor and UMC have been furthering their partnership through licensing of UMC’s 40nm technology and establishment of a 40nm logic production line at MIFS. After several years of joint operations, both companies have agreed on the benefits of integrating MIFS into UMC, which has a strong business foundation as a world leading semiconductor foundry with a broad customer portfolio, enhanced manufacturing expertise and extensive technology offerings enabling MIFS to maximize its values it can deliver to all stakeholders, including its customers.

As a member of UMC, MIFS will continue to provide foundry services of an even higher quality to its customers. While the name of the company and details of distribution after the transaction will soon be determined, for the present, MIFS will maintain its existing distribution channels for customers.

Jason Wang, co-president of UMC said, “UMC is experiencing high demand from mature 12″ processes. With new applications in 5G, IoT, automotive and AI requiring these technologies, we anticipate the market conditions driving this demand to remain strong for the foreseeable future. The acquisition of a fully qualified, equipped, and volume production proven 12″ facility provides greater time and ROI advantages compared to building a fab from scratch, which would cost several billion dollars and several years to construct and equip. With existing 300mm fabs in Taiwan, China and Singapore, Japan-based MIFS will help customers further diversify their manufacturing risk with a robust production base to ensure business continuity, which is especially important for automotive chip makers who require a stable and uninterrupted source of supply. UMC will also be able to leverage its decades of world class IC production experience with Japan’s local talent and world-renowned quality standards to better serve Japanese and international customers. We are excited that the strong partnership between UMC and Fujitsu Semiconductor will enable us to achieve further growth and provide customers with higher value through the acquisition of MIFS.”

“With its strengths in technology, such as ultra-low power consumption process technology, non-volatile memory technology for embedded applications, and RF and mmWave technology, as well as its highly reliable production system, as accepted by automotive customers, and its outstanding and experienced workforce, MIFS has been providing its customers with high quality foundry services” said Kagemasa Magaribuchi, President and Representative Director of Fujitsu Semiconductor. “To sustain its growth in the future and deliver far greater values to its customers, Fujitsu Semiconductor and MIFS have determined that it is the best to further enhance its competitiveness as a pure-play foundry by becoming a member of the UMC Group, a leading global semiconductor foundry. I expect that, by fully leveraging the UMC Group’s strengths, including its expertise and its cost competitiveness driven both by capital investment backed by ample financial resources as well as its globally expanded businesses, MIFS will further grow as a global company. I believe that the further growth of MIFS will also contribute to maintaining and expanding a workforce and to the local economy in the regions MIFS resides.”

An international collaborative research group including Tokyo Institute of Technology, Universite PARIS DIDEROT and CNRS has discovered that CO2 is selectively reduced to CO[1] when a photocatalyst[2] composed of an organic semiconductor material and an iron complex is exposed to visible light. They have made clear that it is possible to convert CO2, the major factor of global warming, into a valuable carbon resource using visible light as the energy source, even with a photocatalyst composed of only commonly occurring elements.

This is CO2 reduction using a photocatalyst combining carbon nitride and an iron compl. Credit: Osamu Ishitani

In recent years, technologies to reduce CO2into a resource using metal complexes and semiconductors as photocatalysts are being developed worldwide. If this technology called artificial photosynthesis can be applied, scientists would be able to convert CO2, which is considered the major factor of global warming and is being treated as a villain, into a valuable carbon resource using sunlight as the energy source.

Complexes and inorganic semiconductors containing precious and rare metals such as ruthenium, rhenium, and tantalum have been used in highly active photocatalysts reported so far. However, considering the tremendous amount of CO2, there was a need to create new photocatalysts made only with elements widely available on Earth.

Professor Osamu Ishitani, Associate Professor Kazuhiko Maeda, research staff Ryo Kuriki and others of Tokyo Tech, with the support of JST (Japan Science and Technology Agency)’s Strategic Basic Research Programs (CREST Establishment of Molecular Technology towards the Creation of New Functions) for international collaborative research projects, performed collaborative research with the research group of Professor Marc Robert of Universite PARIS DIDEROT and CNRS. As a result, by fusing carbon nitride, an organic semiconductor, with a complex made of iron and organic materials and using it as a photocatalyst, they succeeded in turning CO2 into a resource at high efficiency under the condition of exposure to visible light at ordinary temperature and pressure.

By combining the organic semiconductor carbon nitride[3], made of carbon and nitrogen, with an iron complex and using it as a photocatalyst, they found that they could reduce carbon dioxide (CO2) to carbon monoxide (CO) at high efficiency. This photocatalytic reaction progresses when exposed to visible light, which is the major component in the wavelength band of sunlight. The carbon nitride absorbs visible light and drives the migration of electrons from the reducing agent to the iron complex, the catalyst. The iron complex uses that electrons to reduce CO2 to CO. The turnover number[4], the external quantum efficiency[5], and the selectivity[6] of CO2 reduction–performance indicators for the formation of CO–reached 155, 4.2%, and 99%, respectively. These values are almost the same as when precious metal or rare metal complexes are used, and about ten times more than photocatalysts reported so far using base metals or organic molecules.

This research was the first to demonstrate that CO2 can be reduced into a resource efficiently using sunlight as the energy source, even by using materials which exist abundantly on Earth, such as carbon, nitrogen, and iron. Tasks remaining are to further improve their function as a photocatalyst and to succeed in fusing them with oxidation photocatalysts which can use water, which exists abundantly on Earth and is inexpensive, as a reducing agent.

TowerJazz, the global specialty foundry, today announced a ramp for its radio frequency silicon-on-insulator (RF SOI) 65nm process in its 300mm Uozu, Japan fab. TowerJazz has signed a contract with long-term partner, SOITEC, a semiconductor materials supplier to guarantee a supply of tens of thousands of 300mm SOI silicon wafers, securing wafer prices for the next years and ensuring supply to its customers, despite a very tight SOI wafer market.

With best in class metrics, TowerJazz’s 65nm RF SOI process enables the combination of low insertion loss and high power handling RF switches with options for high-performance low-noise amplifiers as well as digital integration. The process can reduce losses in an RF switch improving battery life and boosting data rates in handsets and IoT terminals.

According to Mobile Experts, LLC, a market research firm for mobile communications, the mobile RF front-end market is estimated to reach $22 billion in 2022 from an estimated $16 billion in 2018. TowerJazz’s breakthrough RF SOI technology continues to support this high-growth market and is well-poised to take advantage of next-generation 5G standards which will boost data rates and provide further content growth opportunities in the coming years.

TowerJazz is also proud to announce its relationship with Maxscend, a provider of RF components and IoT integrated circuits, ramping in this new technology.

“We chose TowerJazz for its advanced technology capabilities and its ability to deliver in high volume while continuously innovating with a strong roadmap. We specifically selected its 300mm 65nm RF SOI platform for our next-generation product line due to its superior performance, enabling low insertion loss and high power handling,” said Zhihan Xu, Maxscend Chief Executive Officer.

“We are delighted to see the strong adoption of 300mm RF SOI through this large capacity and supply agreement with TowerJazz to augment our already significant 200mm RF SOI partnership.  TowerJazz was the first foundry to ramp our RFeSI products to high volume production in 200mm and continues as one of the industry leaders in innovation in this exciting RF market with advanced and differentiated offerings,” said Paul Boudre, SOITEC Chief Executive Officer.

“We are thrilled about our continued partnership with Maxscend as they bring breakthrough products to market, manufactured using our latest 300mm 65nm RF SOI platform. Also, we are very pleased with our SOITEC partnership to secure tens of thousands of 300mm RF SOI wafers to feed the strong demand in our 300mm Japan factory,” said Russell Ellwanger, TowerJazz Chief Executive Officer.

For more information on TowerJazz’s 65nm RF SOI technology, please visit: http://www.towerjazz.com/sige-bicmos_rf-cmos.html.

Brewer Science has been awarded a 2018 Top Workplaces honor by the St. Louis Post-Dispatch. Based solely on feedback obtained through an anonymous employee survey, the designation recognizes St. Louis-area employers that offer dynamic work environments to satisfied employees.

The survey, which measured various aspects of workplace culture, was administered by research partner Energage, LLC, a leading provider of technology-based employee engagement tools.

“Top Workplaces is more than just recognition,” said Doug Claffey, CEO of Energage. “Our research shows organizations that earn the award attract better talent, experience lower turnover, and are better equipped to deliver bottom-line results. Their leaders prioritize and carefully craft a healthy workplace culture that supports employee engagement.”

Since the inception of the company in 1981, Dr. Terry Brewer, founder and president of Brewer Science, has been dedicated to creating an environment where employees have the freedom to be innovative. “The culture of creativity at Brewer Science provides opportunities for employees to grow personally and professionally,” explains Alan Gerson, Executive Director, Human Resources. “By giving employees opportunities to participate in wellness programs, community events and mentorships as well as engage in challenging work, Brewer Science is committed to being a company of the people, by the technology and for the customer. This commitment sets us apart as a unique company and makes Brewer Science a rewarding place to work.”

The St. Louis Post-Dispatch has previously recognized Brewer Science as a Top Workplace or honorable mention in 2012, 2013, 2015, 2016, and 2017.