Category Archives: Wafer Processing

Indium Corporation, one of more than 3,000 ON Semiconductor production suppliers, was selected for its commitment to ensuring high quality and supply continuity in an evolving semiconductor market.

The annual Perfect Quality Award was presented to Weng Fai Pang, Managing Director for Asia-Pacific Operations, and Tim Twining, Vice President of Marketing, at ON Semiconductor’s Supplier Executive Conference in March in Hong Kong, China.

Indium Corporation is a materials manufacturer and supplier to the global electronics, semiconductor, thin-film, and thermal management markets. Products include solders and fluxes; brazes; thermal interface materials; sputtering targets; indium, gallium, germanium, and tin metals and inorganic compounds; and NanoFoil®. Founded in 1934, the company has global technical support and factories located in China, Malaysia, Singapore, South Korea, the United Kingdom, and the USA.

The 2018 Symposia on VLSI Technology & Circuits will deliver a unique perspective into the technological ecosystem of converging industry trends – machine learning, IoT, artificial intelligence, wearable/implantable biomedical applications, big data, and cloud computing – the emerging technologies needed for ‘smart living.’ In a weeklong conference packed with technical presentations, a demonstration session, panel discussions, focus sessions, short courses, and a new “Friday Forum” on machine learning, the microelectronics industry’s premiere international conference covers technology, circuits, and systems with a range and scope unlike any other conference.

Built around the theme of “Technology, Circuits & Systems for Smart Living,” the Symposia programintegrates advanced technology developments, innovative circuit design, and the applications that they enable as part of our global society’s adoption of smart, connected devices and systems that change the way humans interact with each other.

Plenary Sessions (June 19):
The Symposia will open with two technology plenary sessions, including “Memory Technology: The Core to Enable Future Computing Systems” by Scott DeBoer, executive VP for technology development, Micron; and “Revolutionizing Cancer Genomic Medicine by Artificial Intelligence & Supercomputing with Big Data” by Satoru Miyano, director of the Human Genome Center, Institute of Medical Science at University of Tokyo.

The following Circuits plenary sessions include “Hardware-Enabled Artificial Intelligence” by Dr. Bill Dally, chief scientist & senior VP, Nvidia; and “Semiconductor Technologies Accelerate Our Future Vision: ‘ANSHIN Platform'” by Tsuneo Komatsuzaki, advisor, SECOM.

Focus Sessions (June 19, 20 & 21):
As part of the Symposia’s ongoing program integration, a series of joint focus sessions will be held to present contributed papers from the Technology and Circuits Symposia on June 20 and 21. Topics will include: “Heterogeneous System Integration,” “Power Devices & Circuits,” “New Devices & Systems for AI,” and “Design & Technology Co-Optimization (DTCO) in Advanced CMOS Technology.”

On June 19, the Technology focus sessions will include: “Back-End Compatible Devices & Advanced Thermal Management“ and “Sensors and Devices for IoT, Medicine, & Smart Living.” The Circuits focus sessions, held on June 21, include “Machine Learning Circuits & SoCs,” and “Advanced Wireline Techniques.”

Evening Panel Sessions (June 18 & 19):
A joint panel discussion, bringing together leading experts from Technology & Circuits programs will be held June 18 to answer the question, “Is the CPU Dying or Dead? Are Accelerators the Future of Computation?”

As Moore’s Law slows down and processor architecture innovations move away from single thread performance, the future of computing seems to be moving away from the general purpose CPU. Is the era of the CPU over? Will future CPUs simply coordinate activity among accelerators and other specialized processing units? The panel will examine future computing workloads as well as the innovative technology and circuit solutions that enable them, from moving computation closer to memory, and developing bio-inspired systems.

The Technology evening panel session panel discussion, held on June 19 will examine “Storage Class Memories: Who Cares? DRAM is Scaling Fine, NAND Stacking is Great.” Memory – DRAM and NAND scaling – though difficult, has persisted due to rapid innovations and continued engineering. Although there are new economic and fundamental challenges posed to continued memory scaling, a new class of memories – Storage Class memories, appears to bridge the latency gap that exists in the memory hierarchy and promises to improve system performance. Now the real question becomes – who really cares now? System architects, DRAM/NAND manufacturers? End users? The panel will discuss the challenges and opportunities of storage class memories in the environment where DRAM and NAND scaling continue.

The question to be addressed by the Circuits evening panel session, also held on June 19, is “What’s The Next Big Thing After Smartphones?” Although smartphones have driven the industry for more than a decade, the pace of innovation is slowing, and market saturation is occurring. What will be the next big thing? The Internet of Things? Automotive electronics? Virtual reality? Something else? A set of panelists with diverse expertise will discuss the possibilities.

Thursday Luncheon (June 21):
Continuing the Symposia’s tradition of thought-provoking presentations centered around the conference theme is the Thursday luncheon talk, entitled “The Hardware of The Mind, from Turing to Today,” by Grady Booch, chief scientist for software engineering at IBM Research. As scientists continue to the computing power of the human mind, they strive to bridge the gap between the physicality of silicon and the exquisite wonder of the brain. This presentation examines the journey of the hardware of the mind – from the Iliad, to da Vinci, to Edison, to Turing, to today – including an examination of how the growing understanding of the brain transforms the engineering of silicon, and how the laws of physics as well as the laws of humanity constrain that journey.

Full Day Short Courses (June 18):
The Technology Short Course – “Device & Integration Technologies for Sub-5nm CMOS & the Next Wave of Computing” will cover a range of topics, including CMOS technology beyond the 5nm node, MOL/BEOL interconnects, atomic-level analysis for FinFET & Nanowire design, 3D integration for image sensors, neuromorphic AI hardware, memory technologies for AI/machine learning, and sensors & analog devices for next generation computing.

The first Circuits Short Course – “Designing for the Next Wave of Cloud Computing” will address advanced computer architectures, GPU applications and FPGA acceleration, the evolution of memory and in-memory computation, and advanced packaging, power delivery and cooling for cloud computing, as well as the impact of quantum computing.

The second Circuits Short Course – “Bio-Sensors, Circuits & Systems for Wearable & Implantable Medical Devices” will cover circuits and systems for mobile healthcare, analog front-ends for bio-sensors, digital phenotyping using wearable sensors, bi-directional neural interfacing, body-area networking and body-coupled communications, ultrasound-on-a-chip, as well as a CMOS-based implantable retinal prosthesis.

Demonstration Session (June 18):
Following a successful launch last year in Kyoto, the popular demonstration session will again be part of the Symposia program, providing participants an opportunity for in-depth interaction with authors of selected papers from both Technology and Circuits sessions. These demonstrations will illustrate technological concepts and analyses through table-top presentations that show device characterization, chip operational results, and potential applications for circuit-level innovations.

Friday Forum (June 22):
New to the Symposia program this year will be the Friday Forum – a full-day series of presentations focusing on how technology and circuit designers engage in and drive the future of AI/machine learning systems, a subject area that continues to evolve as an impactful driver of the integrated systems that are part of the Symposia’s “Smart Living” theme. “Machine Learning Today & Tomorrow: A Technology, Circuits & Systems View” will provide the foundations and performance metrics for machine learning systems, an examination of advanced and emerging circuit architectures for next-generation systems, as well as highlighting tools and datasets for benchmarking and evaluating service-oriented architecture (SoA) machine learning systems.

The annual Symposium on VLSI Technology & Circuits will be held at the Hilton Hawaiian Village in Honolulu, Hawaii from June 18-22, 2018, with Short Courses held on June 18 and a special Friday Forum dedicated to machine learning/AI topics on June 22. The two conferences have been held together since 1987, providing an opportunity for the world’s top device technologists, circuit and system designers to exchange leading edge research on microelectronics technology, with alternating venues between Hawaii and Japan. A single registration enables participants to attend both Symposia.

GLOBALFOUNDRIES Inc. (GF) and Toppan Photomasks, Inc. (TPI) today announced a multi-year extension to their Advanced Mask Technology Center (AMTC) joint venture in Dresden, Germany. Opened in 2002, the AMTC provides GF’s fabs in Dresden, Malta and Singapore with high-end production and development masks at world-class cycle times in support of the foundry’s ambitious technology roadmap. The AMTC also supports TPI customers worldwide from Dresden.

Owned equally by TPI and GF, the AMTC joint venture was previously extended in 2012 to further increase tool capability and capacity. This new extension to the agreement aims to continue the current charter for manufacturing production masks as well as developing mask technology for ever smaller geometries. GF is both TPI’s partner in the joint venture and a strategic and critical customer, while TPI is GF’s preferred mask supplier, leveraging AMTC and TPI’s global manufacturing network to support GF’s worldwide operations.

The AMTC provides one of the most essential and complex elements in the semiconductor manufacturing process, which puts the latest technology innovations at consumers’ fingertips.

Since its inception, the output of AMTC has grown continuously with growth rates exceeding 10 percent in recent years. Sizeable investments have enabled the AMTC to keep up with the rapid technological developments and challenges of this dynamic market sector; in 2017 alone more than 100 million euros (US$124 million) were invested.

“From computing to communication, and from automotive to medtech – our dual roadmap allows us to provide innovative technologies for the benefit of our customers around the world,” said Geoff Akiki, World Wide Mask Operations Executive at GF. “Regardless if they choose FD-SOI with its focus on energy efficiency or FinFET with its focus on high performance, both require leading-edge lithographic masks. AMTC is a great partner and provider of those masks. We are especially pleased that the experience of AMTC will be fully utilized to support us at the leading edge of chip technology.”

“Having been in place for more than 15 years, this joint venture is one of the lengthiest in the mask industry,” said Mike Hadsell, TPI CEO. “This is a testament to the synergy and commitment of the partners, as well as the strength of the AMTC and Toppan Dresden team members. AMTC is truly a best-of-breed effort that has provided high-quality masks to TPI’s customer base, both in Europe and globally.”

“AMTC was founded with a mission to be its customers’ first choice for photomasks. To achieve this goal, our experienced and dedicated team pursues cost-effective and timely manufacturing of high-quality masks for multiple nodes. In the process, the partners have continued to strengthen their relationship while allowing AMTC to serve as a valuable resource for our demanding global customer base,” noted Thomas Schmidt, AMTC’s general manager. “AMTC was established to support AMD’s microprocessor production in Dresden at the 65nm/90nm node. We have moved way beyond that and are looking beyond the current 14nm node.”

AMTC was founded in 2002 by AMD, Infineon Technologies and DuPont Photomasks, which became TPI in 2005. Subsequently, GF and TPI became the ownership partners in 2009. AMTC has seen a cumulative investment of more than US$600 million since 2002. The mask facility employs more than 250 engineers and other specialists. The company is currently expanding its team.

SEMI, the global industry association representing the electronics manufacturing supply chain, today announced that after several years of incremental increases the worldwide semiconductor photomask market surged 13 percent to a record high $3.75 billion in 2017 and is forecast to exceed $4.0 billion in 2019. The mask market is expected to grow 5 percent and 4 percent in 2018 and 2019, respectively, according to the SEMI report. Key photomask market drivers remain advanced technology feature sizes (less than 45nm) and Asia-Pacific manufacturing growth. Taiwan is again the largest photomask regional market for the seventh year in a row and is expected to retain the top spot for the duration of the forecast. Korea rose in the rankings to claim the second spot.

With the $3.75 billion in revenues, photomasks accounted for 13 percent of the total wafer fabrication materials market, behind silicon and semiconductor gases, in 2017. By comparison, SEMI reports that photomasks represented 18 percent of the total wafer fabrication materials market in 2003. Reflecting their growing importance, captive mask shops, aided by intense capital expenditures in 2011 and 2012, continue to gain market share at merchant suppliers’ expense. Captive mask suppliers accounted for 65 percent of the total photomask market last year, up from 63 percent in 2016. In 2013, captive mask shops represented 31 percent of the photomask market.

The recently published SEMI report, 2017 Photomask Characterization Summary, provides details on the 2017 Photomask Market for seven regions of the world including North America, Japan, Europe, Taiwan, Korea, China, and Rest of World. The report also includes data for each of these regions from 2003 to 2019 and summarizes lithography developments over the past year.

By Jamie Girard, Sr. Director, Public Policy, SEMI

Although many months past due, Congress on March 23 finalized the federal spending for the remainder of fiscal year (FY) 2018, only hours before a what would have been the third government shutdown of the year. Congressional spending has been allocated in fits and starts since the end of FY 2017 last September, with patchwork deals keeping things running amid pervasive uncertainty. While this clearly isn’t an ideal way to fund the federal government, the end result will make many in the business of research and development pleased with the addition of more resources for science and innovation.

There was grave concern over the future of federal spending with the release of the president’s FY 2018 budget, which would have cut the National Science Foundation (NSF) budget by 11 percent and National Institutes of Standards & Technology (NIST) spending by 30 percent. Relief came with early drafts from Congress that whittled those cuts down to between 2-9 percent. But the real boost was a February bipartisan Congressional agreement that lifted self-imposed spending caps and introduced a generous dose of non-defense discretionary spending, increasing NSF spending 3.9 percent over the previous year and the NIST budget an astounding 25.9 percent over FY 2017 levels.

SEMI applauds this much-needed support for basic research and development (R&D) at these agencies after their budgets were cut or flat-funded for multiple cycles. It is well understood that federal R&D funding is critical to U.S. competitiveness and future economic prosperity. With the stakes that high, full funding of R&D programs at the NSF and NIST should be a bipartisan national priority backed by a strong and united community of stakeholders and advocates in the business, professional, research, and education communities.

With the work for FY 2018 completed, Congress will now turn to FY 2019 spending – already behind schedule due to the belated completion of the previous year’s budget. With 2018 an election year, Congress will likely begin work on the FY 2019 budget in short order, but probably won’t complete its work prior to the November elections.  SEMI will continue to work with lawmakers to support the R&D budgets at the agencies and their important basic science research. If you’d like to know how you can be more involved with SEMI’s public policy work, please contact Jamie Girard, Sr. Director, Public Policy at [email protected].

Today, research and innovation hub in nanoelectronics and digital technologies imec, and fabless technology innovator Qromis, have announced the development of high performance enhancement mode p-GaN power devices on 200mm engineered Coefficient of Thermal Expansion (CTE)-matched substrates, processed in imec’s silicon pilot line. The substrates are offered by Qromis as commercial 200mm QST® substrates as part of their patented product portfolio. The results will be presented at next week’s CS international Conference (April 10-11, Brussels, Belgium).

Today, GaN-on-Si technology is the industry standard platform for commercial GaN power switching devices for wafer diameters up to 150mm/6 inch.  Imec has pioneered the development of GaN-on-Si power technology for 200mm/8 inch wafers and qualified enhancement mode HEMT and Schottky diode power devices for 100V, 200V and 650V operating voltage ranges, paving the way to high volume manufacturing applications. However, for applications beyond 650V such as electric cars and renewable energy, it has become difficult to further increase the buffer thickness on 200mm wafers to the levels required for higher breakdown and low leakage levels, because of the mismatch in coefficient of thermal expansion (CTE) between the GaN/AlGaN epitaxial layers and the silicon substrate.  One can envisage to use thicker Si substrates to keep wafer warp and bow under control for 900V and 1200V applications, but practice has learned that for these higher voltage ranges, the mechanical strength is a concern in high volume manufacturing, and the ever thicker wafers can cause compatibility issues in wafer handling in some processing tools.

Carefully engineered and CMOS fab-friendly QST® substrates with a CTE-matched core having a thermal expansion that very closely matches the thermal expansion of the GaN/AlGaN epitaxial layers, are paving the way to 900V-1200V buffers and beyond, on a standard semi-spec thickness 200mm substrate. Moreover, QST® substrates open perspectives for very thick GaN buffers, including realization of free-standing and very low dislocation density GaN substrates by >100 micron thick fast-growth epitaxial layers. These unique features will enable long awaited commercial vertical GaN power switches and rectifiers suitable for high voltage and high current applications presently dominated by Si IGBTs and SiC power FETs and diodes.

“QST® is revolutionizing GaN technologies and businesses for 200mm and 300mm platforms”, stated Cem Basceri, President and CEO of Qromis.  “I am very pleased to see the successful demonstration of high performance GaN power devices by stacking leading edge technologies from Qromis, imec and AIXTRON,” Basceri said.

In this specific collaboration, imec and Qromis developed enhancement mode p-GaN power device specific GaN epitaxial layers on 200mm QST®substrates, with buffers grown in AIXTRON’s G5+ C 200mm high volume manufacturing MOCVD system.

Imec then ported its p-GaN enhancement mode power device technology to the 200mm GaN-on- QST® substrates in their silicon pilotline and demonstrated high performance power devices with threshold voltage of 2.8 Volt.  “The engineered QST® substrates from Qromis facilitated a seamless porting of our process of reference from thick GaN-on-Si substrates to standard thickness GaN-on- QST® substrates using the AIX G5+ C system, in a joint effort of imec, Qromis and AIXTRON,” stated Stefaan Decoutere, program director for GaN power technology at imec. The careful selection of the material for the core of the substrates, and the development of the light-blocking wrapping layers resulted in fab-compatible standard thickness substrates and first-time-right processing of the power devices.

quormis

Plasma-Therm today announced that it has acquired KOBUS, a plasma deposition company, which enables F.A.S.T, a valuable alternative to ALD where thick and conformal films are required.

This unique deposition method is at the crossroads of ALD and CVD: F.A.S.T. stands for “Fast Atomic Sequential Technology.” F.A.S.T. is enabled by proprietary CVD reactor design combined with pulsing capability, and while capable of depositing in traditional ALD mode, it is optimal for thick and conformal layer deposition and offers new solutions for 3D integration challenges.

KOBUS offers a unique portfolio of equipment for both mature and advanced materials deposition, which merges well with Plasma-Therm’s operation, expanding the plasma-based deposition and etch suite of products for all silicon and compound semiconductor emerging applications.

This acquisition will allow Plasma-Therm to establish a solid base in Europe and conduct R&D development in the Grenoble “Silicon Valley,” a region fueled with R&D, startups and large semiconductor corporations.

Leti, a research institute of CEA Tech, today announced Leti’s silicon photonics process design kit (PDK) for photonic circuits is available in the Synopsys PhoeniX OptoDesigner suite.

Leti’s integrated silicon photonics platform has been developed for high-speed optical transceivers and highly-integrated optical interposer applications. The process design kit contains the design rules and building blocks for multi-project wafer and custom runs on Leti’s Si310 platform. It also includes a catalogue of components available at Leti, allowing Synopsys PhoeniX OptoDesigner customers to select the ones they need to build their circuits. Once the customers have a completed circuit design, Leti produces a proof of concept on a multi-project wafer run.

Used by more than 300 designers worldwide, OptoDesigner gives access to a complete set of passive components, such as grating couplers, silicon waveguides and transitions; and active components, such as high-speed Mach Zehnder modulators and high-speed germanium photodiodes based on Leti’s fab. It also includes physical verification tools checking whether the contributions meet the design rules defined by the fabrication constraints in Leti’s clean room.

“On the same mask, with this design kit, we are able to have photonic circuits performing various functions, according to the area of expertise of the different contributors,” said Andre Myko, responsible of MPW runs at Leti. “Fabless companies and academics therefore can realize substantial cost savings by ‘sharing’ production costs on multi-project wafer runs.”

Leti is a world leader in silicon photonics technology. Its photonic platform is France’s largest R&D center for the development, characterization and simulation of optoelectronic systems and components. Its activities range from component design through component fabrication, integration into systems and packaging.

“Leti’s process design kit available for Synopsys’ PhoeniX OptoDesigner is a licensed plug-in library of solutions that support multi-project wafers and custom runs provided by Leti,” said Niek Nijenhuis, global business development manager of Synopsys’ PhoeniX OptoDesigner products. “In addition to the photonic elements from the standard OptoDesigner library, Leti’s PDK contains technology-specific information like mask layer names, design rules, validated building blocks, die sizes and GDS file settings.”

Leti’s silicon photonics platform is also fully compatible with STMicroelectronics’ platform in Crolles, which enables fabless customers to take their new circuits to high-volume production.

SEMI, the global association representing the worldwide electronics manufacturing supply chain, today reported that worldwide sales of semiconductor manufacturing equipment totaled $56.6 billion in 2017, a year-over-year increase of 37 percent from 2016 sales of $41.24 billion. The data are available in the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) Report, now available from SEMI.

Korea claimed the largest market for new semiconductor equipment for the first time, shattering all previous regional spending records with $17.95 billion in equipment sales. Taiwan fell to the second position with sales of $11.49 billion. Annual spending rates increased for South Korea, Europe, China, Japan and North America. However, new equipment markets in Taiwan and Rest of World (primarily Southeast Asia) contracted.

Equipment sales to China increased 27 percent as the region maintained the third largest market position for the second year in a row. The 2017 equipment markets in Japan and North America held onto fourth and fifth places, respectively, while the Europe market rose in the rankings to the sixth spot. The global other front-end segment increased 40 percent; the wafer processing equipment market segment rose 39 percent; the assembly and packaging segment jumped 29 percent; and total test equipment sales increased 27 percent.

Compiled from data submitted by members of SEMI and the Semiconductor Equipment Association of Japan (SEAJ), the Worldwide SEMS Report is a summary of the monthly billings figures for the global semiconductor equipment industry. Categories cover wafer processing, assembly and packaging, test, and other front-end equipment. Other front-end includes mask/reticle manufacturing, wafer manufacturing, and fab facilities equipment.

Semiconductor Capital Equipment Market by World Region (2016-2017)
2017
2016
% Change
South Korea
17.95
7.69
133%
Taiwan
11.49
12.23
-6%
China
8.23
6.46
27%
Japan
6.49
4.63
40%
North America
5.59
4.49
24%
Europe
3.67
2.18
68%
Rest of World
3.20
3.55
-10%
Total
56.62
41.24
37%

Source: SEMI/SEAJ April 2018

Note: Summed subtotals may not equal the total due to rounding.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $36.8 billion for the month of February 2018, an increase of 21.0 percent compared to the February 2017 total of $30.4 billion. Global sales in February were 2.2 percent lower than the January 2018 total of $37.6 billion, reflecting typical seasonal market trends. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market continued to demonstrate substantial and consistent growth in February, notching its 19th consecutive month of year-to-year sales increases and growing by double-digit percentages across all major regional markets,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas stood out once again, with sales increasing nearly 40 percent compared to last year, and sales were up year-to-year across all major semiconductor product categories.”

Year-to-year sales increased significantly across all regions: the Americas (37.7 percent), Europe (21.7 percent), China (16.4 percent), Asia Pacific/All Other (16.2 percent), and Japan (15.5 percent). Month-to-month sales increased slightly in Europe (0.9 percent), but fell somewhat in Japan (-0.9 percent), Asia Pacific/All Other (-1.5 percent), China (-2.6 percent), and the Americas (-4.3 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook.

Feb 2018

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

8.63

8.26

-4.3%

Europe

3.40

3.43

0.9%

Japan

3.21

3.18

-0.9%

China

12.01

11.70

-2.6%

Asia Pacific/All Other

10.35

10.19

-1.5%

Total

37.60

36.75

-2.2%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

6.00

8.26

37.7%

Europe

2.82

3.43

21.7%

Japan

2.75

3.18

15.5%

China

10.05

11.70

16.4%

Asia Pacific/All Other

8.77

10.19

16.2%

Total

30.38

36.75

21.0%

Three-Month-Moving Average Sales

Market

Sep/Oct/Nov

Dec/Jan/Feb

% Change

Americas

8.77

8.26

-5.8%

Europe

3.42

3.43

0.1%

Japan

3.21

3.18

-1.0%

China

11.90

11.70

-1.7%

Asia Pacific/All Other

10.39

10.19

-1.9%

Total

37.69

36.75

-2.5%