Category Archives: Wafer Processing

Presto Engineering Inc., an outsourced operations provider to semiconductor and Internet of Things (IoT) device manufacturers, and Maja Systems, a designer of millimeter wave (mmWave) connectivity and sensing solutions, jointly announce their successful collaboration in comprehensive wafer-level ATE for the Maja AirData family of terabit connectivity and data transport solutions.

“Presto’s special expertise in high-volume mmWave RF test was essential in bringing terabit connectivity to the market efficiently,” said Joy Laskar, CTO and SVP of Maja Systems. “They were able to develop a solution that provides reliable testing at the speeds and costs we need, and in a time frame that let us hit our market window.”

“Scalable high-volume, high-frequency RF test solutions, like this one for Maja, will be critical for the industry to achieve the billion plus annual unit volumes projected for mmWave devices by 2020,” said Michel Villemain, CEO, Presto Engineering. “We have developed custom solutions that allow us to use existing ATE, that have already been proven at volumes exceeding millions of units per year and can scale to meet projected demand.”

The Maja AirData™ family of terabit connectivity solutions, based on the MW-6022 single-chip mmWave CMOS transceiver IC and the SPL-100 compact SMT mmWave antenna, solve the terabit wireless data transport problem, addressing data center, wireless, mmWave, and optical transport applications.

SUNY Polytechnic Institute (SUNY Poly) today announced that its advanced semiconductor-based research and development efforts at its Albany NanoTech Complex have successfully received ISO 9001:2015 certification from TÜV SÜD AMERICA INC. for its effective quality management system. This certification acknowledges that SUNY Poly’s Center for Semiconductor Research (CSR) consistently provides products and services meeting the stringent and ever-improving requirements of the internationally recognized ISO 9001 designation, especially as it relates to excellent customer focus, strong top management, and a process-driven approach for the fabrication of test structures on 300mm semiconductor wafers, the platform upon which computer chips are made.

“By earning the ISO 9001:2015 certification, SUNY Poly’s technological and process management capabilities are further validated. It demonstrates the strength of SUNY’s research and development facility and capacity that renders SUNY a reliable, world-class partner for high-tech industry and contributes to New York State’s thriving innovation ecosystem,” said SUNY Interim Provost and Vice Chancellor for Research and Economic Development Grace Wang.”

“This certification showcases not only what SUNY Poly’s advanced facilities and nano-focused know-how are capable of, it is also another indication of how our institution aims to constantly improve via the implementation of its quality management systems with an eye toward continual progress,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “This is one more way in which our globally recognized partners and potential future partners will know that they can work with SUNY Poly on advanced projects with extreme confidence.”

There are more than one million companies and organizations in over 170 countries certified to ISO 9001, but it is relatively rare for a research and educational institution to obtain this certification, with SUNY Poly’s Albany NanoTech Complex sharing the high-level distinction with well-regarded facilities such as the MIT Lincoln Laboratory, for example.

SUNY Poly’s CSR is a 300mm silicon wafer fabrication facility which provides researchers and partners with an industry-compliant and state-of-the-art fully integrated research, development, and prototyping line where companies of all sizes, as well as universities, national laboratories, and other researchers are able to gain access to advanced tool sets. The ISO 9001:2015 quality management system certification will offer current and future research partners even greater assurance of SUNY Poly’s ability to consistently provide high quality products and services as SUNY Poly seeks continual improvement in this area.  In addition, it could help lead to the facilities being designated as a U.S. Department of Defense Trusted Foundry, allowing it to work with any other trusted foundry to develop next-generation semiconductor wafer technologies.

“This third-party certification and detailed audit process are a strong signal to SUNY Poly’s research partners that our facilities, our externally-focused production capacity, as well as our management of services related to the fabrication of test structures on 300mm wafers, follow the strictest, most reliable standards, and we look forward to refining and improving the processes we employ to continually increase SUNY Poly’s fabrication competencies,” said SUNY Poly VP for Research Dr. Michael Liehr.

SUNY Poly’s ISO 9001:2015 certification is also significant because it opens the doors to the potential to work with certain commercial organizations that require the use of the formal quality management system. While the certification primarily concerns SUNY Poly CSR’s test structures program, which uses advanced CMOS processing for commercial customers, research leaders anticipate expanding its scope to also cover highly advanced silicon carbide (SiC) power electronics-centered research capabilities and processes, as well as photonics efforts, such as those related to the American Institute for Manufacturing Integrated Photonics (AIM Photonics), an industry-driven public-private partnership spearheaded by the Department of Defense, SUNY Poly, and New York State with numerous top universities from around the nation and high-tech industry partners. SUNY Poly plans to seek annual recertification.

Silvaco today announced that it has acquired NanGate, a developer of Electronic Design Automation (EDA) software, that offers tools and services for creation, optimization, characterization and validation of physical library IP.

NanGate’s Library Creation Platform has been deployed by a large number of semiconductor companies creating standard cell libraries used in hundreds of SoC designs and have shipped in billions of units. NanGate’s technology is available and proven in a broad range of standard logic CMOS processes from 250nm down to 14nm nodes, available from multiple foundries. The acquisition extends Silvaco’s tools portfolio, complements Silvaco’s IC design flow and strengthens the methodology to achieve high performance, high yield standard cell libraries that meet today’s high-sigma requirements.

“We are happy for the NanGate team with their ability to deliver excellent solutions for library creation to top-tier Semiconductor companies,” said Dave Dutton, CEO of Silvaco. “Together with our leadership in variation aware design methodology with VarMan, SmartSpice, and our complete custom design flow including extraction, we are now able to deliver a complete solution for high performance standard cell libraries creation.”

“The synergy between Silvaco’s growth strategy and NanGates technology plus the combination of our talented teams will accelerate the delivery of tools and methodologies for a highly productive standard cell library and characterization flow,” said Ole Christian Andersen, President and CEO of NanGate. “We are excited to join Silvaco to further our original vision.”

Silvaco’s aggressive growth plan is designed to grow revenue by adding strategic technologies to offer the best solutions to our customers. This acquisition was led by Ron Sorisho and is the sixth acquisition for Silvaco’s business development team.

Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2018.

Enabling the AI Era with Materials Engineering

Screen Shot 2018-03-05 at 12.24.49 PMPrabu Raja, Senior Vice President, Semiconductor Products Group, Applied Materials

A broad set of emerging market trends such as IoT, Big Data, Industry 4.0, VR/AR/MR, and autonomous vehicles is accelerating the transformative era of Artificial Intelligence (AI). AI, when employed in the cloud and in the edge, will usher in the age of “Smart Everything” from automobiles, to planes, factories, buildings, and our homes, bringing fundamental changes to the way we live

Semiconductors and semiconductor processing technol- ogies will play a key enabling role in the AI revolution. The increasing need for greater computing perfor- mance to handle Deep Learning/Machine Learning workloads requires new processor architectures beyond traditional CPUs, such as GPUs, FPGAs and TPUs, along with new packaging solutions that employ high-density DRAM for higher memory bandwidth and reduced latency. Edge AI computing will require processors that balance the performance and power equation given their dependency on battery life. The exploding demand for data storage is driving adoption of 3D NAND SSDs in cloud servers with the roadmap for continued storage density increase every year.

In 2018, we will see the volume ramp of 10nm/7nm devices in Logic/Foundry to address the higher performance needs. Interconnect and patterning areas present a myriad of challenges best addressed by new materials and materials engineering technologies. In Inter- connect, cobalt is being used as a copper replacement metal in the lower level wiring layers to address the ever growing resistance problem. The introduction of Cobalt constitutes the biggest material change in the back-end-of-line in the past 15 years. In addition to its role as the conductor metal, cobalt serves two other critical functions – as a metal capping film for electro- migration control and as a seed layer for enhancing gapfill inside the narrow vias and trenches.

In patterning, spacer-based double patterning and quad patterning approaches are enabling the continued shrink of device features. These schemes require advanced precision deposition and etch technologies for reduced variability and greater pattern fidelity. Besides conventional Etch, new selective materials removal technologies are being increasingly adopted for their unique capabilities to deliver damage- and residue-free extreme selective processing. New e-beam inspection and metrology capabilities are also needed to analyze the fine pitch patterned structures. Looking ahead to the 5nm and 3nm nodes, placement or layer-to-layer vertical alignment of features will become a major industry challenge that can be primarily solved through materials engineering and self-aligned structures. EUV lithography is on the horizon for industry adoption in 2019 and beyond, and we expect 20 percent of layers to make the migration to EUV while the remaining 80 percent will use spacer multi- patterning approaches. EUV patterning also requires new materials in hardmasks/underlayer films and new etch solutions for line-edge-roughness problems.

Packaging is a key enabler for AI performance and is poised for strong growth in the coming years. Stacking DRAM chips together in a 3D TSV scheme helps bring High Bandwidth Memory (HBM) to market; these chips are further packaged with the GPU in a 2.5D interposer design to bring compute and memory together for a big increase in performance.

In 2018, we expect DRAM chipmakers to continue their device scaling to the 1Xnm node for volume production. We also see adoption of higher perfor- mance logic technologies on the horizon for the periphery transistors to enable advanced perfor- mance at lower power.

3D NAND manufacturers continue to pursue multiple approaches for vertical scaling, including more pairs, multi-tiers or new schemes such as CMOS under array for increased storage density. The industry migration from 64 pairs to 96 pairs is expected in 2018. Etch (high aspect ratio), dielectric films (for gate stacks and hardmasks) along with integrated etch and CVD solutions (for high aspect ratio processing) will be critical enabling technologies.

In summary, we see incredible inflections in new processor architectures, next-generation devices, and packaging schemes to enable the AI era. New materials and materials engineering solutions are at the very heart of it and will play a critical role across all device segments.

BY AJIT MANOCHA, President and CEO of SEMI

2017 was a terrific year for SEMI members. Chip revenues closed at nearly $440B, an impressive 22 percent year- over-year growth. The equipment industry surpassed revenue levels last reached in the year 2000. Semicon- ductor equipment posted sales of nearly $56B and semiconductor materials $48B in 2017. For semiconductor equipment, this was a giant 36 percent year-over-year growth. Samsung, alone, invested $26B in semiconductor CapEx in 2017 – an incredible single year spend in an incredible year.

MEMS and Sensors gained new growth in telecom and medical markets, adding to existing demand from automotive, industrial and consumer segments. MEMS is forecast to be a $19B industry in 2018. Flexible hybrid electronics (FHE) is also experiencing significant product design and functionality growth with increasing gains in widespread adoption.

No longer isa single monolithic demand driver propelling the electronics manufacturing supply chain. The rapidly expanding digital economy continues to foster innovation with new demand from the IoT, virtual and augmented reality (VR/AR), automobile infotainment and driver assistance, artificial intelligence (AI) and Big Data, among others. With the explosion in data usage, memory demand is nearly insatiable, holding memory device ASPs high and prompting continued heavy investment in new capacity.

2018 is forecast to be another terrific year. IC revenues are expected to increase another 8 percent and semiconductor equipment will grow 11 percent. With diverse digital economy demand continuing, additional manufacturing capacity is being added in China as fab projects come on line to develop and increase the indigenous semiconductor supply chain.

So, why worry?

The cracks starting to show are in the areas of talent, data management, and Environment, Health, and Safety (EH&S).

Can the industry sustain this growth? The electronics manufacturing supply chain has demonstrated it can generally scale and expedite production to meet the massive new investment projects. The cracks starting to show are in the areas of talent, data management, and Environment, Health, and Safety (EH&S).

Talent has become a pinch point. In Silicon Valley alone, SEMI member companies have thousands of open positions. Globally, there are more than 10,000 open jobs. Attracting new candidates and developing a global workforce are critical to sustaining the pace of innovation and growth.
Data management and effective data sharing are keys to solving problems faster and making practical novel but immature processes at the leading edge. It is ironic that other industries are ahead of semiconductor manufac- turing in harnessing manufacturing data and leveraging AI across their supply chains. Without collaborative Smart Data approaches, there is jeopardy of decreasing the cadence of Moore’s Law below the 10 nm node.

EH&S is critical for an industry that now uses the majority of the elements of the periodic table to make chips – at rates of more than 50,000 wafer starts per month (wspm) for a single fab. The industry came together strongly in the 1990s to develop SEMI Safety Standards and compliance methodologies. Since then, the number of EH&S profes- sionals engaged in our industry has declined while the number of new materials has exploded, new processing techniques have been developed, and manufacturing is expanding across China in areas with no prior semicon- ductor manufacturing experience.

HTU has been a very effective program with over 218 sessions run to date, over 7,000 students engaged, and over 70 percent of respondents pursuing careers in the STEM field.

To ensure we don’t slow growth, the industry will need to work together in 2018 in these three key areas:

Talent development needs to rapidly accelerate by expanding currently working programs and adding additional means to fill the talent funnel. The SEMI Foundation’s High Tech University (HTU) works globally with member companies to increase the number of high school students selecting Science, Technology, Engineering, and Math (STEM) fields – and provides orientation to the semiconductor manufacturing industry. HTU has been a very effective program with over 218 sessions run to date, over 7,000 students engaged, and over 70 percent of respondents pursuing careers in the STEM field. SEMI will increase the number of HTU sessions in 2018.

Plans have already been approved by SEMI’s Board of Directors to work together with SEMI’s membership to leverage existing, and pioneer new, workforce development programs to attract and develop qualified candidates from across the age and experience spectrum (high school through university, diversity, etc.). Additionally, an industry awareness campaign will be developed and launched to make more potential candidates attracted to our member companies as a great career choice. I’ll be providing you with updates on this initiative – and asking for your involvement
– throughout 2018.

Data management is a broad term. Big Data, machine learning, AI are terms that today mean different things to different people in our supply chain. What is clear is that to act together and take advantage of the unimaginable amounts of data being generating to produce materials and make semiconductor devices with the diverse equipment sets across our fabs, we need a common understanding of the data and potential use of the data.

In 2018, SEMI will launch a Smart Data vertical application platform to engage stakeholders along the supply chain to produce a common language, develop Standards, and align expectations for sharing data for mutual benefit. Bench- marking of other industries and pre-competitive pilot programs are being proposed to learn and, here too, we need the support and engagement of thought leaders throughout SEMI’s membership.

EH&S activity must intensify to maintain safe operations and to eliminate business interruptions from supply chain disruptions. There is potential for disruptions from material bans such as the Stockholm Convention action on PFOA and arising from the much wider range of chemicals and materials being used in advanced manufacturing. Being able to reliably identify these in time to guide and coordinate industry action will take a reinvigorated SEMI EH&S stewardship and membership engagement.

As China rapidly develops new fabs in many provinces – some with only limited prior experience and infrastructure – SEMI EH&S Standards orientation and training will accelerate the safe and sustainable operation of fabs, enabling them to keep pace with the ambitious growth trajectory our industry is delivering. In 2018, we’ll be looking for a renewed commitment to EH&S and sustainability for the budding challenges of new materials, methods, and emerging regions.

Remarkable results from a remarkable membership

Thank you all for a terrific 2017 and let’s work together on the key initiatives to ensure that our industry’s growth and prosperity will continue in 2018 and beyond.

In a quick review of 2017, I would like to thank SEMI’s members for their incredible results and new revenue records. Foundational to that, SEMI’s members have worked together with SEMI to connect, collaborate, and innovate to increase growth and prosperity for the industry. These founda- tional contributions have been in expositions, programs, Standards, market data, messaging (communications), and workforce development (with HTU).

The infographic below captures these foundational accom- plishments altogether. SEMI strives to speed the time to better business results for its members across the global electronics manufacturing supply chain. To do so, SEMI is dependent upon, and grateful for, the support and volunteer efforts of its membership. Thank you for a terrific 2017 and let’s work together on the key initiatives to ensure that our industry’s growth and prosperity will continue in 2018 and beyond.

As the world of advanced manufacturing enters the sub-nanometer scale era, it is clear that ALD, MLD and SAM represent viable options for delivering the required few-atoms-thick layers required with uniformity, conformality, and purity.

BY BARRY ARKLES, JONATHAN GOFF, Gelest Inc., Morrisville PA; ALAIN E. KALOYEROS, SUNY Polytechnic Institute, Albany, NY

Device and system technologies across several industries are on the verge of entering the sub-nanometer scale regime. This regime requires processing techniques that enable exceptional atomic level control of the thickness, uniformity, and morphology of the exceedingly thin (as thin as a few atomic layers) film structures required to form such devices and systems.[1]

In this context, atomic layer deposition (ALD) has emerged as one of the most viable contenders to deliver these requirements. This is evidenced by the flurry of research and devel- opment activities that explore the applicability of ALD to a variety of material systems,[2,3] as well as the limited introduction of ALD TaN in full-scale manufacturing of nanoscale integrated circuitry (IC) structures.[4] Both the success and inherent limitations of ALD associated with repeated dual-atom interactions have stimulated great interest in additional self-limiting deposition processes, particularly Molecular Layer Deposition (MLD) and Self- Assembled Monolayers (SAM). MLD and SAM are being explored both as replacements and extensions of ALD as well as surface modification techniques prior to ALD.[5]

ALD is a thin film growth technique in which a substrate is exposed to alternate pulses of source precursors, with intermediate purge steps typically consisting of an inert gas to evacuate any remaining precursor after reaction with the substrate surface. ALD differs from chemical vapor deposition (CVD) in that the evacuation steps ensure that the different precursors are never present in the reaction zone at the same time. Instead, the precursor doses are applied as successive, non-overlapping gaseous injections. Each does is followed by an inert gas purge that serves to remove both byproducts and unreacted precursor from the reaction zone.

The fundamental premise of ALD is based on self-limiting surface reactions, wherein each individual precursor-substrate interaction is instantaneously terminated once all surface reactive sites have been depleted through exposure to the precursor. For the growth of binary materials, each ALD cycle consists of two precursor and two purge pulses, with the thickness of the resulting binary layer per cycle (typically about a monolayer) being determined by the precursor-surface reaction mode. The low growth rates associated with each ALD cycle enable precise control of ultimate film thickness via the application of repeated ALD cycles. Concurrently, the self-limiting ALD reaction mechanisms allow excellent conformality in ultra-high-aspect-ratio nanoscale structures and geometries.[6]

A depiction of an individual ALD cycle is shown in FIGURE 1. In Fig. 1(a), a first precursor A is introduced in the reaction zone above the substrate surface.

Screen Shot 2018-03-01 at 3.03.03 PM

Precursor A then adsorbs intact or reacts (partially) with the substrate surface to form a first monolayer, as shown in Fig. 1(b), with any excess precursor and potential byproducts being evacuated from the reaction zone through a subsequent purge step. In Fig. 1(d), a second precursor Y is injected into the reaction zone and is made to react with the first monolayer to form a binary atomic layer on the substrate surface, as displayed in Fig. 1(e). Again, all excess precursors and reaction byproducts are flushed out with a second purge step 1(f). The entire process is performed repeatedly to achieve the targeted binary film thickness.

In some applications, a direct or remote plasma is used as an intermediate treatment step between the two precursor-surface interactions. This treatment has been reported to increase the probability of surface adsorption by boosting the number of active surface sites and lowering the reaction activation energy. As a result, such treatment has led to increased growth rates and reduce processing temperatures.[7]

A number of benefits have been cited for the use of ALD, including high purity films, absence of particle contami- nation and pin-holes, precise control of thickness at the atomic level, excellent thickness uniformity and step coverage in complex via and trench topographies, and the ability to grow an extensive array of binary material systems. However, issues with surface roughness and large surface grain morphology have also been reported. Another limitation of ALD is the fact that it is primarily restricted to single or binary material systems. Finally, extremely slow growth rates continue to be a challenge, which could potentially restrict ALD’s applicability to exceptionally ultrathin films and coatings.

These concerns have spurred a renewed interest in other molecular level processing technologies that share the self-limiting surface reaction characteristics of ALD. Chief among them are MLD and SAM. MLD refers principally to ALD-like processes that also involve successive precursor-surface reactions in which the various precursors never cross paths in the reaction zone. [8] However, while ALD is employed to grow inorganic material systems, MLD is mainly used to deposit organic molecular films. It should be noted that this definition of MLD, although the most common, is not yet universally accepted. An alternative characterization refers to MLD as a process for the growth of organic molecular components that may contain inorganic fragments, yet it does not exhibit the self-limiting growth features of ALD or its uniformity of film thickness and step coverage.[2]

A depiction illustrating a typical MLD cycle, according to the most common definition, is shown in FIGURE 2. In Fig. 2(a), a precursor is introduced in the reaction zone above the substrate surface. Precursor C adsorbs to the substrate surface and is confined by physisorption (Fig. 2(b)). The precursor then undergoes a quick chemisorption reaction with a significant number of active surface sites, leading to the self-limiting formation of molecular attachments in specific assemblies or regularly recurring structures, as displayed in Fig. 2(c). These structures form at significantly lower process temperatures compared to traditional deposition techniques.

Screen Shot 2018-03-01 at 3.03.09 PM

To date, MLD has been successfully applied to grow exceptionally thin films for applications as organic, inorganic, and hybrid organic-inorganic dielectrics and polymers for IC applications; [1,9] nanoprobes for in-vitro imaging and interrogation of biological cells; [10] photoluminescent devices; [7] and lithium-ion battery electrodes.[11]

SAM is a deposition technique that involves the spontaneous adherence of organized organic structures on a substrate surface. Such adherence takes place through adsorption from the vapor or liquid phase through relatively weak interactions with the substrate surface. Initially, the structures are adsorbed on the surface by physisorption through, for instance, van der Waals forces or polar interactions. Subsequently, the self-assembled monolayers become slowly confined by a chemisorption process, as depicted in FIGURE 3.

Screen Shot 2018-03-01 at 3.03.18 PM

The ability of SAM to grow layers as thin as a single molecule through chemisorption-driven interactions with the substrate has triggered enthusiasm for its potential use in the formation of “near-zero-thickness” activation or barrier layers. It has also sparked interest in its appli- cability to area-selective or area-specific deposition. Molecules can be directed to exhibit preferential reactions with specific segments of the underlying substrate rather than others to facilitate or obstruct subsequent material growth. This feature makes SAM desirable for incorpo- ration in area-selective ALD (AS-ALD) or CVD (AS-CVD), where the SAM-formed layer would serve as a foundation or blueprint to drive AS-ALD or AS-CVD. [12,13]

To date, SAM has been effectively employed to form organic layers as thin as a single molecule for applications as organic, inorganic, and hybrid organic-inorganic dielec- trics; polymers for IC applications; [13,14] encapsulation and barrier layers for IC metallization; [15] photoluminescent devices; [5] molecular and organic electronics; [16] and liquid crystal displays.[17]

As the world of advanced manufacturing enters the sub-nanometer scale era, it is clear that ALD, MLD and SAM represent viable options for delivering the required few-atoms-thick layers required with uniformity, conformality, and purity. By delivering the constituents of the material systems individually and sequentially into the processing environment, and precisely controlling the resulting chemical reactions with the substrate surface, these techniques enable excellent command of processing parameters and superb management of the target specifications of the resulting films. In order to determine whether one or more ultimately make it into full-scale manufacturing, a great deal of additional R&D is required in the areas of understanding and establishing libraries of fundamental interactions, mechanisms of source chemistries with various substrate surfaces, engineering viable solutions for surface smoothness and rough morphology, and developing protocols to enhance growth rates and overall throughput.

References

1. Belyansky, M.; Conti, R.; Khan, S.; Zhou, X.; Klymko, N.; Yao, Y.; Madan, A.; Tai, L.; Flaitz, P.; Ando, T. Silicon Compat. Mater. Process. Technol. Adv. Integr. Circuits Emerg. Appl. 4 2014, 61 (3), 39–45.
2. George, S. M.; Yoon, B. Mater. Matters 2008, 3 (2), 34–37. 3. George, S. M.; Yoon, B.; Dameron, A. A. Acc. Chem. Res.
2009, 42 (4), 498–508.
4. Graef, E.; Huizing, B. International Technology Roadmap for
Semiconductors 2.0, 2015th ed.; 2015.
5. Kim, D.; Zuidema, J. M.; Kang, J.; Pan, Y.; Wu, L.; Warther, D.; Arkles, B.; Sailor, M. J. J. Am. Chem. Soc. 2016, 138 (46),
15106–15109.
6. George, S. M. Chem. Rev. 2010, 110 (1), 111–131.
7. Provine, J.; Schindler, P.; Kim, Y.; Walch, S. P.; Kim, H. J.; Kim,
K. H.; Prinz, F. B. AIP Adv. 2016, 6 (6).
8. Räupke, A.; Albrecht, F.; Maibach, J.; Behrendt, A.; Polywka,
A.; Heiderhoff, R.; Helzel, J.; Rabe, T.; Johannes, H.-H.; Kowalsky, W.; Mankel, E.; Mayer, T.; Görrn, P.; Riedl, T. 226th Meet. Electrochem. Soc. (2014 ECS SMEQ) 2014, 64 (9), 97–105.
9. Fichtner, J.; Wu, Y.; Hitzenberger, J.; Drewello, T.; Bachmann, J. ECS J. Solid State Sci. Technol. 2017, 6 (9), N171–N175.
10. Culic-Viskota, J.; Dempsey, W. P.; Fraser, S. E.; Pantazis, P. Nat. Protoc. 2012, 7 (9), 1618–1633.
11. Loebl, A. J.; Oldham, C. J.; Devine, C. K.; Gong, B.; Atanasov, S. E.; Parsons, G. N.; Fedkiw, P. S. J. Electrochem. Soc. 2013, 160 (11), A1971–A1978.
12. Sundaram, G. M.; Lecordier, L.; Bhatia, R. ECS Trans. 2013, 58 (10), 27–37.
13. Kaufman-Osborn, T.; Wong, K. T. Self-assembled monolayer blocking with intermittent air-water exposure. US20170256402 A1, 2017.
14. Arkles, B.; Pan, Y.; Kaloyeros, A. ECS Trans. 2014, 64 (9), 243–249.
15. Tan, C. S.; Lim, D. F. In ECS Transactions; 2012; Vol. 50, pp 115–123.
16. Kong, G. D.; Yoon, H. J. J. Electrochem. Soc. 2016, 163 (9), G115–G121.
17. Wu, K. Y.; Chen, W. Y.; Wang, C.-H.; Hwang, J.; Lee, C.-Y.; Liu, Y.-L.; Huang, H. Y.; Wei, H. K.; Kou, C. S. J. Electrochem. Soc. 2008, 155 (9), J244.

SMIC, Shaoxing Government, and Shengyang Group together announced today the founding of the Semiconductor Manufacturing Electronics (Shaoxing) Corporation (planned) with joint capital contributions. The signing of the joint venture agreement marks the start of a project to bring the manufacture of MEMS and power devices to Shaoxing. The Secretary of the Shaoxing Municipal Party Committee, Mr. Ma Weiguang, the Deputy Secretary and Deputy Mayor, Mr. Sheng Yuechun, the Member of the Standing Committee and Secretary General, Mr. Zhong Hongjiang, the Chairman of SMIC, Dr. Zhou Zixue, the Chief Financial Officer of SMIC, Dr. Gao Yonggang, and Senior Vice President of Strategic Development at SMIC, Ms. Ge Hong, attended the signing ceremony.

Application fields such as Artificial Intelligence, mobile communications, the Internet of Things, automotive electronics, and industrial controls are thriving and growing in pace with the growth of our intelligent society. Specialty MEMS technologies are at the core of the intelligentization of our industry and society, while the advanced manufacturing base for MEMS and power device chips is still relatively weak in China’s domestic semiconductor ecosystem. The investment of this signed joint venture amounts to ¥5.88 Billion RMB. The joint venture will focus on the fields of MEMS and power devices with a wafer and module foundry that will continue to grow and develop with sustained R&D investment. A comprehensive foundry for specialty technologies will be achieved to win leadership in China’s domestic market.

The Chairman of SMIC, Dr. Zhou Zixue indicated in his speech, “SMIC has worked on the specialty technologies of MEMS and power devices for almost ten years. This joint venture project with Shaoxing meets our strategic objectives to build an advanced manufacturing industrial cluster in the Yangtze River Delta region. We have confidence that we will create a leading first-class semiconductor corporation focused on specialty technologies.”

The Secretary of the Shaoxing Municipal Party Committee, Mr. Ma Weiguang said, “In the 1980s, Shaoxing used to be one of the most important towns for China’s IC manufacturing industry. After 40 years the smooth landing of this project will accelerate the transformation and upgrading of the phrase ‘Made in Shaoxing’ into ‘Intelligent Manufacturing in Shaoxing’. Meanwhile, seizing the opportunity to cooperate with SMIC will help to build the IC industry for specialty technologies in Shaoxing and make contributions to Intelligent Manufacturing in China.”

Since the global economic recession of 2008-2009, the IC industry has been on a mission to pare down older capacity (i.e., ≤200mm wafers) in order to produce devices more cost-effectively on larger wafers. The spree of merger and acquisition activity and the migration to producing IC devices using sub-20nm process technology has also led suppliers to eliminate inefficient wafer fabs. From 2009-2017, semiconductor manufacturers around the world have closed or repurposed 92 wafer fabs, according to data compiled, updated, and now available in IC Insights’ Global Wafer Capacity 2018-2022 report.

Figure 1 shows that since 2009, 41% of fab closures have been 150mm fabs and 26% have been 200mm wafer fabs. 300mm wafer fabs have accounted for only 10% of total fab closures since 2009. Qimonda was the first company to close a 300mm wafer fab after it went out of business in early 2009.

Figure 1

Figure 1

More recently, ProMOS closed two 300mm memory fabs in 2013 and Renesas sold its 300mm logic fab to Sony in 2014.  Sony repurposed that fab to make image sensors.  In 2017, Samsung closed its 300mm Line 11 memory fab in Yongin, South Korea, also repurposing it to manufacture image sensors. Semiconductor suppliers in Japan have closed a total of 34 wafer fabs since 2009, more than any other country/region.   In the 2009-2017 timeframe, 30 fabs were closed in North America and 17 shuttered in Europe, and only 11 wafer fabs were closed throughout the Asia-Pacific region (Figure 2).

Figure 2

Figure 2

Worldwide fab closures surged in 2009 and 2010 partly as a result of the severe economic recession at the end of the previous decade.  A total of 25 fabs were closed in 2009, followed by 22 being shut down in 2010.  Ten fabs closed in 2012 and 2013.  Two fabs were closed in 2015, the fewest number of closures per year during the 2009-2017 time span.  In 2017, 3 wafer fabs were removed from service. IC Insights has identified three wafer fabs (two 150mm fabs, one 200mm fab) that are targeted for closure this year and next.

Given the flurry of merger and acquisition activity seen in the semiconductor industry recently, the skyrocketing cost of new wafer fabs and manufacturing equipment, and as more IC companies transition to a fab-lite or fabless business model, IC Insights expects more fab closures in the coming years—a prediction that will likely please IC foundry suppliers.

Samsung Electronics today announced that it broke ground on a new EUV (extreme ultraviolet) line in Hwaseong, Korea.

With this new EUV line, Samsung will be able to strengthen its leadership in single nanometer process technology by responding to market demand from various applications, including mobile, server, network, and HPC (high performance computing), for which high performance and power efficiency are critical.

The new facility is expected to be completed within the second half of 2019 and start production ramp-up in 2020. The initial investment in the new EUV line is projected to reach USD 6 billion by 2020 and additional investment will be determined depending on market circumstances.

“With the addition of the new EUV line, Hwaseong will become the center of the company’s semiconductor cluster spanning Giheung, Hwaseong and Pyeongtaek in Korea,” said Kinam Kim, President & CEO of Device Solutions at Samsung Electronics. “The line will play a pivotal role as Samsung seeks to maintain a competitive edge as an industry leader in the coming age of the Fourth Industrial Revolution.”

Samsung has decided to utilize cutting-edge EUV technology starting with its 7-nanometer (nm) LPP (Low Power Plus) process. This new line will be set up with EUV lithography equipment to overcome nano-level technology limitations. Samsung has continued to invest in EUV R&D to support its global customers for developing next-generation chips based on this leading-edge technology.

Samsung Electronics Hwaseong Campus EUV line bird’s eye view

Samsung Electronics Hwaseong Campus EUV line bird’s eye view

GLOBALFOUNDRIES and eVaderis today announced that they are co-developing an ultra-low power microcontroller (MCU) reference design using GF’s embedded magnetoresistive non-volatile memory (eMRAM) technology on the 22nm FD-SOI (22FDX®) platform. By bringing together the superior reliability and versatility of GF’s 22FDX eMRAM and eVaderis’ ultra-low power IP, the companies will deliver a technology solution that supports a broad set of applications such as battery-powered IoT products, consumer and industrial microcontrollers, and automotive controllers.

eVaderis designed their MCU to leverage the efficient power management capabilities of the 22FDX platform, achieving more than 10 times the battery life and a significantly reduced die size compared to previous generation MCUs. The technology, developed through GF’s FDXcelerator Partner Program, will help designers push performance density and flexibility to new levels to achieve a more compact, cost-effective single-chip solution for power-sensitive applications.

“The innovative architecture of eVaderis’ ultra-low power MCU IP, designed around GF’s 22FDX eMRAM technology, is well suited for normally-off IoT applications,” said Jean-Pascal Bost, President and CEO of eVaderis. “Utilizing GF’s eMRAM as a working memory allows sections of the eVaderis MCU to power cycle frequently, without incurring the typical MCU performance penalty. eVaderis looks forward to making this silicon-proven IP available to our customers by the end of this year.”

“Wearable and IoT devices require long-lasting battery life, increased processing capability, and the integration of advanced sensors,” said Dave Eggleston, VP of Embedded Memory at GF. “As an FDXcelerator partner, eVaderis is developing an optimized MCU architecture in GF’s 22FDX with eMRAM that helps customers meet demanding requirements.”

The jointly developed reference design with GF’s 22FDX with eMRAM will be available in Q4 2018. Process design kits for 22FDX with eMRAM and RF solutions are available now. Customer prototyping of 22FDX eMRAM on multi-project wafers (MPWs) is underway, with risk production planned for 2018. Off-the-shelf eMRAM macros are available now, featuring easy design-in with both eFlash and SRAM interface options.

Customers that are interested in learning more about GF’s 22FDX with eMRAM solution, co-developed in partnership with Everspin Technologies, contact your sales representative or visit globalfoundries.com.