Category Archives: Wafer Processing

2017 Global Semiconductor Alliance Award nominees announced

November 9, 2017

The Global Semiconductor Alliance (GSA) today announced the 2017 award nominees for the GSA Awards Dinner Celebration. Featuring a new Master of Ceremonies format hosted by Wayne Brady, five-time Emmy winner and Grammy nominee, the celebration will take place on Thursday, December 7, 2017, at the Santa Clara Convention Center in Santa Clara, California. The program will recognize companies that have demonstrated excellence through their vision, strategy, execution and future opportunity. These companies will be honored for their achievements in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry.

The 2017 Dr. Morris Chang Exemplary Leadership Award winner is Ray Stata, Cofounder and Chairman of Analog Devices, Inc.

The evening’s program will recognize leading semiconductor companies that have exhibited market growth through technological innovation and exceptional business management strategies. The award categories and nominees (in alphabetical order) are as follows:

View Nominee Announcement Video

Start-Up to Watch Award

DecaWave Ltd.
Innovium, Inc.
SiFive, Inc.

Most Respected Private Semiconductor Company Award

Aquantia Corporation
Luxtera, Inc.
Montage Technology
Silego Technology, Inc.

Most Respected Emerging Public Semiconductor Company Award (Achieving $100 Million to $500 Million in Annual Sales):

Monolithic Power Systems, Inc. (MPS)
Parade Technologies, Ltd.
Power Integrations, Inc.

Most Respected Public Semiconductor Company Award (Achieving $500 Million to $1 Billion in Annual Sales):

ams AG
Shenzhen Goodix Technology Co., Ltd.
Silicon Labs

Most Respected Public Semiconductor Company Award (Achieving $1 Billion to $5 Billion in Annual Sales)

Analog Devices, Inc.
Dialog Semiconductor
Xilinx, Inc.

Most Respected Public Semiconductor Company Award (Achieving Greater than $5 Billion in Annual Sales)

Infineon Technologies AG
NVIDIA Corporation
NXP Semiconductors N.V.

Best Financially Managed Semiconductor Company Award (Achieving Up to $1 Billion in Annual Sales):

Parade Technologies, Ltd.
Silicon Labs
Silicon Motion Technology Corporation (Silicon Motion, Inc.)

Best Financially Managed Semiconductor Company Award (Achieving Greater than $1 Billion in Annual Sales)

Maxim Integrated
SK Hynix Inc.
Skyworks Solutions, Inc.

Analyst Favorite Semiconductor Company Award (chosen by analyst Rajvindra Gill of Needham & Company, LLC)

Microchip Technology Inc.
Micron Technology, Inc.
NVIDIA Corporation

Outstanding Asia Pacific Semiconductor Company Award

MediaTek Inc.
Samsung Electronics Co., Ltd.
Spreadtrum Communications

Outstanding EMEA Semiconductor Company Award

Graphcore
Infineon Technologies AG
STMicroelectronics
Valens

Enabling the A.I. era

November 8, 2017

BY PETE SINGER, Editor-in-Chief

There’s a strongly held belief now that the way in which semiconductors will be designed and manufactured in the future will be largely determined by a variety of rapidly growing applications, including artificial intelligence/deep learning, virtual and augmented reality, 5G, automotive, the IoT and many other uses, such as bioelectronics and drones.

The key question for most semiconductor manufacturers is how can they benefit from these trends? One of the goals of a recent panel assembled by Applied Materials for an investor day in New York was to answer that question.

The panel, focused on “enabling the A.I. era,” was moderated by Sundeep Bajikar (former Sellside Analyst, ASIC Design Engineer). The panelists were: Christos Georgiopoulos (former Intel VP, professor), Matt Johnson (SVP in Automotive at NXP), Jay Kerley (CIO of Applied Materials), Mukesh Khare (VP of IBM Research) and Praful Krishna (CEO of Coseer). The panel discussion included three debates: the first one was “Data: Use or Discard”; the second was “Cloud versus Edge”; and the third was “Logic versus Memory.”

“There’s a consensus view that there will be an explosion of data generation across multiple new categories of devices,” said Bajikar, noting that the most important one is the self-driving car. NXP’s Johnson responded that “when it comes to data generation, automotive is seeing amazing growth.” He noted the megatrends in this space: the autonomy, connectivity, the driver experience, and electrification of the vehicle. “These are changing automotive in huge ways. But if you look underneath that, AI is tied to all of these,” he said.

He said that estimates of data generation by the hour are somewhere from 25 gigabytes per hour on the low end, up to 250 gigabytes or more per hour on the high end. or even more in some estimates.

“It’s going to be, by the second, the largest data generator that we’ve seen ever, and it’s really going to have a huge impact on all of us.”

Intel’s Georgiopoulos agrees that there’s an enormous amount of infrastructure that’s getting built right now. “That infrastructure is consisting of both the ability to generate the data, but also the ability to process the data both on the edge as well as on the cloud,” he said. The good news is that sorting that data may be getting a little easier. “One of the more important things over the last four or five years has been the quality of the data that’s getting generated, which diminishes the need for extreme algorithmic development,” he said. “The better data we get, the more reasonable the AI neural networks can be and the simpler the AI networks can be for us to extract information that we need and turn the data information into dollars.” Check out our website at www.solid-state.com for a full report on the panel.

Temperature impact on UHP pressure transducer performance

November 8, 2017

The temperature impact on the performance of UHP pressure transducers is discussed.

BY YANLI CHEN, Ph.D. and MATTHEW MILBURN, P.E., UCT, Hayward, CA

As the semiconductor industry develops new films that require heated delivery systems, all related components need to be characterized at elevated temperatures. Vacuum pressure measurement components, typically called manometers, have been used at elevated temperatures for many years. In fact, many of the vacuum measurement transducers are internally heated to a known temperature to stabilize the mechanical relationships between moving parts and the sensors used to measure the movement. This stabilization enables the precision and inaccuracy of the measurement to be greatly improved. For positive pressure UHP transducers, this elevated temperature characterization has not been done. Based on the testing performed at UCT, temperature related performance variations are very real and must be carefully considered before choosing a positive pressure transducer for elevated temperature use. Since the industry is driving toward higher delivery system operating temperatures, temperature effects will become more important.

The UHP pressure transducer is a widely-used component in the semiconductor industry and the performance is very important for process control and process monitoring. Selecting a proper UHP pressure transducer with good performance for the specific application is challenging, because different UHP pressure transducers manufacturers have different parameters listed in their data and specification sheets. Behind the data presented, it was found that different test procedures and data processing methods were used to determine and report performance characteristics. This reality creates a situation where, without standardized test method or reporting format, neither the specifier nor the end user can compare the performance of different brands of pressure transducers. To date, the industry has not recognized the full scope of the specification problem nor developed a standardized testing and reporting program. A new push toward standardization has become available with the publishing of SEMIF113 “Test Method For Pressure Transducers Used In Gas Delivery Systems” in November of 2016.

In order to have a better understanding about the performance of different UHP pressure transducer manufacturers’ products, UCT initialized a comprehensive performance evaluation project with a participation of three major UHP pressure transducer manufacturers (MFG A, MFG B and MFG C). The totality of the project covered a total of nine test categories, including warm up time test, input voltage sensitivity test, repeatability, linearity, hysteresis and inaccuracy test, reproducibility test, thermal coefficient test, drift test, accelerated lift cycle test, proof and burst test. The topic of this paper is the thermal coefficient test. Interested readers can find the other article “Comprehensive performance evaluation of UHP pressure transducers” published on the VOL. 59 NO. 4 of Solid State Technology (June 2016), which demonstrated the test method of repeatability, linearity, hysteresis and inaccuracy.

Ideally, a pressure transducer would sense pressure and remain unaffected by other environmental changes. In reality, however, the signal output of every pressure transducer is somewhat affected by variations in environment and fluid temperature. Temperature changes can cause the expansion and contraction of the sensor materials, fill fluids, housings, and electronics. Temperature changes also can affect the sensor’s resistors and electrical connections through the thermoelectric effects. Typically, a sensor’s behavior regarding changes in temperature is characterized by two temperature coefficients: temperature effect on zero (TC zero) and temperature effect on span (TC Span). TC zero is expressed as a percentage of full scale and indicates the greatest deviation of a pressure transducer at zero setpoint per equal temperature change (such as 10K or 50°C) during the operating temperature range. TC span is also expressed as a percentage of full scale and indicates the greatest deviation of a pressure transducer at 100%FS setpoint per equal temperature change (such as 10K or 50°C) during the operating temperature range. FIGURES 1, 2 and 3 list the TC zero and TC span of pressure transducer products of MFG A, MFG B and MFG C, respectively.

Comparing the three thermal coefficient specifications above for MFG A, MFG B and MFC C, it is not possible to conclude which manufacturer’s product is the best for thermal behavior. Therefore, a standard test method and data process for thermal effects evaluation is needed.

Test setup and procedure

Three major UHP pressure transducer manufacturer (MFG A, MFG B, and MFG C) participated in this comprehensive performance evaluation project by providing test samples. Table 1 shows the detailed information of all the devices under tests (DUTs). Twelve DUTs were installed in a test fixture designed by UCT for running simultaneous tests. The schematic of the test fixture is shown in FIGURE 4. The benefit of this design is to save significant time that would be otherwise used for assembly, disassembly, and testing, and eliminates the potential for setup errors if each transducer was tested separately in the battery of tests.

The test was conducted in a temperature controlled environmental chamber (see Figure 5). The following sequence of steps were taken:

• A leak integrity test
• Make the initial zero adjustment per the manufacturer’s instructions
• Adjust the temperature of the environmental chamber to 0°C and allow the temperature to stabilize for a minimum period of two hours.
• Adjust the pressure to 0% FS (-14.7 psig), and record the signal output of all the DUTs and the pressure reference device after the pressure stabilization.
• Adjust the pressure to 100% FS(235.3 psig),andrecord the signal output of all the DUTs and the pressure reference device after the pressure stabilization.
• Repeat the same procedure for the temperature setpoints of 20°C, 40°C and 60°C at the pressure setpoints of 0%FS and 100%FS.

Results and discussion

The TC zero (0%FS) and TC span (100%FS) values of all DUTs are listed in Table 2. For each manufacturer’s sample group, the highest value for the thermal coefficients at zero and span are highlighted in red; the lowest value for the thermal coefficients at zero and span are highlighted in green. To reiterate, the smaller the TC value, the better.

• For the DUTs from MFG A, the smallest TC zero is 0.0022%FS/°C and the smallest TC span is 0.0324%FS/°C.
• For the DUTs from MFG B, the smallest TC zero is 0.0012%FS/°C and the smallest TC span is 0.0099%FS/°C.
• For the DUTs from MFG C, the smallest TC zero is 0.0102%FS/°C and the smallest TC span is 0.0215%FS/°C.
• For the DUTs from MFG A, the largest TC zero is 0.0127%FS/°C and the largest TC span is 0.0564%FS/°C.
• For the DUTs from MFG B, the largest TC zero is 0.0042%FS/°C and the largest TC span is 0.0155%FS/°C.
• For the DUTs from MFG C, the largest TC zero is 0.0283%FS/°C and the largest TC span is 0.0354%FS/°C.

The extreme TC values for each manufacturer are summarized in Table 3. As shown in this table, the MFG B product has the lowest value (0.0042%FS/°C) and MFG C product has the highest value (0.0283%FS/°C) for the TC zero. For the TC span, the MFG B product still has the lowest value (0.0155%FS/°C), and the MFG A product has the highest value (0.0564%FS/°C).

To compare the results to the published specification from MFG A, the results needed to be converted and are listed in Table 4.

Comparing test results with the published specifications (FIGURE 1), the MFG A devices are meeting their thermal coefficient specification.

To compare the results to the published specification from MFG B, the results needed to be converted and are listed in Table 5.

Compared with the published specifications (FIGURE 2), the MFG B devices are meeting their thermal coefficient specification at zero. All the MFG B devices except DUT 6 meet the of the thermal coefficient specification at span. However, the TC span for DUT 6 is 0.15550%FS/10K, which is very close to the specification value (0.15%FS/10K).

To compare the results to the published specification from MFG C, the results needed to be converted and are listed in Table 6.

Compared to the published MFG C specifications (FIGURE 3), the MFG C devices are meeting their thermal coefficient specification.

The error change with the temperature increase of all the DUTs at 0%FS is shown graphically in FIGURE 6. Comparing the three plots, it can be seen that the DUTs from manufacturer C have the largest thermal variation across the temperature range of the test as well as device to device variation. The DUTs from manufacturer B have the smallest thermal variation across the temperature range of the test as well as device to device variation.

The error change with the temperature increase of all the DUTs at 100%FS is shown graphically in FIGURE 7. Comparing the three plots, it can be seen that the DUTs from manufacturer C have the largest thermal variation across the temperature range of the test as well as device to device variation. The DUTs from manufacturer B have the smallest fluctuation across the temperature range.

Conclusion

Based on this study, transducers marketed as comparable to each other display dramatically different performance levels within a relatively small temperature range which could lead to process reproducibility challenges. As the demand for higher temperature applications increases, these temperature performance variances will become more pronounced. These variations may prove to be very problematic with tool-to-tool process replication or when a transducer is replaced as a repair activity and the new transducer does not have the same performance characteristic as the old unit. The test results also demonstrate that the published specifications need to be standardized to improve direct comparison by end users. In addition, a uniform test procedure and data processing method needs to be adopted by the industry. The pressure measurement task force of SEMI North America Gases and Facilities Committee has developed and published a new pressure transducer measurement standard in November of 2016 based on this study.

Temperature-related shift not only contributes to the overall inaccuracy of a pressure transducer in a particular application, but they also factor into the economics of designing and manufacturing pressure transducers. This is due to the fact that temperature compensation is a complex, time-consuming, and expensive process that requires a significantly larger investment in production equipment and a deeper understanding of the influencing parameters.

References

1. Chemical Engineering Progress (CEP), June 2014 Gassmann, E. (2014, June) Pressure Sensor Fundamentals: Interpreting Accuracy and Error, 37-45
2. IEC 61298-3 Process measurement and control devices-General methods and procedures for evaluating performance-Part 3: Tests for the effects of influence quantities
3. SEMI C59-1104-0211R Specifications and Guidelines for Nitrogen
4. SEMI F1-0812 Specification for leak integrity of high-purity gas piping systems and components
5. SEMI F62-1111 Test method for determining mass flow controller performance characteristics from ambient and gas temperature effects
6. SEMI F113-1116 Test method for pressure transducers used in gas delivery systems

The intelligence that leads to artificial intelligence

November 8, 2017

By Ajit Manocha, president and CEO, SEMI

Artificial intelligence (AI) may be a hot topic today, but SEMI has helped to incubate Big Data and AI since its founding. Early in SEMI’s history, SEMI’s always intelligent members worked together to introduce International Standards that enabled different pieces of equipment to collect and later pass data. At first, it was for basic interoperability and equipment state analysis. Later, SEMI data protocol Standards allowed process and metrology data to be used locally and across the fab to approach the goals of Smart Manufacturing and AI – for the equipment itself to make adjustments based on incoming wafer data.

As a part of this evolution, SEMI members developed the latest sensors and computational hardware that could ever better sense, analyze and act on the environment. Often first to use its own newly developed hardware, progress in this area was critical toward improving the likelihood of success for one of the world’s most complicated production processes – and coping with the breakneck speed of Moore’s Law – by accelerating capabilities that would later be regarded as the basis for machine learning and “thinking” systems.

Since then, process steps have increased from about 175 to as many as 1,000 for the leading technology nodes. By the time 300mm wafers were introduced, manufacturing intelligence and automation sharply increased productivity while reducing fab labor by more than 25 percent. Employing adaptive models, modern leading-edge factories are fully automated and operate at nearly 60 percent autonomous control.

Today, AI is akin to where IoT was yesterday in the hype cycle – popping up everywhere as a major consideration for the future. Neither IoT nor AI is hype, though – they’re the future. There is ever more at stake for SEMI members with AI. AI appears to be the next wave helping to maintain double-digit growth for the foreseeable future.

As part of its appeal for the global supply chain, AI can be a key silicon driver for three inflections that should benefit society. First, there is a massive increase in the amount of compute needed. Half of all the compute architectures shipping in 2021 will be supporting and processing AI.

Second, the Cloud will flourish and the Edge will bloom. By 2021, 50 percent of enterprise infrastructure will employ cognitive and artificial intelligence.

Third, new species of chips will emerge, such as the devices fueling IC content and electronics for the rapid growth of disruptive capabilities in vehicles and autonomous cars (as well as medical and agricultural applications, for example). There are also many more advantages created with and for AI as SEMI members enable new materials and advanced packaging.

What results can be measured from these changes for the global electronics manufacturing supply chain? More apps, more electronics, more silicon and more manufacturing.

On the other hand, the technologies alone create relatively little business value if the problems in our factories and markets are not well understood. There’s a great need to anticipate and guide AI. This requires a new kind of collaboration.

To address this need, SEMI’s vertical application platforms have been created for Smart Data (which is all about AI), and also for Smart MedTech, Smart Transportation, Smart Manufacturing and IoT. This higher degree of facilitated collaboration serves to cultivate multiple “smart communities” that accelerate progress for AI, better directing how connected networks and data mining can step up the pace for advancement of global prosperity. This process also provides members with access to untapped business opportunities and new players.

We at SEMI are learning right along with our members. If you attended SEMICON West in July, several lessons about AI were presented by the Executive Panel (“Meeting the Challenges of the 4^th Industrial Revolutions along the Microelectronics Supply Chain”) with Mary Puma (Axcelis), Shaheen Dayal (Intel), Lori Ciano (Brooks Automation) and Regenia Sanders (Ernst & Young). This very timely and excellent panel discussed how and where predictive analytics can have the biggest impact and the implications of sharing (and not sharing) data for problem solving and process optimization.

Ensuring that the SEMI staff gleans everything possible from the experts, we hosted an “encore” of the Executive Panel in October in our headquarters for an even more in-depth discussion about how to enhance collaboration across the supply chain in support of AI.

Going forward, these SEMI vertical platform communities will help to simplify and accelerate supply chain engagement for member value. Collaboration will play an ever greater role for using AI to master the making of advanced node semiconductor devices and enabling limitless cognitive computing. As a result, AI as we know it today, has a big head start over the previous pace of evolution for one of our great trendsetters, Moore’s Law.

Join the conversation. Find out how you can work with SEMI to advance the AI – and especially AI in semiconductor manufacturing. Frank Shemansky Jr., Ph.D., is heading up SEMI’s formation of SEMI’s Smart Data vertical application platform. Let Frank know ([email protected]) you’re interested and he’ll give you more information on what’s to come. As always, please let me know your thoughts.

Semiconductor super cycle: Market trends, drivers and forecasts

November 8, 2017

By Lara Chamness, SEMI

2017 will be a record-breaking year. Semiconductor sales will exceed $400 billion for the first time and semiconductor equipment sales will finally shatter the historic high set in 2000. What is driving this growth?

Monolithic demand drivers have been replaced by a diversity of applications including: Augmented Reality, Virtual Reality, Artificial Intelligence, cloud storage, Smart Automotive (driver assistance and autonomous), Smart Manufacturing, and Smart MedTech. These proliferating demand drivers and ensuing increasing silicon (semiconductor) content in electronics is fueling what many are calling a “super cycle.” The overwhelming majority of semiconductor devices used to enable these end markets are commodities, creating a renaissance for smaller wafer diameter fabs (200mm and smaller).

Not only are legacy fabs seeing a resurgence, the industry is seeing the evolution of China transitioning away from primarily being a consumer of chips towards developing a self-sufficient semiconductor supply chain. Spurred by the 2014 National IC Guideline, all IC ecosystem sectors in China made significant progress in 2016. Such as IC design becoming the largest semiconductor sector, surpassing IC packaging and test, with over 1,300 vendors. Advancements have been made in chip production with over 24 new fab construction projections underway or planned, prompting the wafer fab equipment market to exceed $11 billion in 2018 and to potentially surpass $18 billion by 2020.

SEMI’s complimentary webinar will take place on Thursday, November 9, 2017.

In this webinar, an overview of the latest semiconductor market trends, drivers and forecasts will be discussed. Segments covered will include fab capacity, equipment, and materials trends as well as discuss year-to-date data based on SEMI’s data collection programs. SEMI will provide a market update with data from SEMI’s Industry Research & Statistics Reports and Database, specifically highlighting two recently released reports: 200 mm Fab Outlook to 2021 and SEMI China IC Industry Outlook2017.

REGISTER for WEBINAR: 8:00am – 8:45am PST, Thur., Nov. 9, 2017

Third quarter 2017 silicon wafer shipments hit another quarterly record

November 8, 2017

Worldwide silicon wafer area shipments increased during the third quarter 2017 when compared to second quarter 2017 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,997 million square inches during the most recent quarter, a 0.7 percent increase from the record 2,978 million square inches shipped during the previous quarter. New quarterly total area shipments are 9.8 percent higher than third quarter 2016 shipments and continue to ship at their highest recorded quarterly level.

“Global silicon wafer shipment volumes surpassed record levels for the sixth quarter in a row, resulting in a new historical high,” said Chungwei (C.W.) Lee (李崇偉), chairman of SEMI SMG and spokesman, VP, Corporate Development and chief auditor of GlobalWafers (環球晶圓). “While silicon demand is strong, silicon pricing remains well below pre-downturn levels.”

Silicon* Area Shipment Trends

Source: SEMI (www.semi.org), November 2017

	Millions of Square Inches
	2Q2016	3Q2016	4Q2016	1Q2017	2Q2017	3Q2017
Total	2,706	2,730	2,764	2,858	2,978	2,997

*Semiconductor applications only

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

Kyma demonstrates high quality 200mm diameter GaN on QST templates

November 7, 2017

Kyma Technologies, Inc., a developer of advanced wide bandgap semiconductor materials technologies, announced it has used its new K200 hydride vapor phase epitaxy (HVPE) growth tool to produce high quality 200mm diameter HVPE GaN on QST (QROMIS Substrate Technology) templates.

Today’s announcement of Kyma’s development of 200mm diameter GaN on QST templates follows its announcement in 2016 of its demonstration of 150mm diameter GaN on QST templates in partnership with QROMIS, Inc. (formerly Quora Technology, Inc.) and its recent announcement of the commissioning of Kyma’s K200 HVPE growth tool.

Pictured is one of the demonstrated 200mm diameter HVPE GaN on QST templates which consists of 10 microns of HVPE GaN grown on a 5 micron MOCVD GaN on QST wafer provided by QROMIS, Inc. X-ray diffraction rocking curve linewidths for the templates fall in the range of 250 and 330 arc-sec for the symmetric {002) and asymmetric {102} XRD peaks, respectively, which is consistent with high structural quality. Low wafer bow (~50 microns) and smooth surface morphology suggest these materials should support high performance device manufacturing.

Kyma’s newly constructed K200 HVPE tool represents a first for the industry and was designed by Kyma engineers to enable uniform and rapid growth of high quality GaN on a number of different substrates.

Keith Evans, President & CEO, commented, “We have successfully transferred the process for making high quality GaN to our K200 HVPE tool. The structural quality of the GaN produced on QROMIS’ QST substrate is excellent. We are currently engaging with customers interested in large diameter GaN on QST templates.”

Kyma and Qromis are partnered for this work under a Kyma-led US DOE Phase IIB SBIR with award number DE-SC0009653.

QROMIS recently began manufacturing 200-mm QST substrates and GaN-on-QST wafers using its foundry partner Vanguard International Semiconductor (VIS). VIS is planning to offer GaN power device manufacturing services on 8-inch diameter QST platform in 2018.

QROMIS co-founder & CEO Cem Basceri added, “QROMIS’ CMOS fab-friendly 200-mm diameter QST substrates and GaN-on-QST wafers represent a disruptive technology, enabling GaN epitaxy from a few microns to hundreds of microns for GaN power applications ranging from 100V to 1,500V or beyond in lateral, quasi vertical or vertical device forms, and device manufacturing on the same 8-inch or 12-inch diameter platform at Si power device cost. Kyma’s K200 HVPE technology represent an important value-add to QST-based GaN power device manufacturing by enabling the low cost deposition of a thicker and lower defect density GaN surface than is practically achievable using MOCVD growth alone.”

Kyma is also teamed with a semiconductor equipment OEM to manufacture K200 HVPE tools for customers who prefer to bring Kyma’s HVPE GaN growth process in-house.

2017 sees advances in connected devices, memory

November 7, 2017

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing.

BY STACY WEGNER, Ottawa, Canada, and JEONGDONG CHOE, Ottawa, Canada

TechInsights analysts have been keeping an intent watch on where technology has progressed, how it’s changing, and what new developments are emerging. At the end of the first quarter, our analysts shared their insights and thoughts about what to keep an eye on as the year unfolds. In this article, they provide an update on what 2017 has delivered so far.

Intelligent, connected devices

As we wrote earlier this year, in 2016, wearables were extremely interesting mainly because there was so much uncertainty around whether or not the market would be viable. Some, no, many, say the wearables market will cool off and possibly just expire. At TechInsights, we do will not speculate about whether this market is going to survive. We will report what we find and analyze what is currently being sold. Apple, Samsung, and Huawei have all released smartwatches for what would parallel a “flagship” in the mobile market (FIGURE 1). Fitness bands are becoming even ”smarter” and combining sensors where possible. Perhaps one of the most notable developments is Nokia’s acquisition and complete integration of Withings into its existing brands.

We are witnessing the “rise of the machines,” in products from scales and hair brushes to rice cookers. Primarily these devices offer consumers convenience. For example, with a connected scale, instead of recording your weight manually, the smart scales do the job for you, syncing with various health apps so you can track your weight over time. The connected hair brush provides insights into your hair’s manageability, frizziness, dryness, split ends and breakage to provide a hair quality score. Brushing patterns, pressure applied and brush stroke counts are analyzed to measure effectiveness of brushing habits and a personal diagnosis is provided with tips and real-time product recommendations. The most common connected devices include refrigerators, lights, washing machines, thermostats, and televisions.

One dominant example is the ever-popular Amazon Echo, which has taken on a life of its own and is generating spin-off markets and competition. In July, it was reported that Amazon’s Alexa voice platform passed 15,000 skills — the voice-powered apps that run on devices like the Echo speaker, Echo Dot, newer Echo Show and others. The figure is up from the 10,000 skills Amazon officially announced in February. Amazon’s Alexa is building out an entire voice app ecosystem putting it much further ahead than its nearest competitor. The success seen with Echo has motivated other companies like Google, Lenovo, LG, Samsung and Apple to release compet- itive speakers, however it is estimated that Amazon is expected to control 70 percent of the market this year. In addition, Amazon and Microsoft recently announced a partnership to better integrate their digital assistants. This cross-platform integration provides users with access to Cortana features that Alexa is missing, and vice versa. Finally, the high- performance far-field microphones found in Amazon Echo products may soon find their way to other hardware companies as Amazon announced that the technology is available to those who want to integrate into the Alexa Experience. With its new reference solution, it’s never been easier for device makers to integrate Alexa and offer their customers the same voice experiences.

In the mobile market overall, we are seeing a strong emergence of devices targeted for the very hot market of India. The mobile devices for this market range from supporting 15 or more cellular bands to as few as five cellular bands, and that is for smart- phones. At TechInsights, we will be analyzing OEMs in India like Micromax, Intex, and Lava to see how they approach dealing with strong competitors like Samsung and Xiaomi.

Memory devices

In early 2017, 32L and 48L 3D NAND products were common and all the NAND players were eager to develop next generation 3D NAND products such as 64L and 128L. 3D NAND has been jumping into 64L (FIGURE 2). Samsung, Western Digital, Toshiba, Intel, and Micron already revealed CS or mass-products on the market. SK Hynix also showed their 72L NAND die as a CS product. In the second half of this year, we will see 64L and 72L NAND products on the commercial market. For n+1 generation with 96L or 128L, we expect that two-stacked cell array architecture for 3D NAND would be adopted in 2018. Micron/Intel will keep their own FG based 3D NAND cell structure for the next generation.

Referring to DRAM, all the major players already used their advanced process technology for cell array integration such as an advanced ALD for high-k dielectrics, low damage plasma etching and honeycomb capacitor structure. Buried WL, landing pad and plug for a capacitor node, and MESH structure are still main stream. Samsung 18nm DRAM products for DDR4 and LPDDR4X are on the market. SK Hynix and Micron will reveal the same tech node DRAM products in this year. n+1 gener- ation with 15nm or 16nm node will be next in 2018. Once 6F2 15nm DRAM cell technology is successful, 4F2 DRAM products such as a capacitorless DRAM might be delayed. In 2018, 18nm and 15nm DRAM technology will be used for GDDR6 and LPDDR5.

When it comes to emerging memory, 3D XPoint memory technology is a hot potato (FIGURE 3). The XPoint products from Intel are on the market as an Optane SSD with 16GB and 32GB. Performance including retention, reliability and speed are not matched as expected, but they used a double stacked memory cell between M4 and M5 on the memory array. It’s a PCM with GST based material. An OTS with Se-As-Ge-Si is added between the PCM and the electrode (WL or BL). We expect to see multiple (triple or quadruple) stacked XPoint memory architecture within a couple years. For other emerging memory such as STT-MRAM, PCRAM and ReRAM, we’re waiting on some commercial products from Adesto (CBRAM 45nm, RM33 series) and Everspin (STT-MRAM pMTJ 256Mb, AUP-AXL-M128).

Conclusion

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing. As our analysts continue to examine and reveal the innovations others can’t inside advanced technology, we will continue to share our findings on these and new technologies as they emerge, including how they are used, how they impact the market, and how they will be changed by the next discovery or invention.

How to solve the BEOL RC delay problem?

November 7, 2017

The RC delay issues started a few nodes ago, and the problems are becoming worse.

BY ZSOLT TOKEI, imec, Leuven, Belgium

With the 7nm technology node in the development phase and the 5nm node moving into development, transistor scaling gets ever more complex. On top of that, the performance benefits gained at the front-end-of-line (i.e., the transistors) can easily be undone if the back-end-of-line can’t come along. BEOL processing involves the creation of stacked layers of Cu wires that electrically interconnect the transistors in the chip. Today, high-end logic chips easily have 12 to 15 levels of Cu wires. With each technology node, this Cu wiring scheme becomes more complex, mainly because there are more transistors to connect with an ever tighter pitch. Shrinking dimensions also means the wires have a reduced cross-sectional area, which drives up the resistance-capacitance product (RC) of the interconnect system. And this results in strongly increasing signal delay. The RC delay issues started a few nodes ago, and the problems are becoming worse. For example, a delay of more than 30% is expected when moving from the 10nm to the 7nm node.

The current BEOL flow

Cu-based dual damascene has been the workhorse process flow for interconnects since its introduction in the mid 1990s. A simple dual damascene flow starts with the deposition of a low-k dielectric material on a structure. These low-k films are designed to reduce the capacitance and the delay in the ICs. In a next step, this dielectric layer is covered with an oxide and a resist, and vias and trenches are formed using lithography and etch steps. These vias connect one metal layer with the layer above or below. Then, a metallic barrier layer is added to prevent Cu atoms from migrating into the low-k materials (FIGURE 1). The barrier layers are deposited with physical vapor deposition, using materials such as tantalum and tantalum nitride, and subsequently coated by a Cu seed barrier. In a final step, this structure is electroplated by Cu in a chemical mechanical polishing (CMP) step.

A 5nm technology full dual damascene module

The semiconductor industry is hugely in favor of extending the current dual damascene technology as long as possible before moving to a new process. And this starts with incremental changes to the current technology, which should suffice for further scaling to at least the 5nm technology node. Researchers at imec have demonstrated a full dual damascene module for the 5nm technology node. At this node, the BEOL process becomes extremely complex, and interconnects are designed at very tight pitches. For example, a 50% area scaling in logic and 60% scaling of an SRAM cell from 7nm to 5nm results in a gate pitch at around 42nm and an intermediate first routing metal at 32nm pitch (or 16nm half pitch, which is half the distance between identical features). In these BEOL layers, trenches are created which are then filled with metal in a final metallization step. In order to create electrically functional lines, perpendicular block layers to the trenches are added, where metal traces are not formed. One of the many challenges to scaling the interconnects relates to the patterning options. Patterning these tight pitch layers is no longer possible by using single immersion lithography and direct etch steps. Only multi-patterning – which is known to be very costly and complex – is possible either by immersion or by EUV or by a combination of immersion and EUV exposures to form a single metal layer. At IITC, imec showed a full integration flow using multi-patterning, which enables the patterning of tight-pitch metal-cut (the blocks), and effectively scaling the trench critical dimension to 12nm at 16nm half pitch. The researchers also looked at the reliability, for example at electromigration issues caused by the movement of atoms in the interconnect wires. They demonstrated the ability of imec’s Cu metallization scheme at 16nm critical dimension with extendibility to 12nm width, and investigated full ruthenium (Ru) metallization as copper replacement.

Scaling the BEOL beyond the 5nm node

For the technology nodes below the 5nm, the team of imec is investigating a plethora of options and comparing their merits. Options include new materials for conductors and dielectrics, barrier layers, vias, and new ways to deposit them; innovative BEOL architectures for making 2.5D/3D structures; new patterning schemes; co-optimization of system and technology, etc.

For example, to achieve manufacturable processes and at the same time control the RC delay, scaling boosters, such as fully self-aligned vias, are increasingly being used. Via alignment is a critical step in the BEOL process, as it defines the contact area between subsequent interconnect levels. Any misalignment impacts both resistance and reliability. Imec’s team has shown the necessity of using a fully self-aligned via to achieve overlay specifications, and proposed a process flow for 12nm half pitch structures.

Also, self-assembled monolayers (SAMs) open routes to new dielectric and conductor schemes. SAMs composed of sub-1nm organic chains and terminated with desired functional groups can help engineering thin-film dielectric and metal interfaces, and can strongly inhibit interfacial diffusion. The use of SAMs has been a topic of research for the past ten years. Imec has now moved this promising concept from lab to fab, and combined SAMs with a barrier/liner/metallization scheme on a full wafer. The researchers investigated the implica- tions on the performance and scaling ability of this process flow, and demonstrated a ~18% reduction in the RC of 22nm half-pitch dual damascene intercon- nects, due to a better interface and thinner barrier.

For conventional BEOL metallization, a barrier layer is coated by a Cu seed barrier, and this structure is electroplated with low-resistive Cu, which acts as the conductor. But when moving to sub-10nm interconnects, the resistivity of Cu continues to increase. At the same time, the diffusion barrier – which is highly resistive and difficult to scale – is taking up more space, thereby increasing the overall resistance of the barrier/Cu structure. Therefore, alternative metals are being investigated that could possibly serve as a replacement for Cu and do not require a diffusion barrier. Among the potential candidates, such as Co, Ni, Mo, etc., platinum-group metals, especially ruthenium (Ru), have shown great promise due to their low bulk resistivity and resistance to oxidation. They also have a high melting point which can result in better electromigration behavior (FIGURE 2). Imec has realized Ru nanowires with 58nm2 cross section area. The nanowires exhibit low resistivity and robust wafer-level reliability. For example, a very high current carrying capacity with fusing currents as high as 720MA/cm2 was demonstrated.

At the 2017 IITC conference, this author was invited to take part in a panel discussion, organized by Applied Materials, to discuss the latest developments in metallization at single-digit nodes, the challenges and bottlenecks arising at these very small dimensions, and new application-driven requirements. Distinguished speakers from the technical field reviewed viable solutions for extending the current technology and alternative options were discussed. From the discussion it is clear that the biggest immediate benefit can be found in the area of conductors – both from the material side as well as design. Indeed, it is driving the replacement of copper at specific metallization levels. Other avenues – such as dielectric innovations, functionality in the BEOL or 2D materials – remain interesting options for the R&D pipeline.

As an option that is further out, spin wave propagation in conductors is an alternative signaling to traditional electron based propagation.

Adding additional functionality in the BEOL

In the future, more and more technology options may get dictated by the requirements of systems or even applications. This could result in a separate technology for e.g. high-performance computing, low-power mobile communication, chips for use in medical applications, or dedicated chips for IoT sensors. Along the same lines, imec is investigating the benefits of introducing additional functionality in the BEOL.

More specifically, imec is evaluating the possibility of integrating thin-film organic transistors – with typically low-leakage level – into the BEOL interconnect circuitry of Si FinFETs. The potential advantages of fabricating them together are mainly a reduced power consumption and improved area saving. A variety of circuits can fully utilize the benefits of this hybrid processing, including portable applications, eDRAM, displays and FPGA applications. As a concrete example, imec researchers are currently merging imec’s expertise in BEOL technologies and in thin-film-based flat panel displays, thereby opening opportunities for new applications…

Broadcom proposes to acquire Qualcomm

November 6, 2017

Broadcom Limited (NASDAQ: AVGO) (“Broadcom”), a semiconductor device supplier to the wired, wireless, enterprise storage, and industrial end markets, today announced a proposal to acquire all of the outstanding shares of Qualcomm Incorporated (NASDAQ: QCOM) (“Qualcomm”) for per share consideration of $70.00 in cash and stock.

Under Broadcom’s proposal, the $70.00 per share to be received by Qualcomm stockholders would consist of $60.00 in cash and $10.00 per share in Broadcom shares. Broadcom’s proposal represents a 28% premium over the closing price of Qualcomm common stock on November 2, 2017, the last unaffected trading day prior to media speculation regarding a potential transaction, and a premium of 33% to Qualcomm’s unaffected 30-day volume-weighted average price. The Broadcom proposal stands whether Qualcomm’s pending acquisition of NXP Semiconductors N.V. (“NXP”) is consummated on the currently disclosed terms of $110 per NXP share or the transaction is terminated. The proposed transaction is valued at approximately $130 billion on a pro forma basis, including $25 billion of net debt, giving effect to Qualcomm’s pending acquisition of NXP on its currently disclosed terms.

“Broadcom’s proposal is compelling for stockholders and stakeholders in both companies. Our proposal provides Qualcomm stockholders with a substantial and immediate premium in cash for their shares, as well as the opportunity to participate in the upside potential of the combined company,” said Hock Tan, President and Chief Executive Officer of Broadcom. “This complementary transaction will position the combined company as a global communications leader with an impressive portfolio of technologies and products. We would not make this offer if we were not confident that our common global customers would embrace the proposed combination. With greater scale and broader product diversification, the combined company will be positioned to deliver more advanced semiconductor solutions for our global customers and drive enhanced stockholder value.”

Tan continued, “We have great respect for the company founded 32 years ago by Irwin Jacobs, Andrew Viterbi and their colleagues, and the revolutionary technologies they developed. Following the combination, Qualcomm will be best positioned to build on its legacy of innovation and invention. Given the common strengths of our businesses and our shared heritage of, and continued focus on, technology innovation, we are confident we can quickly realize the benefits of this compelling transaction for all stakeholders. Importantly, we believe that Qualcommand Broadcom employees will benefit from substantial opportunities for growth and development as part of a larger company.”

Thomas Krause, Broadcom Chief Financial Officer, added, “The Broadcom business continues to perform very well. Broadcom has completed five major acquisitions since 2013, and has a proven track record of rapidly deleveraging and successfully integrating companies to create value for our stockholders, employees and customers. Given the complementary nature of our products, we are confident that any regulatory requirements necessary to complete a combination with Qualcomm will be met in a timely manner. We look forward to engaging immediately in discussions with Qualcomm so that we can sign a definitive agreement and complete this transaction expeditiously.”

“The combined Qualcomm/Broadcom operation would represent the third largest global semiconductor supplier. The Qualcomm shareholders are likely to be split with many viewing this opportunity as a solution to the worsening relations with Apple, whom Broadcom has a good relationship with. The potential merger raises significant questions surrounding the difficult takeover of NXP by Qualcomm and much is still to be discerned regarding the value of the Qualcomm patent holdings and its associated lucrative high-margin revenue stream,” said Stuart Carlaw, Chief Research Officer at ABI Research.