Category Archives: Wafer Processing

The ConFab, to be held May 20-23 at The Cosmopolitan of Las Vegas, is excited to announce IBM’s Dr. Rama Divakaruni will be the opening keynote for the 2018 conference. Dr. Divakaruni’s presentation is entitled, “How AI is Driving the New Semiconductor Era“. He will address the Artificial Intelligence era demands for dramatic enhancement in computational performance and efficiency of AI workloads, and discuss the needs and changes required in algorithms, systems and chip design as well as in devices and materials.

“Increased use of artificial intelligence will radically change how semiconductors are designed and manufactured, and I’m delighted IBM’s Rama Divakaruni will be sharing his insights at The ConFab in 2018,” said Pete Singer, Editor-in-Chief of Solid State Technology and the conference chair of The ConFab.

Dr. Divakaruni is responsible for IBM Advanced Process Technology Research (which includes EUV technologies and advanced unit process and enablement technologies) and he is the main interface between IBM Semiconductor Research and IBM’s Systems Leadership. Dr. Divakaruni is an IBM Distinguished Engineer and one of IBMs top inventors with over 225 issued US patents.

An impressive background – since 1994, Dr. Divakaruni has been working on advanced semiconductor technologies at IBM. Through 2003, while in DRAM Technology Development, his team introduced the world’s first sub-8F2 vertical transistor DRAM trench technology. The next two years, Dr. Divakaruni worked as the technical lead for the 90nm strained silicon technology which was the world’s first to introduce dual stress liner technology; the technology was the basis of the Nintento Wii, XBOX360 and the PlayStation3 game platforms. After a year serving as project manager for the Unit Process team, he was program manager and technical lead for the development of 45nm industry standard bulk technologies for IBM’s Joint Development Alliance. At 45nm, IBM and its development partners introduced strained silicon technology for low power mobile products thus launching strained silicon across the spectrum of bulk low power and SOI performance CMOS technologies. This technology was the basis for the first Apple I-pad, early Apple I-phones and was the technology that IBM’s partners, including Samsung, used for all their mobile platforms and devices. 

Praxair, Inc. (NYSE:PX), a global industrial gas company, has signed a long-term agreement to supply gaseous nitrogen to GLOBALFOUNDRIES in Malta, New York.

Praxair will build, own and operate a plant to support GLOBALFOUNDRIES’ advanced manufacturing processes at its Malta fabrication facility. GLOBALFOUNDRIES is a semiconductor foundry that provides design, development and fabrication services to technology companies, manufacturing chips for many of the top semiconductor companies in the world.

“With our rich history of supporting leading electronics customers worldwide, we are proud to grow Praxair’s existing relationship with GLOBALFOUNDRIES as they expand their chip manufacturing,” said Kevin Foti, president of Praxair’s U.S. industrial gases business. “As a result of this agreement, two companies with significant local New York operations are coming together and spurring growth in their businesses and the local economy as well. Our reliable supply of nitrogen and industry expertise will support GLOBALFOUNDRIES’ position as one of the leading semiconductor fabs in the world.”

“GLOBALFOUNDRIES continues to grow to meet the needs of our global customer base,” said Debra Leach, GLOBALFOUNDRIES senior director of Procurement. “A reliable supply of high-quality gaseous nitrogen is an important component of our manufacturing operation at Fab 8 in New York, especially as we expand capacity to meet demand for our leading-edge semiconductor technologies.”

The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel, may go down as one of the most memorable editions for the sheer variety and depth of its talks, sessions, courses and events.

Among the most-anticipated talks are presentations by Intel and Globalfoundries, which will each detail their forthcoming competing FinFET transistor technology platforms in a session on Wednesday morning. FinFET transistors are a major driver of the continuing progress of the electronics industry, and these platforms are as important for their commercial potential as they are for their technical innovations.*

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations, along with other events.

“Those who attend IEDM 2017 will find much that is familiar, beginning with a technical program describing breakthroughs in areas ranging from mainstream CMOS technology to innovative nanoelectronics to medical devices. The Sunday Short Courses are also a perennial favorite because they are not only comprehensive but are also taught by accomplished world experts,” said Dr. Barbara De Salvo, Scientific Director at Leti. “But we have added some new features this year. One is a fourth Plenary session, on Wednesday morning, featuring Nobel winner Hiroshi Amano. Another is a revamped Tuesday evening panel. Not only will it focus on a topic of great interest to many people, it is designed to be more open and less formal.”

Other features of the IEDM 2017 include:

  • Focus Sessions on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current Status and Perspectives.
  • A vendor exhibition will be held, based on the success of last year’s event at the IEDM.
  • The IEEE Magnetics Society will again host a joint poster session on MRAM (magnetic RAM) in the exhibit area. New for this year, though, is that the Society will also hold its annual MRAM Global Innovation Forum on Thursday, Dec. 7 at the same hotel, enabling IEDM attendees to participate. (Refer to the IEEE Magnetics Society website.) The forum consists of invited talks by leading experts and a panel discussion.

Here are details of some of the events that will take place at this year’s IEDM:

90-Minute Tutorials – Saturday, Dec. 2
These tutorials on emerging technologies will be presented by leading technical experts in each area, with the goal of bridging the gap between textbook-level knowledge and cutting-edge current research.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec

Short Courses – Sunday, Dec. 3
The day-long Short Courses provide the opportunity to learn about important developments in key areas, and they enable attendees to network with the industry’s leading technologists.

Boosting Performance, Ensuring Reliability, Managing Variability in Sub-5nm CMOS, organized by Sandy Liao of Intel, will feature the following sections:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS,Cathyrn Christiansen, Globalfoundries
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights

Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang of TSMC, will feature the following sections:

  • Embedded Non Volatile Memory for Automotive Applications, Alfonso Maurelli, STMicroelectronics
  • 3D ReRAM: Crosspoint Memory Technologies, Nirmal Ramaswamy, Micron
  • Ferroelectric Memory in CMOS Processes, Thomas Mikolajick, Namlab
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive, Danny P. Shum, Globalfoundries
  • Embedded Memories for Energy-Efficient Computing, Jonathan Chang, TSMC
  • Abundant-Data Computing: The N3XT 1,000X, Subhasish Mitra, Stanford University

Plenary Presentations – Monday, Dec. 4

  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL
  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University. Dr. Amano received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting. His talk will be preceded by the Focus Session on silicon photonics.

Evening Panel Session – Tuesday evening, Dec. 5

  • Where will the Next Intel be Headquartered?  Moderator: Prof. Philip Wong, Stanford

Entrepreneurs Lunch
Jointly sponsored by IEDM and IEEE EDS Women in Engineering, this year’s Entrepreneurs Lunch will feature Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in Ohio. The moderator will be Prof. Leda Lunardi from North Carolina State University. Gras is an engineer by training and an entrepreneur by nature. After leaving her job as a NASA power systems engineer to work for on own startup company, she discovered a passion for building startup communities and helping technology-focused companies meet their goals. Named to the Forbes ’30 Under 30′ list in 2016, among many other recognitions and awards, Gras enjoys sharing her stories of founding a cleantech company with young entrepreneurs. She speaks on entrepreneurship, women in technology and clean energy at venues such as TEDx Budapest, the Pioneers Festival, and the IEEE WIE International Women’s Leadership Conference.

 

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This SEMI forecast provides an outlook for the demand in silicon units for the period 2017–2019. The SEMI forecast shows polished and epitaxial silicon shipments totaling 11,448 million square inches in 2017; 11,814 million square inches in 2018; and 12,235 million square inches in 2019 (refer to table below). Total wafer shipments this year are expected to exceed the market high set in 2016 and are forecast to continue shipping at record levels in 2018 and 2019.

“Silicon shipment volumes are expected to ship at historic highs for this year and into 2019,” said Dan Tracy, senior director of Industry Research & Statistics at SEMI. “The expectation is for steady annual growth due to the proliferation of connected devices required for automotive, medical, wearables, and high-performance computing applications.”

2017 Silicon Shipment Forecast
(Millions of Square Inches, MSI)

Actual
Forecast
2015
2016
2017
2018
2019
MSI
10,269
10,577
11,448
11,814
12,235
Annual Growth
4.5%
3.0%
8.2%
3.2%
3.6%

Total Electronic Grade Silicon Slices* – Does not Include Non-Polished Wafers
Source: SEMI (www.semi.org), October 2017
*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

China IC industry outlook


October 17, 2017

SEMI, the global industry association and provider of independent electronics market research, today announced its new China IC Industry Outlook Report, a comprehensive report for the electronics manufacturing supply chain. With an increasing presence in the global semiconductor manufacturing supply chain, the market opportunities in China are expanding dramatically.

China is the largest consumer of semiconductors in the world, but it currently relies mainly on semiconductor imports to drive its growth. Policies and investment funds are now in place to further advance the progress of indigenous suppliers in China throughout the entire semiconductor supply chain. This shift in policy and related initiatives have created widespread interest in the challenges and opportunities in China.

With at least 15 new fab projects underway or announced in China since 2017, spending on semiconductor fab equipment is forecast to surge to more than $12 billion, annually, by 2018. As a result, China is projected to be the top spending region in fab equipment by 2019, and is likely to approach record all-time levels for annual spending for a single region.

Figure 1

Figure 1

This report covers the full spectrum of the China IC industry within the context of the global semiconductor industry. With more than 60 charts, data tables, and industry maps from SEMI sources, the report reveals the history and the latest industry developments in China across vast geographical areas ranging from coastline cities to the less developed though emerging mid-western regions.

The China IC industry ecosystem outlook covers central and local government policies, public and private funding, the industry value chain from design to manufacturing and equipment to materials suppliers. Key players in each industry sector are highlighted and discussed, along with insights into China domestic companies with respect to their international peers, and potential supply implications from local equipment and material suppliers. The report specifically details semiconductor fab investment in China, as well as the supply chain for domestic equipment and material suppliers.

Figure 2

Figure 2

Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 0981.HK), the largest and most advanced foundry in mainland China, today announced the appointment of Dr. Haijun Zhao and Dr. Liang Mong Song as SMIC Co-CEO and Executive Director.

Dr. Zhao, age 54, was appointed as the Chief Executive Officer of the Company on May 10, 2017. Dr. Zhao joined the Company in October 2010 and was appointed as Chief Operating Officer and Executive Vice President in April 2013. In July 2013, Dr. Zhao was appointed as General Manager of Semiconductor Manufacturing North China (Beijing) Corporation, a joint venture company established in Beijing and a subsidiary of the Company. Dr. Zhao received his bachelor of science and doctor of philosophy degrees in electronic engineering from Tsinghua University (Beijing) and a master degree in business administration from the University of Chicago. He has 25 years of experience in semiconductor operations and technology development.

Dr. Liang Mong Song, age 65, graduated with a doctor of philosophy degree in electrical engineering from the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. Dr. Liang has been engaged in the semiconductor industry for over 33 years, and was involved in memory and advanced logic process technology development. He owns over 450 patents and has published over 350 technical papers. He is a Fellow of Institute of Electrical and Electronic Engineers (IEEE).

Dr. Zixue Zhou, Chairman of SMIC, commented, “I am very pleased that Dr. Haijun Zhao and Dr. Liang Mong Song have joined the board of directors of SMIC as Executive Directors. I also warmly welcome Dr. Liang Mong Song to join SMIC together with Dr. Haijun Zhao to serve as Co-CEO. For decades Dr. Liang has focused on integrated circuit (“IC”) technology research and development and team management, with excellence and successful experience in advanced IC process development and management. His accession will further enhance SMIC’s ability to develop process technology and narrow the advanced technology gap between SMIC and its international peers; and at the same time, his efforts will further enhance SMIC’s ability to serve its customers and improve the metrics of SMIC’s existing technology. In addition, he brings corporate culture of top tier companies, which will enhance the company’s corporate culture to world class standards. It is believed with Dr. Haijun Zho and Dr. Liang Mong Song’s joint efforts SMIC will be led to a new height and make contributions to the development of IC industry.”

Dr. Haijun Zhao, Co-CEO of SMIC remarked, “I am pleased to join the board of directors of SMIC as Executive Director, and warmly welcome Dr. Liang Mong Song to join SMIC. Dr. Liang’s great achievements in the semiconductor industry are obvious to all. His accession will strengthen our management team, and as Co-CEO I am looking forward to working together with Dr. Liang. Together with our management and staff we will strive to make SMIC a global first-class IC enterprise.”

Dr. Liang Mong Song, Co-CEO of SMIC said, “I am greatly honored to take on the position of Co-CEO and Executive Director of SMIC, which to me, is not merely an opportunity, but also a challenge. SMIC’s rapid developments in recent years have been notable in the industry, and I am looking forward to working closely with the board of directors, Dr. Haijun Zhao and the management team to continuously improve the competitiveness of SMIC in the area of international IC manufacturing.”

sureCore Ltd. today announced it has joined the GLOBALFOUNDRIES (GF) FDXcelerator™ Partner Program and will make both their Low Power “PowerMiser” and Ultra Low Voltage “EverOn” SRAM offerings available on GF’s 22nm FD-SOI (22FDX®) process technology. PowerMiser delivers dynamic and static power savings exceeding 50 percent and 20 percent respectively. EverOn is the first commercially available SRAM to enable robust and reliable operation at near threshold voltages delivering hitherto unprecedented power savings. sureCore SRAMs are built from standard foundry bit cells and need no process modifications

“GF’s 22FDX is a logical next step for developers who are currently in 28nm bulk processes” said CEO Paul Wells. “We believe the 22FDX technology offers many technical and commercial benefits when compared to standard bulk CMOS technology. Combined with sureCore’s low power SRAM technology it will provide a best-in-class platform for the development of low power devices. In particular the EverOn SRAM will enable developers of IoT and Wearables the capability to deliver true near threshold operation by voltage scaling in tandem with the logic. Operation at as low as 550mV, the bit cell retention voltage, is a real game changer.”

“Our collaboration with sureCore enables customers to fully leverage the benefits of GF’s 22FDX platform and meet the ultra-low-power requirements of next generation connected devices,” said Alain Mutricy, senior vice president of product management at GF.

Key to the break-through is sureCore’s patented “smart-Assist” technology that allows robust operation down to the bit cell retention voltage. Other architectural improvements include enhanced sleep modes as well as array subdivision into four banks, each being independently controllable to be active, in retentive sleep or powered off thereby facilitating even greater power efficiency.

The challenges of near-threshold design drove sureCore to implement a world class verification and characterisation regime exploiting leading edge EDA tooling as well as extensive silicon validation using targeted process skews. Successful completion of industry standard High Temperature Operating Life (HTOL) tests has confirmed the inherent robustness and reliability of the EverOn SRAM.

“Low power design is placing new demands on SoC developers and, compared to the restrictions imposed by standard memory, our EverOn SRAM enables a new dimension in low power capability,” said Eric Gunn, sureCore’s COO.

A new method that precisely measures the mysterious behavior and magnetic properties of electrons flowing across the surface of quantum materials could open a path to next-generation electronics.

Found at the heart of electronic devices, silicon-based semiconductors rely on the controlled electrical current responsible for powering electronics. These semiconductors can only access the electrons’ charge for energy, but electrons do more than carry a charge. They also have intrinsic angular momentum known as spin, which is a feature of quantum materials that, while elusive, can be manipulated to enhance electronic devices.

A team of scientists, led by An-Ping Li at the Department of Energy’s Oak Ridge National Laboratory, has developed an innovative microscopy technique to detect the spin of electrons in topological insulators, a new kind of quantum material that could be used in applications such as spintronics and quantum computing.

A new microscopy method developed by an ORNL-led team has four movable probing tips, is sensitive to the spin of moving electrons and produces high-resolution results. Using this approach, they observed the spin behavior of electrons on the surface of a quantum material. Credit: Saban Hus and An-Ping Li/Oak Ridge National Laboratory, U.S. Dept. of Energy

A new microscopy method developed by an ORNL-led team has four movable probing tips, is sensitive to the spin of moving electrons and produces high-resolution results. Using this approach, they observed the spin behavior of electrons on the surface of a quantum material. Credit: Saban Hus and An-Ping Li/Oak Ridge National Laboratory, U.S. Dept. of Energy

“The spin current, namely the total angular momentum of moving electrons, is a behavior in topological insulators that could not be accounted for until a spin-sensitive method was developed,” Li said.

Electronic devices continue to evolve rapidly and require more power packed into smaller components. This prompts the need for less costly, energy-efficient alternatives to charge-based electronics. A topological insulator carries electrical current along its surface, while deeper within the bulk material, it acts as an insulator. Electrons flowing across the material’s surface exhibit uniform spin directions, unlike in a semiconductor where electrons spin in varying directions.

“Charge-based devices are less energy efficient than spin-based ones,” said Li. “For spins to be useful, we need to control both their flow and orientation.”

To detect and better understand this quirky particle behavior, the team needed a method sensitive to the spin of moving electrons. Their new microscopy approach was tested on a single crystal of Bi2Te2Se, a material containing bismuth, tellurium and selenium. It measured how much voltage was produced along the material’s surface as the flow of electrons moved between specific points while sensing the voltage for each electron’s spin.

The new method builds on a four-probe scanning tunneling microscope–an instrument that can pinpoint a material’s atomic activity with four movable probing tips–by adding a component to observe the spin behavior of electrons on the material’s surface. This approach not only includes spin sensitivity measurements. It also confines the current to a small area on the surface, which helps to keep electrons from escaping beneath the surface, providing high-resolution results.

“We successfully detected a voltage generated by the electron’s spin current,” said Li, who coauthored a paper published by Physical Review Letters that explains the method. “This work provides clear evidence of the spin current in topological insulators and opens a new avenue to study other quantum materials that could ultimately be applied in next-generation electronic devices.”

ClassOne Group, provider of semiconductor processing systems, today announced a special new financing program that seeks to give more attractive options to equipment purchasers.

ClassOne stated that the new financing program can eliminate the upfront cash outlay typically associated with equipment purchases, instead allowing more affordable and budgetable monthly payments. The new financing options will include capital leases, fair-market-value leases, term loans, payment deferrals and bridge-to-budget solutions. ClassOne has developed its new program in association with First American Vendor Finance, one of the nation’s largest and most highly respected equipment finance providers. The new financing program will be available both to current and future ClassOne customers.

“Our goal is to make it easier for users – especially budget-limited users – to acquire the tools and technology they need to achieve more profitable revenues,” said Byron Exarcos, CEO of ClassOne Group. “By integrating affordable new financing options directly into the equipment purchase process we can provide buyers with more attractive, more turnkey solutions – and put their new tools to work more quickly.”

The new financing program will be available both for ClassOne Technology and ClassOne Equipment purchases. ClassOne Technology provides new wet-chemical process tools specifically for ≤200mm wafer users, delivering advanced technology for the production of MEMs, power devices, RF, LEDs, photonics, sensors, microfluidics and other emerging technologies. ClassOne Equipment supplies the industry with certified high-quality refurbished systems, including major-name tools that cover a broad range of processing and metrology needs.

ClassOne Technology develops and produces innovative new wet-chemical equipment solutions that deliver advanced performance for the cost-conscious users of ≤200mm substrates.

With the prospects of large 450mm wafers going nowhere, IC manufacturers are increasing efforts to maximize fabrication plants using 300mm and 200mm diameter silicon substrates. The number of 300mm wafer production-class fabs in operation worldwide is expected to increase each year between now and 2021 to reach 123 compared to 98 in 2016, according to the forecast in IC Insights’ Global Wafer Capacity 2017-2021 report.

As shown in Figure 1, 300mm wafers represented 63.6% of worldwide IC fab capacity at the end of 2016 and are projected to reach 71.2% by the end of 2021, which translates into a compound annual growth rate (CAGR) of 8.1% in terms of silicon area for processing by plant equipment in the five-year period.

capacity install

Figure 1

The report’s count of 98 production-class 300mm fabs in use worldwide at the end of 2016 excludes numerous R&D front-end lines and a few high-volume 300mm plants that make non-IC semiconductors (such as power transistors).  Currently, there are eight 300mm wafer fabs that have opened or are scheduled to open in 2017, which is the highest number in one year since 2014 when seven were added, says the Global Wafer Capacity report.  Another nine are scheduled to open in 2018.   Virtually all these new fabs will be for DRAM, flash memory, or foundry capacity, according to the report.

Even though 300mm wafers are now the majority wafer size in use, both in terms of total surface area and in actual quantity of wafers, there is still much life remaining in 200mm fabs, the capacity report concludes.  IC production capacity on 200mm wafers is expected to increase every year through 2021, growing at a CAGR of 1.1% in terms of total available silicon area. However, the share of the IC industry’s monthly wafer capacity represented by 200mm wafers is forecast to drop from 28.4% in 2016 to 22.8% in 2021.

IC Insights believes there is still much life left in 200mm fabs because not all semiconductor devices are able to take advantage of the cost savings 300mm wafers can provide.  Fabs running 200mm wafers will continue to be profitable for many more years for the fabrication of numerous types of ICs, such as specialty memories, display drivers, microcontrollers, and RF and analog products.  In addition, 200mm fabs are also used for manufacturing MEMS-based “non-IC” products such as accelerometers, pressure sensors, and actuators, including acoustic-wave RF filtering devices and micro-mirror chips for digital projectors and displays, as well as power discrete semiconductors and some high-brightness LEDs.