Category Archives: Wafer Processing

North America-based manufacturers of semiconductor equipment posted $2.18 billion in billings worldwide in August 2017 (three-month average basis), according to the August Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in August 2017 was $2.18 billion.The billings figure is 3.9 percent lower than the final July 2017 level of $2.27 billion, and is 27.7 percent higher than the August 2016 billings level of $1.71 billion.

“Equipment billings in August declined relative to July, signaling a pause in this year’s extraordinary growth,” said Ajit Manocha, president and CEO of SEMI. “Nonetheless monthly billings remain well above last year’s monthly levels.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017
$2,270.5
41.8%
June 2017
$2,300.3
34.1%
July 2017 (final)
$2,269.7
32.9%
August 2017 (prelim)
$2,181.8
27.7%

Source: SEMI (www.semi.org), September 2017

Synopsys, Inc. (Nasdaq: SNPS) today announced that GLOBALFOUNDRIES (GF) has certified the Synopsys Design Platform for the GF 22nm FD-SOI (22FDX) process, ensuring designers achieve optimized implementation and predictable signoff results using industry leading digital design tools. This certification leveraged the silicon-proven GF Foundry Reference Flow for the Synopsys Design Platform, architected to realize the full potential of GF’s 22FDX process. IEEE 1801 (UPF)-driven bias voltage support throughout the flow enables optimal power and performance tradeoff during design implementation.

“GF worked closely with Synopsys to complete the rigorous certification process of the Synopsys Design Platform on our 22FDX process platform,” said Jai Durgam, vice president, Customer Design Enablement at GLOBALFOUNDRIES. “The Synopsys tools support 22FDX capabilities such as voltage dependent spacing rules, continuous-diffusion aware placement and optimal bias tap cell insertion in IC Compiler II. Having a reference flow with certified tools enables our mutual customers to take advantage of the technology differentiation, which offers FinFET-like performance and energy efficiency at a cost comparable to 28-nm planar technologies.”

Key tools and features of the Synopsys Design Platform certified for the 22FDX process include:

  • IC Compiler™ II layout with physical implementation support for non-uniform library floorplanning, implant-aware placement, multi-rail routing, and advanced power mesh creation
  • IC Validator physical signoff tool for In-Design verification, enabling early and accurate timing-aware metal fill with support for high performance DRC- and LVS-aware short finder
  • StarRC™  parasitic extraction for multi-rail signoff with support for multi-valued standard parasitic exchange format (SPEF)
  • PrimeTime® timing analysis and signoff including DMSA static timing and noise analysis, using AOCV and POCV technology

“Our broad collaboration with GLOBALFOUNDRIES has been focused on delivering the platform and IP needed for seamless adoption of the FD-SOI technology at 22 nanometers and smaller geometries,” said Michael Jackson, corporate vice president of marketing and business development for Synopsys’ Design Group. “Together, Synopsys’ full ecosystem solution and GLOBALFOUNDRIES’ FDX technology are enabling designers to take advantage of the performance and power benefits offered by this process.”

To certify their process platform with a real-world complex hierarchical design that requires the best performance in the smallest possible area and power budget, GF selected the DesignWare® EV61 Embedded Vision Processor with a convolutional neural network (CNN) engine configured for 880 MACs. DesignWare EV6x Vision Processor IP is a family of fully programmable and configurable vision processors that integrates scalar, vector DSP and CNN processing units for highly accurate and fast vision processing. Supported by a comprehensive software programing environment including the ARC® MetaWare EV Toolkit, the EV6x Vision Processors offer SoC designers a flexible, power-efficient embedded vision solution for a wide range of automotive, industrial and consumer applications.

Over the past half-century, scientists have shaved silicon films down to just a wisp of atoms in pursuit of smaller, faster electronics. For the next set of breakthroughs, though, they’ll need novel ways to build even tinier and more powerful devices.

A study led by UChicago researchers, published Sept. 20 in Nature, describes an innovative method to make stacks of semiconductors just a few atoms thick. The technique offers scientists and engineers a simple, cost-effective method to make thin, uniform layers of these materials, which could expand capabilities for devices from solar cells to cell phones.

Stacking thin layers of materials offers a range of possibilities for making electronic devices with unique properties. But manufacturing such films is a delicate process, with little room for error.

“The scale of the problem we’re looking at is, imagine trying to lay down a flat sheet of plastic wrap the size of Chicago without getting any air bubbles in it,” said Jiwoong Park, a UChicago professor with the Department of Chemistry, the Institute for Molecular Engineering and the James Franck Institute, who led the study. “When the material itself is just atoms thick, every little stray atom is a problem.”

Today, these layers are “grown” instead of stacking them on top of one another. But that means the bottom layers have to be subjected to harsh growth conditions such as high temperatures while the new ones are added — a process that limits the materials with which to make them.

Park’s team instead made the films individually. Then they put them into a vacuum, peeled them off and stuck them to one another, like Post-It notes. This allowed the scientists to make films that were connected with weak bonds instead of stronger covalent bonds–interfering less with the perfect surfaces between the layers.

“The films, vertically controlled at the atomic-level, are exceptionally high-quality over entire wafers,” said Kibum Kang, a postdoctoral associate who was the first author of the study.

Kan-Heng Lee, a graduate student and co-first author of the study, then tested the films’ electrical properties by making them into devices and showed that their functions can be designed on the atomic scale, which could allow them to serve as the essential ingredient for future computer chips.

The method opens up a myriad of possibilities for such films. They can be made on top of water or plastics; they can be made to detach by dipping them into water; and they can be carved or patterned with an ion beam. Researchers are exploring the full range of what can be done with the method, which they said is simple and cost-effective.

“We expect this new method to accelerate the discovery of novel materials, as well as enabling large-scale manufacturing,” Park said.

SEMICON Europa 2017 will take place in Munich for the first time, co-located with productronica (14-17 November in Munich, Germany). SEMICON Europa will showcase the critical issues shaping the entire electronics manufacturing supply chain. Fourexecutive keynotes will share their thought leadership on current opportunities for Europe: Maria Marced, president, TSMC Europe; Stefan Finkbeiner, CEO, Bosch Sensortec; and Frank M. Rinderknecht, founder and CEO of Rinspeed Inc.

“Innovations in semiconductor manufacturing are at the heart of the value chain driving innovations enabling key future growth drivers in Mobile, Automotive, Medical, passive and intelligent computing as well as AR and VR,” stated Laith Altimime, president, SEMI Europe. SEMICON Europa programs, sessions, and speakers will illuminate this year’s theme “Empowering Innovation and Shaping the Value Chain.”  Highlights of SEMICON Europa include:

  • Fab Management Forum: Quality Challenges – Solutions for Tomorrow ─ Topics include:Future of digital vehicles and requirements for quality and availability of semiconductors with Daimler AG, an analysis of Human failure and mindset change by European School of Management and Technology (ESMT) Berlin, and how innovative sensor and analytics solutions enable new applications in the fab of tomorrow by KINEXON GmbH.
  • Advanced Packaging Conference: Electronics Packaging and Test for Future Mobility ─With Yole Développement on the dynamics of the advanced packaging ecosystem, Robert Bosch GmbH on automotive, Infineon Technologies on packaging for automotive ─ challenges and solutions, RoodMicrotec GmbH on wafer and final test in the new era of electronics, and STMicroelectronics on packaging challenges for robust miniaturization.
  •  Power Electronics Conference: From Materials to Systems,The Latest Innovations ─Covering power electronics applications for Automotive by Fraunhofer Institute for Integrated Systems and Device Technology IISB, a forecast of the next five years to reveal how technology development will shape the power electronics market by Yole Développement, and  Cambridge University on Silicon and Wide bandgap devices in power electronics.
  • New! Materials Conference: Connected World ─ New Material Challenges and Solutions ─Includes a keynote by Christophe Maleville, SOITEC, on how to better optimize performance, power budget and cost to meet applications requirements; plus presentations from Volkswagen AG on the need for new industry alliances in automotive, FUJIFILM on maximum utilization of chemically amplified resist, and Dow Chemical on the information age and connectivity enabled by advanced electronic materials. The free Webinar “Connected World: New Material Challenges and Solutions – Market Update and Outlook“ is planned on 27 September.
  • New! European Connect2Car Forum ─ A new Forum in collaboration with SAE International. Insights for automotive OEM and supplier executives, consumer electronics leaders, mobile application developers, and aftermarket entrepreneurs focusing on enhancing the driver experience and accelerating the deployment of connected and autonomous vehicle technologies.
  • New! 2017FLEX Europe “Be Flexible” ─ New collaboration between FLEX and Fraunhofer EMFT. Insights on innovative solutions for flexible and stretchable systems by Würth Elektronik GmbH,  technology and applications of chip-film patch for hybrid systems in foil by IMS CHIPS, new capabilities and applications of flexible components by E Ink Corporation, and insight on how potentials of System-in-Package technologies will affect the future by Bosch.

SEMI and Messe München Joint Press Conference will take place on 14 November at 11:00-12:00, at Messe München Press Conference Center.

IC Insights has just released its September Update to The McClean Report.  This 32-page Update includes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends.  Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.

In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).

Figure 1

Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year.  In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion.  Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.

TSMC is by far the technology leader among the major pure-play foundries.  In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC.  In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC).  In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.

In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.  In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.

GLOBALFOUNDRIES and Soitec today announced that they have entered into a five-year agreement to ensure the volume supply of state-of-the-art fully depleted silicon-on-insulator (FD-SOI) wafers. This agreement extends the current partnership to provide a solid foundation for both companies to strengthen the FD-SOI supply chain and help ensure high-volume manufacturing.

With the leadership from the two companies, FD-SOI has become the standard technology for cost-effective, low-power devices in high-volume consumer, IoT and automotive applications. The agreement, which is effective immediately, builds on the existing close relationship between the companies and guarantees wafer supply for GF’s 22nm FD-SOI (22FDX®) technology platform.

“GLOBALFOUNDRIES is delivering industry leading ultra-low power, performance-on-demand FD-SOI solutions with cost-sensitive manufacturing options,” said John Docherty, senior vice president of Global Operations at GF. “With Soitec as a long-term strategic partner, this agreement ensures a secure supply to meet the high-volume capacity needs of current and future customers.”

“This agreement represents a long-term commitment from a key strategic customer, further strengthening the FD-SOI supply chain and confirming high-volume adoption,” said Christophe Maleville, executive vice president, Digital Electronics Business Unit at Soitec . “Soitec is fully prepared to support GF on its long-term plan to implement and grow 22FDX. This strategic agreement, with very significant wafer volumes, reflects GF’s strong confidence in Soitec as we build the required capacity to serve the growing FD-SOI demand.”

FD-SOI semiconductor technology has been made possible by the mutual commitment of many companies to deliver breakthroughs at both the device and substrate levels. GF and Soitec collaborate very closely to ensure landmark FD-SOI performance advantages at the right cost in developing the foundry’s FDX platforms. The FD-SOI process technologies are based on ultra-thin SOI substrates manufactured with Soitec’s industry-standard Smart Cut(TM) technology to generate ultra-thin layers with high quality and uniformity.

Offering the best power, performance, area and cost (PPAC) optimization of advanced planar technologies in smart phones, automotive electronics, and Internet of Things (IoT) applications, FD-SOI is quickly becoming a new mainstream process technology for battery powered, wireless and connected devices. This agreement will secure effective demand support for the fast growing, global ecosystem which is fueled by the successful market adoption of GF’s 22FDX technology.

Semiconductor Research Corporation (SRC), today announced that Samsung Electronics Company Ltd. (Samsung), one of the world’s largest chipmakers, has signed an agreement to join SRC’s research consortium. Samsung will participate in two SRC platforms – the New Science Team (NST) project and the Global Research Collaboration (GRC) program.

The NST project, a 5-year, $300M+ initiative commences in January 2018. NST consists of two complementary research programs: JUMP (Joint University Microelectronics Program) and nCORE (nanoelectronics Computing Research), supporting long-term research focused on high- performance, energy-efficient microelectronics for communications, computing and storage needs. Within the GRC program, comprised of nine design and process technology research disciplines, Samsung will participate in the Packaging and Logic & Memory Devices programs.

“It is an exciting time at SRC with the addition of Samsung to our premier group of semiconductor design, manufacturing, and advanced technology companies. SRC welcomes Samsung as we continue to bring together the world’s most brilliant minds to turn theories into reality,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “We now have the most innovative semiconductor companies collaborating to advance research for next-generation technology and to continue the promise of Moore’s Law economics, bringing increased performance and new product features to the consumer.”

“Collaborative research has been a key element of Samsung’s global strategy,” said Dr. HK Kang, Executive Vice President of Semiconductor Research and Development Center, Samsung Electronics. “The roadmap to future discoveries in technology is deeply rooted in the research coming from industry-sponsored university programs such as NST and GRC. We look forward to working with the SRC team to spark meaningful advancements in semiconductor technology as we explore future innovation.”

With the addition of Samsung, 7 of the top 10 global semiconductor companies are now members of SRC. Samsung represents the fifth non-U.S. headquartered company to join SRC within the last 18+ months.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has received three TSMC Partner of the Year awards at this year’s TSMC Open Innovation Platform (OIP) Ecosystem Forum. Cadence was presented with awards for the joint development of the 7nm FinFET Plus design infrastructure and the 12nm FinFET Compact (12FFC) design infrastructure and the joint delivery of the automotive design enablement platform.

The awards for the joint development of the 7nm FinFET Plus design infrastructure and 12FFC design infrastructure were awarded based on the early, in-depth collaboration between TSMC and Cadence on FinFET technology enablement and the development of the latest advanced-node solutions for next-generation system-on-chip (SoC) designs. Cadence secured the award for the joint delivery of the automotive design enablement platform based on collaboration and support of aging simulation and advanced electromagnetic (EM) rules for the 16FFC process.

“Cadence continues to partner with TSMC to deliver the innovation and deep technical expertise that is required to address evolving requirements for the latest process nodes, such as 7nm FinFET Plus and 12FFC, and within growth industries, such as automotive,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “These awards from TSMC highlight Cadence’s dedication to delivering the innovative tools that our customers need for advanced SoC and automotive designs.”

“Throughout the history of our long, collaborative relationship with Cadence, they have consistently delivered high-quality results and continue to invest in the most advanced technologies as demonstrated by the latest developments in 7nm FinFET Plus, 12FFC and automotive design enablement,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “The awards are indicative of our close collaboration with Cadence, and we look forward to continuing the development of advanced-node solutions for our mutual customers.”

GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications.

GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design.

“GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.”

“This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.”

GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs.

SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com.

The International Microelectronics And Packaging Society (IMAPS) will celebrate the 50th anniversary of its flagship technical conference – the IMAPS Symposium – from October 9 – 12, 2017, as microelectronics engineers and scientists gather at the Raleigh Convention Center near Research Triangle Park, North Carolina, USA to take part in the electronics industry’s largest technical conference dedicated to advanced microelectronics packaging technology. Researchers and exhibitors will showcase their work during a comprehensive conference program of technical papers, panels, special sessions, short courses/tutorials, and an exhibition that will spotlight premier work in the fields of microelectronics, semiconductor packaging and circuit design.

The 50th International Symposium on Microelectronics is an international technology forum for the presentation of applied research on microelectronics, consisting of more than 180 papers presented by researchers from corporations, universities and government labs worldwide, with five technical tracks: Chip Packaging Interactions; High Performance, Reliability, & Security; Advanced Packaging & Enabling Technologies; Advanced Packaging & System Integration; and Advanced Materials & Processes.

Keynote Presentations Lead Off the IMAPS Technical Program on Tuesday, October 10
Four keynote addresses from leading industry experts include:

“Packaging Challenges for the Next Generation of Mobile Devices,” by Ahmer Syed, Senior director of package engineering, Qualcomm Technologies

“Packaging without the Package – A More Holistic Moore’s Law,” by Subramanian (Subu) S. Iyer, distinguished chancellor’s professor in the Charles P. Reames Endowed Chair of the Electrical Engineering Department at the University of California at Los Angeles (UCLA) and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS)

“Electronics Outside the Box: Building a Manufacturing Ecosystem for Flexible Hybrid Electronics,” by Benjamin Leever, senior materials engineer, Air Force Research Laboratory (AFRL) Soft Matter Materials Branch

“Transforming Electronic Interconnect,” by Tim Olson, founder & CTO, Deca Technologies

International Panel Session & Wine Reception on Wednesday, October 11
A panel session on “Global Perspectives on Packaging Requirements & Trends Towards 2025” will be moderated by Jan Vardaman, TechSearch International and Gabriel Pares, CEA-Leti. Panelist will include representatives from Asia (Yasumitsu Orii, NAGASE Group and Ton Schless, SIBCO), Europe (Steffen Kroehnert, Nanium and Eric Bridot, SAFRAN), and North America (David Jandzinski, Qorvo). The 90-minute panel session includes a wine reception.

Diversity Roundtable & Networking Discussions on Monday, October 9
Following the opening reception, IMAPS leaders will conduct a series of roundtable discussions designed to inspire conversations about overcoming diversity barriers, the strengths inherent in a diverse workforce, identifying and collaborating with a mentor, and more.

Posters & Pizza Session on Thursday, October 12
One of the fastest-growing segments of the IMAPS conference is the popular “Posters & Pizza” session held outside the exhibit hall, giving attendees the opportunity to interact one-on-one with presenters in a more informal setting.

Professional Development Courses (Short Courses & Tutorials) on Monday, October 9
Preceding the IMAPS Symposium technical program is a full day of professional development opportunities, presented as a series of 2-hour sessions in four tracks: Intro to Microelectronics Packaging; Next Generation Packaging Challenges; Baseline & Emerging Technologies; and Reliability. These short courses represent a unique opportunity, only available through IMAPS, for participants to personally interact with the instructors, and with each other in small groups from 10 – 30 people, led by industry experts in the field with ample time for questions and networking.

Student Opportunities at IMAPS
As part of its ongoing mission IMAPS invites students to participate in an informal networking event on Tuesday, October 10 with IMAPS industry leaders over lunch in the exhibit hall, giving them an chance to learn about career opportunities, navigating the hiring process, and other topics. In addition, the IMAPS Microelectronics Foundation sponsors a student paper competitionin conjunction with the Symposium that awards more than $3,500 in scholarships for outstanding student papers.

Social Events & an Introduction to the RTP/Raleigh Area’s Technology Community
In addition to the technical program, a variety of social events are planned around the IMAPS Symposia, including the Annual David C. Virissimo Memorial Fall Golf Classic, a charity golf outing scheduled for Monday, October 9 at NCSU’s Lonnie Poole Golf Course. Proceeds from the event benefit the IMAPS Microelectronics Foundation.

Monday evening’s welcome reception will feature NC-themed entertainment from a local bluegrass band, and participants will also be able to view historical photos and other memorabilia spanning 50 years of IMAPS history.

There is also a scheduled tour of the nearby Micross Advanced Interconnect Technology (AIT) facility, one of the premier wafer bumping and wafer level packaging facilities in the U.S., with more than 20 years experience providing leading edge interconnect and 3D integration technologies (TSV, Si interposers, 3D IC) to worldwide customers.

New to the Symposium this year is a unique opportunity for IMAPS attendees to experience the vibrant technology community in the greater RTP/Raleigh area. IMAPS has invited local non-profit organizations that comprise the area’s rapidly-growing technology ecosystem to participate in a special area adjacent to the exhibit hall during the day of October 10, providing an opportunity for IMAPS Symposium attendees to network and interact.

To register for the IMAPS 50th International Symposium on Microelectronics, please visit the online registration site for more information, or contact Brianne Lamm, IMAPS Marketing & Events Manager, at [email protected] or 980-299-9873.