Category Archives: Wafer Processing

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it is delivering a comprehensive automotive IP portfolio for the TSMC 16nm FinFET Compact (16FFC) automotive process technology. This broad IP portfolio enables a host of applications ranging from in-vehicle infotainment, in-cabin electronics, vision subsystems, digital noise reduction and advanced driver assistance system (ADAS) subsystems and is registered in the TSMC9000A program.

The comprehensive IP portfolio incorporates the key IP needed to implement advanced infotainment and ADAS systems on chip (SoCs), and includes the Cadence flagship 4266-speed grade LPDDR4/4X DDR PHY and controllers and PCI Express® 4.0/3.0 (PCIe®4/3) PHY and controllers. This is complemented by subsystems supporting MIPI® D-PHYSM, USB3.1/USB2.0, DisplayPort, Octal SPI/QSPI, UFS and Gigabit Ethernet with TSN.

In order to support cost-effective automotive SoC designs, Cadence IP is area- and power-optimized for the AEC-Q100 Grade 2 temperature range, eliminating the need to carry Grade 1 power and area penalties into cost-sensitive automotive SoC designs. Cadence IP is designed to be ASIL-B ready and ASIL-C/D capable based on end users’ safety goals and safety requirements as outlined in the ISO 26262 standard.

“Renesas has been the world leader in providing automotive computing SoCs for a long time,” said Masahiro Suzuki, vice president of the Automotive Solutions Business Unit, Renesas Electronics Corporation. “We are seeing increased adoption of advanced MCUs in automobiles to accelerate autonomous driving, connected cars and electric vehicles. To address these trends in a timely manner, we have been working with Cadence on the development of physical IP using cutting-edge process nodes. Cadence has delivered advanced solutions for LPDDR4/4X PHY that support the highest LPDDR4 memory speed available in the market.”

“Cadence automotive subsystem solutions have been designed from the ground up to meet the stringent requirements of automotive OEMs and tier 1 suppliers,” said Babu Mandava, Cadence’s senior vice president and general manager, IP Group. “Additionally, Cadence IP is performance optimized for the advanced SoC designs for in-vehicle infotainment and ADAS applications. Through our continued collaboration with TSMC, we’re making it very simple for automotive designers to use the most advanced IP solutions to deliver innovative products to market quickly with confidence that they are compliant with the industry’s latest safety and reliability standards.”

“Cadence has quickly adapted its IP portfolio to support automotive applications for our 16FFC process, enabling accelerated design-ins with major automotive suppliers,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Our ongoing collaboration with Cadence has resulted in a robust, comprehensive set of IP that enables today’s complex automotive designs for ADAS applications and infotainment systems.”

Kulicke & Soffa Industries, Inc. (NASDAQ: KLIC) (“Kulicke & Soffa”, “K&S” or the “Company”) announced today its collaboration agreement with Kinik Company, to provide comprehensive dicing blades solutions.

This sales and distribution agreement enhances both organizations’ complementary product offerings within select markets. Kulicke & Soffa’s electro-plated dicing blades target silicon wafer and non-metalized package singulation, while Kinik’s molded dicing blades focus on metalized packages and hard-material substrate singulation applications. This initial collaboration partnership establishes a foundation for more meaningful joint development opportunities in the future.

“This is a perfect match for K&S and Kinik to provide customers with a complementary portfolio of dicing blades products,” said Eugene Tan, Kulicke & Soffa’s Senior Director of Capillary and Blade Business Lines. “We look forward to enhancing this partnership in the future.”

William Lee, Kinik’s General Manager and Head of Diamond Business Unit said, “This collaboration is an important step in our commitment to better support our customers. Together, with our aligned market-driven strategy, we will provide a broad range of competitive dicing blades solutions to customers.”

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC’s embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC’s debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.

The DesignShare concept enables an entirely new range of applications. Companies like SiFive, UltraSoC and other ecosystem partners have developed efficient, pre-integrated solutions to lower the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization. The partnership between SiFive, originator of the industry’s first open-source chip platform, and UltraSoC, the industry leader in vendor-neutral on-chip debug and analytics tools, significantly strengthens the ecosystem surrounding RISC-V, the open source processor specification which is often dubbed “the Linux of the semiconductor industry.”

“SiFive was founded with the mission to disrupt the semiconductor industry by leveling the playing field for anyone who wants to develop custom silicon,” said Naveed Sherwani, CEO of SiFive. “The DesignShare ecosystem enables aspiring system designers with the tools they need when designing their SoC. We’re thrilled to welcome UltraSoC to the DesignShare ecosystem and look forward to seeing the innovations our collaboration brings to the market.”

UltraSoC’s IP simplifies the development of systems on chip (SoCs) and provides embedded analytics features that enable chip makers to cut development costs significantly and increase the profitability of their projects. The company has taken a leading role in producing a specification for RISC-V processor trace functionality, which UltraSoC and SiFive intend to work together with the RISC-V Foundation to incorporate fully into the RISC-V standard. Trace is a fundamental requirement for developers working with any processor architecture, allowing engineers to view the behavior of their programs in detail, isolating bugs and identifying areas for improvement. UltraSoC and SiFive IP fully supports this recently released trace specification.

“UltraSoC is committed to increasing the number of silicon design starts, and our participation in DesignShare with SiFive is a natural extension of that work,” said Rupert Baines, CEO of UltraSoC. “We are committed to driving the acceleration of the democratization of the semiconductor industry, both through our membership in the RISC-V Foundation and via individual partnerships like this one with SiFive. Making UltraSoC’s IP available through the DesignShare model will enable chipmakers everywhere to leverage the benefits of open source hardware and introduces new innovative designs to the market.”

Rick O’Connor, executive director of the RISC-V Foundation, commented: “The idea behind the open source movement is that one doesn’t have to design everything from scratch. The idea behind DesignShare is to help speed the development of new silicon designs by reducing the barriers of cost, process and integration that have traditionally held back innovation in the semiconductor industry. SiFive, UltraSoC and the other companies that are making their IP available through DesignShare are fundamentally enabling this revolution in an otherwise stagnant industry.”

SiFive was founded by the inventors of RISC-V – Andrew Waterman, Yunsup Lee and Krste Asanovic – with a mission to democratize access to custom silicon. In its first six months of availability, more than 1,000 HiFive1 software development boards have been purchased and delivered to developers in over 40 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products, started shipping the industry’s first RISC-V SoC in November 2016 and announced the availability of its Coreplex RISC-V based IP earlier this month. SiFive’s innovative “study, evaluate, buy” licensing model dramatically simplifies the IP licensing process, and removes traditional road blocks that have limited access to customized, leading edge silicon.

UltraSoC allows designers to create an on-chip infrastructure that non-intrusively monitors a chip’s behavior – both hardware and software. In development, engineers can use this IP to gain an intimate understanding of the interactions between on-chip processor blocks, custom logic, and system software. The company joined the RISC-V Foundation in 2016, with a mission to provide the RISC-V community with secure, independent on-chip development and debug capabilities; earlier in 2017 it offered its RISC-V processor trace specification for adoption by the RISC-V Foundation as part of the open source specification.

Microsemi Corporation (Nasdaq: MSCC), a provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the appointment of Richard M. Beyer to its board of directors.

Beyer was chairman and CEO of Freescale Semiconductor from 2008 through June 2012. Prior to Freescale, he served as president, CEO and director of Intersil Corporation from 2002 to 2008. He has also previously served in executive management roles at Elantec Semiconductor, FVC.com, VLSI Technology Inc. and National Semiconductor Corporation. Beyer currently serves as chairman of the board at Dialog Semiconductor PLC and sits on the board at Micron Technology Inc. In addition, he served three years as an officer in the United States Marine Corps.

Researchers examining the flow of electricity through semiconductors have uncovered another reason these materials seem to lose their ability to carry a charge as they become more densely “doped.” Their results, which may help engineers design faster semiconductors in the future, are published online in the journal ACS Nano.

Semiconductors are found in just about every piece of modern electronics, from computers to televisions to your cell phone. They fall somewhere between metals, which conduct electricity very well, and insulators like glass that don’t conduct electricity at all. This moderate conduction property is what allows semiconductors to perform as switches and transistors in electronics.

The most common material for semiconductors is silicon, which is mined from the earth and then refined and purified. But pure silicon doesn’t conduct electricity, so the material is purposely and precisely adulterated by the addition of other substances known as dopants. Boron and phosphorus ions are common dopants added to silicon-based semiconductors that allow them to conduct electricity.

But the amount of dopant added to a semiconductor matters – too little dopant and the semiconductor won’t be able to conduct electricity. Too much dopant and the semiconductor becomes more like a non-conductive insulator.

“There’s a sweet spot when it comes to doping where the right amount allows for the efficient conduction of electricity, but after a certain point, adding more dopants slows down the flow,” says Preston Snee, associate professor of chemistry at the University of Illinois at Chicago and corresponding author on the paper.

“For a long time scientists thought that the reason efficient conduction of electricity dropped off with the addition of more dopants was because these dopants caused the flowing electrons to be deflected away, but we found that there’s also another way too many dopants impede the flow of electricity.”

Snee, UIC chemistry student Asra Hassan, and their colleagues wanted to get a closer look at what happens when electricity flows through a semiconductor.

Using the Advanced Photon Source Argonne National Laboratory, they were able to capture X-ray images of what happens at the atomic level inside a semiconductor. They used tiny chips of cadmium sulfide for their semiconductor “base” and doped them with copper ions. Instead of wiring the tiny chips for electricity, they generated a flow of electrons through the semiconductors by shooting them with a powerful blue laser beam. At the same time, they took very high energy X-ray photos of the semiconductors at millionths of a microsecond apart – which showed what was happening at the atomic level in real time as electrons flowed through the doped semiconductors.

They found that when electrons were flowing through, the copper ions transiently formed bonds with the cadmium sulfate semiconductor base, which is detrimental to conduction.

“This has never been seen before,” said Hassan. “Electrons are still bouncing off dopants, which we knew already, but we now know of this other process that contributes to impeding flow of electricity in over-doped semiconductors.”

The bonding of the dopant ions to the semiconductor base material “causes the current to get stuck at the dopants, which we don’t want in our electronics, especially if we want them to be fast and efficient,” she said. “However, now that we know this is happening inside the material, we can design smarter systems that minimize this effect, which we call ‘charge carrier modulation of dopant bonding’.”

By Dave Anderson, president, SEMI Americas

The SEMI Strategic Materials Conference (SMC) is the industry’s premier event devoted to technology and business drivers of materials in the electronics supply chain. Slated for September 18-20 in San Jose, Calif., the 18th annual SMC “offers a unique chance to network and discover opportunities in and around the industry in a year where dramatic growth has returned to the semiconductor market,” observes SMC 2017 co-chair Mark Thirsk of Linx Consulting, who will provide opening remarks at the conference.

SMC features three distinguished keynote speakers: AMD’s CTO, Mark Papermaster, will discuss “The Future of Semiconductors: Moore’s Law Plus.”  Next, Lam Research’s CTO, Dave Hemker, will present “The Next Level: Is it Time for Equipment and Materials Suppliers to Collaborate More?” describing how the current market environment is having a rippling effect across the supply chain. “As the continuation of Moore’s Law becomes ever-more challenging, closer, earlier collaboration between materials suppliers, equipment makers, and semiconductor manufacturers becomes necessary,” says Hemker.   SMIC’s Sunny Hui, senior VP of Marketing, will kick off day two telling the audience how to “Collaborate to Win in China.”

The first day’s agenda features “Economic and Market Trends: The Consolidation Game (M&A), China, 200mm & More,” with speakers from Applied Materials, Credit Suisse, Linx Consulting, and SEMI China.

Detailing Heterogeneous Integration for Performance and Scaling, UCLA’s Subramanian S. Iyer will describe how adapting silicon-inspired processing, integration, and materials to advanced packaging constructs may be the key to perpetuating Moore’s Law.

The Future of Materials Market in China will focus on the state of China’s semiconductor materials industry, government policies, growth opportunities for suppliers, and best practices for companies operating in this expanding environment.  Hear from Dow Chemical, Konfoong Materials International (KFMI) and SMIC.

More than twenty program sessions will explore the developments driving industry growth and enabling innovative new materials for today’s evolving electronics industry. The conference agenda also includes:

  • Process Challenges at 5nm & Beyond: Insights from ARM, Samsung, and TSMC.
  • Universities − Innovation Drivers: Viewpoints from Stanford University, University of California Berkeley, and University of Chicago.
  • Materials Supply Chain Challenges in Adjacent Industries: Perspectives from Linde Group, PARC (Xerox), and Pixelligent Technologies
  • Heterogeneous Integration − Design to New Materials & Packaging: Insights from ASE Group, imec, and UCLA

SMC 2017 will close with an Executive Panel discussion addressing emerging material challenges for each participant’s company and the segment within which it operates. Executives from Intel, Tokyo Electron, TSMC and Versum Materials will share their views on how the industry can collectively address challenges through focused R&D investment, collaboration throughout the vertical supply chain, and the application of innovative business strategies to ensure a win-win for all companies across the extended supply chain.

I hope to see you at the SEMI Strategic Materials Conference this month. Learn more and register here.

Note: The SEMI Strategic Material Conference (SMC) is organized by the Chemical and Gas Manufacturers Group, a SEMI not-for-profit Special Interest Group comprised of leading manufacturers, producers, packagers, and distributors of chemicals and gases used in the electronics industry.

 

By Ajit Manocha, president and CEO, SEMI

In my first six months at SEMI, I’ve visited with many member companies and industry leaders.  One theme I hear repeatedly is a concern about our most fundamental source of innovation and productivity – people.

Our industry has a significant need for additional workers and several trends are working against us.

For one, only 11 percent of elementary students in the U.S. indicate an interest in science, technology, engineering, and mathematics (STEM) education according to the National Science Foundation.  In other regions, recruiting and retaining high-skilled workers remains a constant challenge.

Ironically, the incredible electronics manufacturing technology that we create has enabled many of the new-tech industries in software, social media, internet services and applications that now directly compete for the best and brightest technical talent.  Young engineers have other choices and many are lured to newer growth industries with familiar internet brands.

Today, due to continued industry advancement and robust growth, capital equipment companies, device makers and materials companies collectively have thousands to tens-of-thousands of open unfilled positions. Furthermore, the representation of women in the high-tech workplace remains disproportionately low.

We have long been aware of the need to support a diverse pipeline for high-skilled workers.  In 2001, the SEMI Foundation was established to encourage STEM education and stimulate interest in high-tech careers. SEMI and its Foundation launched the High-Tech U (HTU) program to engage and excite high school students. HTU enlists industry volunteers to work with local high school students in a three-day interactive hands-on curriculum. Young people get a fun and inspirational exposure to binary logic, circuit making, a fab or electronics manufacturing setting and other aspects of professional development.

To date, we’ve delivered 216 HTU programs and reached nearly 7,000 students in 12 states and nine countries.  The results are compelling.  Our 2016 survey of HTU alumni shows that they enter college at five times the national rates and 70 percent that graduated college are employed in a STEM field.   By any measure, the initiative is successful and worthwhile.

However, the talent problem statement has grown. Industry needs are greater and the time has come to redouble our effort to attract and retain talent for our high-skilled manufacturing sector.  Therefore, SEMI is elevating workforce development as a top strategic priority.

The SEMI HTU team is already engaged with key member companies to develop our enhanced roadmap for workforce development including a comprehensive study with Deloitte Consulting to underpin the key problems and solutions in areas of focus for decisive and systematic SEMI action.

Belle Wei, SEMI Foundation Board member and the Carolyn Guidry Chair in Engineering Education and Innovative Learning at San Jose State University said, “It is critical that we work to prepare the future workforce.  This requires a high level of collaboration between industry and higher education.  We appreciate SEMI’s leadership role in this collaboration to further develop the workforce pipeline.”

We have launched a HTU Certified Partner Program (CPP) with the goal of reaching more students through industry partners who commit to long-term participation and independent delivery of High Tech U.  In addition, we are expanding outreach to universities and community colleges and preparing to launch an industry image campaign to better tell the remarkable story of opportunity in our industry.

The capacity to innovate and the skills to manage complex design, engineering and manufacturing processes are essential factors that sustains our high-tech industry – and they are dependent on people.

Finally, as mentioned above, we have already started some new initiatives to enhance our HTU. A SEMI workforce development roadmap and execution plan will be detailed in a future SEMI Global Update article following the upcoming SEMI International Board Meeting.  SEMI welcomes any inputs in addition to your continued support.

This endeavor is increasingly urgent and recruiting the industry’s future innovators is well-aligned with SEMI’s mantra to connect, collaborate, innovate, grow and prosper.

Advanced Semiconductor Engineering, Inc (TAIEX: 2311, NYSE: ASX), a semiconductor assembly and test service provider, announced that its K7 manufacturing facility in Kaohsiung has received the Green Factory Label from the Industrial Development Bureau, Ministry of Economic Affairs, Taiwan. K7 is the sixth factory following K3, K5, K11, K12 and K15, at the ASE Kaohsiung Nantze campus to receive the label.

ASE is fully committed to corporate sustainability through actions that produce tangible results and meet our goal of co-existence with the environment. In 2009, ASE Kaohsiung green building plans were drawn up to combine nature with technology, and provide a green factory environment optimized for living, productivity and the ecology. The ASE K7 building has incorporated green innovation, eco-friendly designs, energy and water conservation, waste reduction, low carbon and various environmental benchmarks to achieve the green factory label.

‘Sustainability has always been at the core of ASE’s corporate philosophy,’ said KC Chou, senior vice president, ASE. ‘In 2014, ASE Kaohsiung implemented the EEWH-RN system and adopted ‘clean production’. Beginning with sustainable product design and production, green management, social responsibility to innovation; these four facets helped reduce resource consumption, reduce waste, lower impacts to the environment and other improvements that aim to strike a balance between economic and environmental sustainability. Our Kaohsiung facilities are constantly challenged to establish energy reduction goals and each department regularly proposes diverse programs to lower carbon footprints. This year, K7 is also working towards achieving the EEWH-RN diamond grade. At ASE, we will continuously raise the bar on our sustainability performance,’ he concluded.

About ASE Sustainability Actions and Results

ASE K7

  • Green innovation. The use of DI water to replace acetic acid reduced the usage of organic acid by 14,400 liters.
  • Green material usage. The use of boron-free developing agent reduced boron-containing agent usage by 1,830 liters and boron-containing liquid waste by 2,015 metric tons per year. The use of lead-free solder paste reduced usage of lead paste by 1,500 kg per year.
  • Energy efficient manufacturing process. Improvements made to the adsorption dryer reduced energy usage by 278,495 kWh per year.
  • Water efficiency. The use of chamber piping to control water flow resulted in water savings of 314.52 tons per year. Employing UF and RO systems further reduced wastewater discharge volume by 15,600 tons.
  • Lower carbon emissions. Converting the fixed frequency of chilled water pumps and cooling water pumps to variable frequency enabled us to reduce 625 tons of CO2 equivalent per year. Energy efficiency lights are installed throughout the factory premises, further reducing 793 tons of CO2 equivalent per year.
  • Waste reduction. Establishing a central chemical delivery system helped reduce the use of 1,208 chemical barrels per year. We also reduced photoresist coating usage by 14,400 liters per year. Gold and copper reuse amounted to 474.45 kg per year. Wafer cassette reuse amounted to 39,795 pieces per year.

Building certifications as of August 31, 2017

  • LEED rating：Kaohsiung K12, K21, K22, K23, K26；Chung Li Buildings K and L；Shanghai Headquarters
  • EEWH rating：Kaohsiung K3, K4, K5, K7, K11, K12, K14B(water recycling facility), K15, K16, K21, K26；Chung Li Building A
  • Green Factory Label：Kaohsiung K3, K5, K7, K11, K12, K15
  • In progress: The construction of our new K24 building in Kaohsiung has taken into consideration of ‘low carbon footprint building’ methodologies from the transportation of materials, equipment, type of material used, renovation, dismantling and the entire building’s life cycle.

BY PETE SINGER, Editor-in-Chief

At a SEMICON West press conference, SEMI released its Mid-year Forecast. Worldwide sales of new semiconductor manufacturing equipment are projected to increase 19.8 percent to total $49.4 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the market high of $47.7 billion set in 2000. In 2018, 7.7 percent growth is expected, resulting in another record-breaking year—totaling $53.2 billion for the global semiconductor equipment market.

“It’s really an exciting time for the industry in the terms of technology, the growth in information and data and that’s all going to require semiconductors to enable that growth,” said Dan Tracy, senior director, IR&S at SEMI.

The average of various analysts forecast the semiconductor industry in general 12% growth for the year. “It’s a very good growth year for the industry,” Tracy said. “In January, the consensus was about 5% growth for the year and with the improvement in the market and the firmer pricing for memory we see an increase in the outlook for the market.”

The SEMI Mid-year Forecast predicts wafer processing equipment is anticipated to increase 21.7 percent in 2017 to total $39.8 billion. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, will increase 25.6 percent to total $2.3 billion. The assembly and packaging equipment segment is projected to grow by 12.8 percent to $3.4 billion in 2017 while semiconductor test equipment is forecast to increase by 6.4 percent, to a total of $3.9 billion this year.

“Based on the May outlook, we are looking at a record year in terms of tracking equipment spending. This is for new equipment, used equipment, and spending related to the facility that installed the equipment. It will be about a $49 billion market this year. Next year, it’s going to grow to $54 billion, so we have two years in a row of back to back record spending,” Tracy said.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 68.7 percent, followed by Europe at 58.6 percent, and North America at 16.3 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 61.4 percent, to a total of $11.0 billion, following 5.9 percent growth in 2017. In 2018, South Korea, Taiwan, and China are forecast to remain the top three markets, with South Korea maintaining the top spot to total $13.4 billion. China is forecasted to become the second largest market at $11.0 billion, while equipment sales to Taiwan are expected to reach $10.9 billion.

Over the last two years, Waterloo based Siborg Systems Inc. teamed up with Sensor Creations Inc. from Camarillo, California in development of a practical tool for simulation of the process flow and optical sensor performance.

The companies collaborated in both the semiconductor process and device simulation for optical sensor structures. They have large sizes and require many fabrication steps such as epitaxial growth, implantation, deposition, etching, annealing and oxidation. Due to the large size, use of conventional simulation tools lead to high CPU time. In contrast, MicroTec was able to run a typical process simulation within a few minutes on a regular PC.

Doping profile for 3-junction optical sensor simulated with MicroTec. For 100,000 required CPU time was about 2 minutes on regular PC. (PRNewsfoto/Siborg Systems Inc.)

Doping profile for 3-junction optical sensor simulated with MicroTec. For 100,000 required CPU time was about 2 minutes on regular PC. (PRNewsfoto/Siborg Systems Inc.)

MicroTec provides steady-state two-dimensional semiconductor device simulation that is not sufficient for capacitance extraction. A new method was developed allowing to calculate capacitance of a semiconductor structure by solving equation for the total current conservation. The method is equally applicable to 1D, 2D and 3D structures but limited to low frequencies and low-leakage conditions. The most straightforward method is solving the equation of the total current conservation, mutual capacitances may be calculated simply by the formula C=Idt/dV.

This formula could be improved by using a relation involving resistances as well as capacitances. In order to do that, one more data point is required. Although this expression is more accurate than the first one, it is still not equivalent to the actual compact model of the semiconductor structure because, strictly speaking, it is a set of interconnected transmission lines and therefore any simplification of the equivalent circuit results in a loss of accuracy. The current based method is not very accurate and requires simulation with a properly selected ramp speed. If it is too fast, voltage drop due to Ohm’s law distorts the capacitance, and if it is too slow, displacement current becomes too small and is swamped by the numerical noise. Practically this method has a limited application due to high sensitivity to the ramp time.

In contrast to the current method, the charge method provides charges affiliated with the contacts rather than the currents, thus eliminating the problem of result interpretation using equivalent R-C circuit. To calculate the charges we solve the same equation but instead of calculating currents, we use the response to the excitation applied to a contact as a weight function when integrating the charge in the structure. The charges are easily calculated by a convolution of the “affiliation” function with the carrier density. This method appeared very stable and accurate and was successfully used for capacitance calculation in optical sensors.

The picture below shows the capacitance calculated by the charge based method at various ramp speeds. Note that all 4 curves virtually coincide. The method applicability is questionable when significant minority charge is injected as in the case of forward biased junctions. The proposed method has a wider range of applicability but the extent of its accuracy still needs to be studied.

“We used Two-dimensional Semiconductor Process and Device Simulation Software MicroTec from Siborg intensively for the last couple of years. We found it very useful in our practical optical sensor prototype development. It significantly outperforms other available commercial tools by the speed, ease-of-use and robustness. Last, but not least, the license cost is significantly lower as well,” says Stefan Lauxtermann from Sensor Creations.

MicroTec is a TCAD tool that has been used by major semiconductor manufacturers such as Hitachi, Texas Instruments, Matasushita, etc. As an educational tool, MicroTec and three-dimensional SibLin are simple and easy to learn.