Category Archives: Wafer Processing

The ConFab – an exclusive conference and networking event for semiconductor manufacturing and design executives from leading device makers, OEMs, OSATs, fabs, suppliers and fabless/design companies – announces the 2018 event will be held at THE COSMOPOLITAN of LAS VEGAS on May 20-23.

Pete Singer, Conference Chair of The ConFab and Editor-in-Chief of Solid State Technology had this to say, “The ConFab is a unique combination of business, technology and social interactions that make this industry gathering of influencers and leaders so valuable. In 2018, we will take a close look at the new applications driving the semiconductor industry, the technology that will be required at the device and process level to meet new demands, and – perhaps most importantly – the kind of strategic collaboration that will be required.” He also stated, “the key to continued business success for both guests and presenters will be the crucial insights that will be gained at the conference about critical market trends; and how to take advantage of emerging opportunities. Our goal is to “connect the dots” and how what’s going on in the end semiconductor application space (IoT, AI, 5G, VR, automotive, etc.) will ultimately impact semiconductor manufacturing and design.”

Keynotes, panel discussions and technical sessions on new technology needed in manufacturing will be a focal point of The ConFab 2018. Topics include: EUV, now entering volume production and ushering in a new era of patterning for the 7 and 5nm generations. And the many new materials being considered, transistors that are evolving from FinFETs to gate-all-around nanowires, on chip communication with silicon photonics emerging, and advanced packaging/heterogeneous integration as ever more critical. How semiconductors are playing an increasingly important role in the healthcare industry, will also be in the robust 2018 agenda.

The ConFab is a high-level, 3 1/2 day conference for decision-makers and influencers to connect, innovate and collaborate in multiple sessions, one-on-one private business meetings, and other daily networking activities. For more information, visit www.theconfab.com.

Two-dimensional materials are a sort of a rookie phenom in the scientific community. They are atomically thin and can exhibit radically different electronic and light-based properties than their thicker, more conventional forms, so researchers are flocking to this fledgling field to find ways to tap these exotic traits.

Applications for 2-D materials range from microchip components to superthin and flexible solar panels and display screens, among a growing list of possible uses. But because their fundamental structure is inherently tiny, they can be tricky to manufacture and measure, and to match with other materials. So while 2-D materials R&D is on the rise, there are still many unknowns about how to isolate, enhance, and manipulate their most desirable qualities.

Now, a science team at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) has precisely measured some previously obscured properties of moly sulfide, a 2-D semiconducting material also known as molybdenum disulfide or MoS2. The team also revealed a powerful tuning mechanism and an interrelationship between its electronic and optical, or light-related, properties.

To best incorporate such monolayer materials into electronic devices, engineers want to know the “band gap,” which is the minimum energy level it takes to jolt electrons away from the atoms they are coupled to, so that they flow freely through the material as electric current flows through a copper wire. Supplying sufficient energy to the electrons by absorbing light, for example, converts the material into an electrically conducting state.

As reported in the Aug. 25 issue of Physical Review Letters, researchers measured the band gap for a monolayer of moly sulfide, which has proved difficult to accurately predict theoretically, and found it to be about 30 percent higher than expected based on previous experiments. They also quantified how the band gap changes with electron density – a phenomenon known as “band gap renormalization.”

“The most critical significance of this work was in finding the band gap,” said Kaiyuan Yao, a graduate student researcher at Berkeley Lab and the University of California, Berkeley, who served as the lead author of the research paper.

“That provides very important guidance to all of the optoelectronic device engineers. They need to know what the band gap is” in orderly to properly connect the 2-D material with other materials and components in a device, Yao said.

Obtaining the direct band gap measurement is challenged by the so-called “exciton effect” in 2-D materials that is produced by a strong pairing between electrons and electron “holes” ¬- vacant positions around an atom where an electron can exist. The strength of this effect can mask measurements of the band gap.

Nicholas Borys, a project scientist at Berkeley Lab’s Molecular Foundry who also participated in the study, said the study also resolves how to tune optical and electronic properties in a 2-D material.

“The real power of our technique, and an important milestone for the physics community, is to discern between these optical and electronic properties,” Borys said.

The team used several tools at the Molecular Foundry, a facility that is open to the scientific community and specializes in the creation and exploration of nanoscale materials.

The Molecular Foundry technique that researchers adapted for use in studying monolayer moly sulfide, known as photoluminescence excitation (PLE) spectroscopy, promises to bring new applications for the material within reach, such as ultrasensitive biosensors and tinier transistors, and also shows promise for similarly pinpointing and manipulating properties in other 2-D materials, researchers said.

The research team measured both the exciton and band gap signals, and then detangled these separate signals. Scientists observed how light was absorbed by electrons in the moly sulfide sample as they adjusted the density of electrons crammed into the sample by changing the electrical voltage on a layer of charged silicon that sat below the moly sulfide monolayer.

Researchers noticed a slight “bump” in their measurements that they realized was a direct measurement of the band gap, and through a slew of other experiments used their discovery to study how the band gap was readily tunable by simply adjusting the density of electrons in the material.

“The large degree of tunability really opens people’s eyes,” said P. James Schuck, who was director of the Imaging and Manipulation of Nanostructures facility at the Molecular Foundry during this study.

“And because we could see both the band gap’s edge and the excitons simultaneously, we could understand each independently and also understand the relationship between them,” said Schuck, now at Columbia University. “It turns out all of these properties are dependent on one another.”

Moly sulfide, Schuck also noted, is “extremely sensitive to its local environment,” which makes it a prime candidate for use in a range of sensors. Because it is highly sensitive to both optical and electronic effects, it could translate incoming light into electronic signals and vice versa.

Schuck said the team hopes to use a suite of techniques at the Molecular Foundry to create other types of monolayer materials and samples of stacked 2-D layers, and to obtain definitive band gap measurements for these, too. “It turns out no one yet knows the band gaps for some of these other materials,” he said.

The team also has expertise in the use of a nanoscale probe to map the electronic behavior across a given sample.

Borys added, “We certainly hope this work seeds further studies on other 2-D semiconductor systems.”

The Molecular Foundry is a DOE Office of Science User Facility that provides free access to state-of-the-art equipment and multidisciplinary expertise in nanoscale science to visiting scientists.

Researchers from the Kavli Energy NanoSciences Institute at UC Berkeley and Berkeley Lab, and from Arizona State University also participated in this study, which was supported by the National Science Foundation.

North America-based manufacturers of semiconductor equipment posted $2.27 billion in billings worldwide in July 2017 (three-month average basis), according to the July Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in July 2017 was $2.27 billion. The billings figure is 1.4 percent lower than the final June 2017 level of $2.30 billion, and is 32.8 percent higher than the July 2016 billings level of $1.71 billion.

“We observed softening in the equipment billings in July following the strong surge in the first half of the year,” said Ajit Manocha, president and CEO of SEMI. “However, overall, equipment billings remain significantly up year-over-year, with 2017 on-track to be a record spending year.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)
Year-Over-Year
February 2017
$1,974.0
63.9%
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017
$2,270.5
41.8%
June 2017 (final)
$2,300.3
34.1%
July 2017 (prelim)
$2,268.4
32.8%

Source: SEMI (www.semi.org), August 2017

LTX-Credence shipped the 600th PAx test system to Skyworks Solutions, Inc., an innovator of high performance analog semiconductors connecting people, places and things. The PAx platform has been specifically designed to address the high volume manufacturing test challenges of suppliers of advanced front end RF devices such as Multiband RF Power amplifiers, RF Front End Modules, RF Analog System in Package and RF discrete devices. The PAx platform is shipped in two main configurations, PAx and PAx-ac, which are deployed at most IDM, Fabless and OSAT companies specializing in the high volume manufacturing and test of these types of devices.

“Our goal with the PAx platform was to offer semiconductor manufacturers of RF front end devices an alternative to deploying their own in house test systems.” Steve Wigley, Vice President of the semiconductor tester group of Xcerra, commented: “Our approach was to leverage LTX-Credence RF manufacturing test technology and use our systems expertise to package it in a compact footprint to offer the required levels of performance, fast test times and operational availability. The shipment of the 600th of these test systems demonstrates the value of this approach, and has established the PAx platform as the clear market leader for testing RF front end applications with an estimated market share greater than 70%”.

IC Insights has revised its outlook for semiconductor industry capital spending and presented its new findings in the August Update to The McClean Report 2017.  IC Insights’ latest forecast is for semiconductor industry capital spending to climb 20% this year.

Figure 1 shows the steep upward trend of quarterly capital spending in the semiconductor industry since 1Q16. Although there was a slight pause in the upward trajectory in 1Q17, 2Q17 set a new record for quarterly spending outlays.   Moreover, 1H17 semiconductor industry spending was 48% greater than in 1H16.  IC Insights believes that whether industry-wide capital spending in the second half of 2017 can match the first half of the year is greatly dependent upon the level of Samsung’s 2H17 spending outlays.

Not only has Samsung Semiconductor been on a tear with regard to its semiconductor sales, surging into the number one ranking in 2Q17, but the company has also been on a tremendous capital spending spree for its semiconductor division this year.  As depicted in Figure 2, Samsung spent a whopping $11.0 billion in capital outlays for its semiconductor group in 1H17, more than 3x greater than the company spent in 1H16 and only $300 million less than the company spent in all of 2016!   In fact, Samsung’s capital expenditures in 1H17 represented 25% of the total semiconductor industry capital spending and 28% of the outlays in 2Q17.

While the company has publicly reported that it spent $11.0 billion in capital outlays for its semiconductor division in 1H17 (a $22.0 billion annual run-rate), Samsung has been very secretive about revealing its full-year 2017 budget for its semiconductor group (it might be afraid of shocking the industry with such a big number!).  In 2012, the year of Samsung’s previous first half spending surge before 1H17, the company cut its second half capital outlays by more than 50%, from $8.5 billion in 1H12 to $3.7 billion in 2H12.  Will the company follow the same pattern in 2017?  At this point, it is impossible to tell.  IC Insights believes that Samsung’s full-year 2017 capital expenditures could range from $15.0 billion to $22.0 billion!

Figure 1

Figure 1

If Samsung spends $22.0 billion in capital outlays this year, total semiconductor industry capital spending could reach $85.4 billion, which would represent a 27% increase over the $67.3 billion the industry spent in 2016.

It is interesting to note that two of the major spenders, TSMC and Intel, are expected to move in opposite directions with regard to their 2H17 capital spending plans. TSMC spent about $6.8 billion in capital outlays in 1H17. If it sticks to its $10.0 billion budget this year, which it reiterated in its second quarter results, it would only spend about $3.2 billion in 2H17, less than half its outlays in 1H17. In contrast, Intel spent only about $4.7 billion in 1H17, leaving the company to spend about $7.3 billion in 2H17 in order to reach its stated full-year 2017 spending budget of $12.0 billion.

Figure 2

Figure 2

TowerJazz, the global specialty foundry, and Tacoma Technology Ltd and Tacoma (Nanjing) Semiconductor Technology Co., Ltd (collectively known as “Tacoma”) announced today that Tower has received a first payment of $18 million net, rendering phase one of the framework agreement with Tacoma binding. This agreement maps the establishment of a new 8-inch semiconductor fabrication facility in Nanjing, China. According to the terms of the framework agreement, TowerJazz will provide technological expertise together with operational and integration consultation, for which the Company shall receive additional payments based on milestones during the next few years, subject to a definitive agreement specifying all terms and conditions.

In addition, from the start of production at the facility, TowerJazz will be entitled to capacity allocation of up to 50% of the targeted 40,000 wafer per month fab capacity, which it may decide to use at its discretion. This capacity will provide TowerJazz with additional manufacturing capability and flexibility to address its growing global demand.

Tacoma will be responsible to source funds for all activities, milestones and deliverables of the entire project, including the construction, commissioning and ramp of this facility, with the project being fully supported by Nanjing Economic and Technology Development Zone through its Administration Committee, Credito Capital as well as through potential funding from other third party investors and entities.

“This agreement with Tacoma is in line with our business strategy to focus on growing markets such as China. The fabless business in China has grown rapidly in the past years. The new 8-inch fabrication facility in Nanjing will provide us with a strategic footprint in China and the opportunity to extend our offerings in advanced specialty process technologies by enabling customers in China to optimize their product performance and time to market,” said Dr. Itzhak Edrei, TowerJazz President.

Russell Ellwanger, TowerJazz Chief Executive Officer, commented, “We are exploring multiple opportunities in China, and determined this agreement with Tacoma to be a good fit for TowerJazz, providing a roadmap for a meaningful long-term strategic partnership. China’s focus to develop its domestic semiconductor industry with full infrastructure presents additional opportunities for TowerJazz, as a global analog leader, to expand our served markets and geographic presence. This partnership will enable us to further fulfill our customers’ needs through additional available capacity as well as to be an active player in the growing Chinese market.”

Joseph Lee, Tacoma Chairman, stated: “Deeply engraved in the corporate culture of both Tacoma and TowerJazz is the core belief in working ‘SMART’ with ‘PASSION.’ Our people are committed to contributing to our business partners, the global semiconductor industry and society with the best endeavor and integrity. Tacoma will fully fund this project together with Credito Capital and other entities. This venture will become a dominant player in Asia and will raise the standard in the semiconductor industry to another level.”

A groundbreaking and signing ceremony took place in Nanjing, China, attended by TowerJazz Chairman Mr. Amir Elstein, President Dr. Itzhak Edrei, Business Development Vice President Mr. Erez Imberman, as well as the then Israeli Ambassador to China the Honorable Mr. Matan Vilnai. Pictured, the signing between Tacoma Chairman, Mr. Joseph Lee and TowerJazz CEO Mr. Russell Ellwanger, with among others the above cited attendees.

The SEMI Foundation today announced that it will be celebrating its 10th anniversary of partnership with New York State United Teachers (NYSUT) on August 22-23 in Latham, New York at the NYSUT headquarters.  The Foundation and NYSUT will culminate a two-day SEMI High Tech U program for teachers on Wednesday, August 23rd with a reception recognizing industry instructors from Applied Materials and KLA-Tencor for leadership in volunteerism and STEM education.

The SEMI Foundation’s acclaimed STEM program, SEMI High Tech U – Teacher Edition has reached more than 600 teachers in upstate New York since 2007.  The two-day teacher program provides industry led, hands-on activities and curriculum that teachers can take back to the classroom in addition to unique opportunities to network with high-tech industry professionals.  Teachers-turned-students also tour the College of Nanoscale Science and Engineering for a first-hand look at how relevant STEM skills are utilized in a high-tech workplace.  This fall, the teachers’ new knowledge will be passed along to their students in the classroom. A retrospective survey of past SEMI High Tech U teacher participants showed that 95 percent of teachers who attend SEMI High Tech U – Teacher Edition gain an increased understanding of the relevance of STEM skills in today’s workplace.

This year’s program at NYSUT is supported by Applied Materials, GLOBALFOUNDRIES and KLA-Tencor.

Leslie Tugman, executive director of the SEMI Foundation, states, “NYSUT is a premier model of how education and industry partnerships can work together for the benefit of all in their region.  Through NYSUT’s High Tech U programs for teachers, we have exponentially reached thousands of students to help fill the high-tech talent pipeline.”

All SEMI High Tech U modules are taught by industry professionals and two legacy volunteer instructors, Vincent Villaume of Applied Materials and Jeff Barnum of KLA-Tencor, will be honored at a reception at NYSUT on August 23.

The “Global Gallium Arsenide (GaAs) Wafers Market 2017-2021” report has been added to Research and Markets’ offering.

The global gallium arsenide wafer market to decline at a CAGR of 11.9% during the period 2017-2021.

The report, Global Gallium Arsenide Wafer Market 2017-2021, has been prepared based on an in-depth market analysis with inputs from industry experts. The report covers the market landscape and its growth prospects over the coming years. The report also includes a discussion of the key vendors operating in this market.

The latest trend gaining momentum in the market is shutdown of 2G network. High-speed Internet has now become readily available worldwide. The data speed of a 4G connection is 10 times faster 3G data speed. This high-speed connectivity results in faster browsing, uninterrupted streaming of videos, and improved GPS performance. Thus, countries are now focusing on the adoption of 3G or 4G connectivity and shutting down 2G network spectrums.

According to the report, one of the major drivers for this market is the increasing adoption of smartphones. Shipments of smartphones will reach 2.16 billion units by 2021, which is a significant increase from around 1.6 billion units in 2016. The major driving factor responsible for this growth is the rising smartphone penetration in countries with high population density such as China, India, and Brazil. The growth in the shipment volume of smartphones will drive the demand for GaAs wafers used in mobile handsets, particularly for mobile power amplifiers.

Chipmakers want every part of the wafer to produce, or yield, good die. Advances in process technologies over the years have just about made this a reality, even as feature dimensions continue to shrink and devices grow ever more complex. Now, the last frontier is improving yields at the edge of the wafer – the outer 10 mm or so – where chemical, physical, and even thermal discontinuities are simply much harder to control. Complicating matters, current strategies used to manage these edge issues involve tradeoffs between yield and manufacturing costs that result in less than ideal fab economics. At Lam, our technologists have been working on solutions to this challenge, and today, we released the new Corvus™ edge control technology for our Kiyo® conductor etch products to address these very issues and enhance edge yield.

Edge Challenges

Taking a closer look at the wafer’s edge, where up to ~10% of the die may be located, there are several issues at play that can impact yield. In all plasma etch reactors, the abrupt end of the wafer surface creates inherent electrical discontinuities at the edge region, forming voltage gradients that bend the plasma sheath. This, in turn, changes the direction of the plasma’s components (ions and neutrals), which impacts etch results and causes unwanted variability. In the case of 3D NAND devices, for example, this change in the plasma conditions at the wafer’s edge can cause tilted etch profiles or prevent features from being completely etched. In addition to affecting tilt angle, these edge effects can result in non-uniform critical dimensions (CDs) or changes in local overlay metrics.

LAMResearch1

Another challenge is that process drift creates CD uniformity and selectivity problems over time. As a way to manage this, chipmakers often add more chamber wet cleans to restore the equipment to a standard condition. However, this approach significantly reduces productivity because the chamber is not available for processing wafers during this maintenance. In addition, as process margins get tighter, more frequent wet cleans are required, which increases operational costs.

Corvus Solution

Lam’s new Corvus technology provides a novel capability to smooth out extreme edge discontinuities and enhance edge performance. It offers the ability to tune the plasma sheath at the edge to produce a constant, user-defined etch rate and ion angle. For example, etch rate can be tuned to be faster or slower at the edge relative to the rate over the rest of the wafer. With 3D NAND applications, Corvus technology has demonstrated the ability to minimize plasma sheath drift, preventing detrimental feature tilting at the wafer’s edge. Tuning to within 1.5 mm of the edge, the new technology can correct for inherent process variation in the edge region as well as for incoming film variations to optimize die yield. Furthermore, with Corvus, every wafer sees the same edge conditions for optimal yield, eliminating previously seen systematic wafer-to-wafer yield variability.

Corvus technology not only improves across-wafer uniformity, it also greatly reduces wafer-to-wafer and chamber-to-chamber variability and eliminates the historical tradeoffs among yield, operational flexibility, and cost. Customers have reported die yield improvements of 0.5-2% per wafer, which can be a significant advantage – especially when you consider how many thousands of wafers chipmakers process every day. Additionally, Corvus has demonstrated the ability to provide higher and more consistent yield over a longer period. It also greatly enhances productivity and lowers overall fab operating costs for high-volume manufacturing by requiring fewer chamber wet cleans. The new technology is being used for advanced patterning, mask open, and other challenging conductor etch applications where reducing variation in CD, profile, or selectivity and improving productivity helps enable continued scaling.

The new capability provided by Corvus complements Lam’s Hydra® technology, which enables fine tuning of within-wafer uniformity and actively compensates for incoming variation. Together, these advanced process control technologies are reducing variability across the entire wafer surface, improving yield, and enabling the production of next-generation logic and memory devices.

Welch Foundation, the Army Research Office and the National Science Foundation supported the research.

The next generation of feature-filled and energy-efficient electronics will require computer chips just a few atoms thick. For all its positive attributes, trusty silicon can’t take us to these ultrathin extremes.

Now, electrical engineers at Stanford have identified two semiconductors – hafnium diselenide and zirconium diselenide – that share or even exceed some of silicon’s desirable traits, starting with the fact that all three materials can “rust.”

“It’s a bit like rust, but a very desirable rust,” said Eric Pop, an associate professor of electrical engineering, who co-authored with post-doctoral scholar Michal Mleczko a paper that appears in the journal Science Advances.

The new materials can also be shrunk to functional circuits just three atoms thick and they require less energy than silicon circuits. Although still experimental, the researchers said the materials could be a step toward the kinds of thinner, more energy-efficient chips demanded by devices of the future.

Silicon’s Strengths

Silicon has several qualities that have led it to become the bedrock of electronics, Pop explained. One is that it is blessed with a very good “native” insulator, silicon dioxide or, in plain English, silicon rust. Exposing silicon to oxygen during manufacturing gives chip-makers an easy way to isolate their circuitry. Other semiconductors do not “rust” into good insulators when exposed to oxygen, so they must be layered with additional insulators, a step that introduces engineering challenges. Both of the diselenides the Stanford group tested formed this elusive, yet high-quality insulating rust layer when exposed to oxygen.

Not only do both ultrathin semiconductors rust, they do so in a way that is even more desirable than silicon. They form what are called “high-K” insulators, which enable lower power operation than is possible with silicon and its silicon oxide insulator.

As the Stanford researchers started shrinking the diselenides to atomic thinness, they realized that these ultrathin semiconductors share another of silicon’s secret advantages: the energy needed to switch transistors on – a critical step in computing, called the band gap – is in a just-right range. Too low and the circuits leak and become unreliable. Too high and the chip takes too much energy to operate and becomes inefficient. Both materials were in the same optimal range as silicon.

All this and the diselenides can also be fashioned into circuits just three atoms thick, or about two-thirds of a nanometer, something silicon cannot do.

“Engineers have been unable to make silicon transistors thinner than about five nanometers, before the material properties begin to change in undesirable ways,” Pop said.

The combination of thinner circuits and desirable high-K insulation means that these ultrathin semiconductors could be made into transistors 10 times smaller than anything possible with silicon today.

“Silicon won’t go away. But for consumers this could mean much longer battery life and much more complex functionality if these semiconductors can be integrated with silicon,” Pop said.

More to do

There is much work ahead. First, Mleczko and Pop must refine the electrical contacts between transistors on their ultrathin diselenide circuits. “These connections have always proved a challenge for any new semiconductor, and the difficulty becomes greater as we shrink circuits to the atomic scale,” Mleczko said.

They are also working to better control the oxidized insulators to ensure they remain as thin and stable as possible. Last, but not least, only when these things are in order will they begin to integrate with other materials and then to scale up to working wafers, complex circuits and, eventually, complete systems.

“There’s more research to do, but a new path to thinner, smaller circuits – and more energy-efficient electronics – is within reach,” Pop said.

Additional Stanford contributors to this research include: Chaofan Zhang, Hye Ryoung Lee, Hsueh-Hui Kuo, Blanka Magyari-Köpe, Robert G. Moore, Zhi-Xun Shen, Ian R. Fisher, and Professor Yoshio Nishi.

The work was supported by the Air Force Office of Scientific Research (AFOSR), the National Science Foundation, Stanford Initiative for Novel Materials and Processes (INMP), the Department of Energy (DOE) Office of Basic Energy Sciences, Division of Material Sciences, and an NSERC PGS-D fellowship.