Category Archives: Wafer Processing

Everspin Technologies, Inc. has begun sampling its new 1-Gigabit Spin Torque Magnetoresistive Random Access Memory (ST-MRAM) with lead customers. This product delivers a high-endurance, persistent memory with a DDR4-compatible interface. These features enable storage system vendors to enhance the reliability and performance of storage devices and systems by delivering protection against power loss without the use of supercapacitors or batteries. Enterprise SSD designers can take advantage of fast persistent memory that is inherently power fail-safe while also reducing write amplification and overprovisioning, common limitations for NAND Flash based SSDs.

The 1 Gb MRAM is produced in 28nm CMOS on 300mm wafers in partnership with GLOBALFOUNDRIES, utilizing Everspin’s patented perpendicular magnetic tunnel junction (pMTJ) technology. The rapid development of the 1Gb part is a direct result of the high degree of scalability of the pMTJ, moving from 40nm to 28nm processes in less than one year through our close partnership with Global Foundries.

“We are very excited to begin sampling our 1 Gb product,” said Phill LoPresti, Everspin’s President and CEO. “Getting our latest technology into customers’ hands so they can develop their products to take advantage of the unique capabilities of high-endurance, fast, persistent memory is a significant milestone for Everspin.”

Everspin will be demonstrating the EMD4E001G at the upcoming Flash Memory Summit in Santa Clara on August 7-10. This latest ST-MRAM product provides 4 times the capacity of Everspin’s current 256Mb DDR3 ST-MRAM and will be shown running in Everspin’s nvNITRO storage accelerator products.

 

NanoString Technologies, Inc. (Nasdaq:NSTG), a provider of life science tools for translational research and molecular diagnostic products, and Lam Research Corporation (Nasdaq:LRCX), a global supplier of wafer fabrication equipment and services to the semiconductor industry, today announced a strategic collaboration to develop NanoString’s proprietary Hyb & Seq next-generation sequencing platform.

This collaboration brings together NanoString’s proprietary sequencing chemistry and Lam’s expertise in advanced systems engineering to enable nanoscale manufacturing, with the goal of building a clinical sequencer with the simplest workflow in the industry. The objectives of the collaboration are to complete the development of the Hyb & Seq single molecule sequencing chemistry, design and engineer a clinical sequencing instrument, develop clinical assay panels, and secure the necessary regulatory approvals.  In addition, the companies intend to explore methods for coupling the sequencing chemistry with advanced semiconductor fabrication processes to optimize the performance of molecular profiling platforms.

Under the terms of the collaboration, Lam will provide up to $50 million of funding intended to cover the costs of development and regulatory approval over a development period expected to last approximately three years, as well as advanced engineering and technical support. Lam will receive a warrant to purchase one million shares of NanoString common stock at $16.75 per share, as well as a royalty on all products developed under the collaboration. NanoString retains all rights to commercialize the resulting Hyb & Seq products, and the parties will share ownership rights in jointly developed intellectual property.

“We are excited to collaborate with Lam Research, in a partnership that brings together leading innovators in our respective fields,” said Brad Gray, NanoString’s President and Chief Executive Officer. “By combining our Hyb & Seq technology with Lam’s advanced engineering expertise, we intend to fully resource the development of the industry’s simplest clinical sequencer, and enable open-ended innovation at the intersection of semiconductors and genomics.”

“Our vision is to create value from natural technology extensions, including nanoscale applications enablement, chemistry, plasma, fluidics, and advanced systems engineering,” stated Martin Anstice, Lam Research’s President and Chief Executive Officer. “We are excited to collaborate with NanoString to advance the development of their novel Hyb & Seq system and chemistry to meet the challenge of increasing our understanding of human genetics, and we envision a number of strategic benefits by aligning our complementary respective strengths. This is a compelling opportunity for the whole to be significantly greater than the sum of its parts; it is an accelerator of enablement and value for both companies.”

Worldwide semiconductor capital spending is projected to increase 10.2 percent in 2017, to $77.7 billion, according to Gartner, Inc. This growth rate is up from the previous quarter’s forecast of 1.4 percent, due to continued aggressive investment in memory and leading-edge logic which is driving spending in wafer-level equipment (see Table 1).

“Spending momentum is more concentrated in 2017 mainly due to strong manufacturing demand in memory and leading-edge logic. The NAND flash shortage was more pronounced in the first quarter of 2017 than the previous forecast, leading to over 20 percent growth of etch and chemical vapor deposition (CVD) segments in 2017 with a strong capacity ramp-up for 3D NAND,” said Takashi Ogawa, research vice president at Gartner.

According to Gartner’s latest view, the next cyclical down cycle will emerge in 2018 to 2019 in capital spending, compared with 2019 to 2020 in the previous quarter’s forecast. “Spending on wafer fab equipment will follow a similar cycle with a peak in 2018. While the most likely scenario will still keep positive growth in 2018, there is a concern that the growth will turn negative if the end-user demand in key electronics applications is weaker than expected,” said Mr. Ogawa.

Table 1: Worldwide Semiconductor Capital Spending and Equipment Spending Forecast, 2016-2020
(Millions of Dollars)

2016

2017

2018

2019

2020

Semiconductor Capital Spending

70,568.9

77,794.5

77,443.5

71,814.8

73,239.5

Growth (%)

9.1

10.2

-0.5

-7.3

2.0

Wafer Fab Equipment, Including Wafer-Level Packaging

37,033.1

43,661.0

43,690.4

40,515.8

41,342.7

Growth (%)

11.4

17.9

0.1

-7.3

2.0

Other Semiconductor Capital Spending

33,535.8

34,133.5

33,753.2

31,299.0

31,896.8

Growth (%)

6.8

1.8

-1.1

-7.2

1.9

Source: Gartner (July 2017)

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $97.9 billion during the second quarter of 2017, an increase of 5.8 percent over the previous quarter and 23.7 percent more than the second quarter of 2016. Global sales for the month of June 2017 reached $32.6 billion, an uptick of 2.0 percent over last month’s total of $32.0 billion, and a surge of 23.7 percent compared to the June 2016 total of $26.4 billion. Cumulatively, year-to-date sales during the first half of 2017 were 20.8 percent higher than they were at the same point in 2016. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry has enjoyed impressive sales growth midway through 2017, posting its highest-ever quarterly sales in Q2 and record monthly sales in June,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales into the Americas market were particularly robust in June, and all regional markets saw growth of at least 18 percent year-over-year. Conditions are favorable for continued market growth in the months ahead.”

Regionally, sales increased compared to June 2016 in the Americas (33.4 percent), China (25.5 percent), Asia Pacific/All Other (19.5 percent), Europe (18.3 percent), and Japan (18.0 percent). Sales also were up across all regions compared to last month: the Americas (5.1 percent), Europe (1.9 percent), China (1.5 percent), Japan (1.0 percent), and Asia Pacific/All Other (0.8 percent).

June 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

6.27

6.59

5.1%

Europe

3.11

3.16

1.9%

Japan

2.95

2.98

1.0%

China

10.25

10.41

1.5%

Asia Pacific/All Other

9.43

9.50

0.8%

Total

32.00

32.64

2.0%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

4.94

6.59

33.4%

Europe

2.68

3.16

18.3%

Japan

2.52

2.98

18.0%

China

8.29

10.41

25.5%

Asia Pacific/All Other

7.95

9.50

19.5%

Total

26.38

32.64

23.7%

Three-Month-Moving Average Sales

Market

Jan/Feb/Mar

Apr/May/Jun

% Change

Americas

5.96

6.59

10.5%

Europe

2.96

3.16

7.1%

Japan

2.84

2.98

4.8%

China

10.06

10.41

3.4%

Asia Pacific/All Other

9.02

9.50

5.4%

Total

30.84

32.64

5.8%

Toshiba Corporation (TOKYO:6502) today announced that Toshiba Memory Corporation (TMC), a wholly-owned subsidiary that manufactures Flash memory, will unilaterally invest in manufacturing equipment for the Fab 6 clean room at Yokkaichi Operations.

As Toshiba announced in its June 28, 2017 release, “Toshiba Memory Corporation to Invest in Manufacturing Facilities for Fab 6 at Yokkaichi Operations,” the company negotiated with SanDisk on a joint investment in the manufacturing equipment, but failed to reach agreement. Accordingly, TMC will move forward with a unilateral investment in Phase-1 of Fab 6 that will equip the clean room to handle TMC’s next-generation 96-layer BiCS FLASH memory, and allow TMC to meet demand growth in coming years.

TMC will invest approximately 195 billion yen in Fab 6 in FY2017, covering the installation of manufacturing equipment for 96-layer BiCS FLASH memory in the Phase-1 clean room, and the construction of Phase-2. TMC calculates that proceeding unilaterally with the installation of manufacturing equipment in Fab 6 will require it to increase its funding by 15 billion yen against its initial estimate. Installation is expected to begin as early as December, 2017.

Demand for TMC’s next generation BiCS memory devices is expected to increase significantly due to growing demand for enterprise SSDs in datacenters, SSDs for PCs, and memory for smartphones; TMC expects this strong market growth to continue in 2018. TMC’s investment timing will position it to capture this growth and to expand its business. TMC intends to increase the output of 3D NAND at Yokkaichi to approximately 90% of its capacity in FY2018, and will continue to make timely investments to expand operations.

This decision to move forward with a unilateral investment in Fab 6 does not impact production for the memory business, as Toshiba Memory produces the memory. Nor does it impact the various contracts related to development.

 

IC Insights has revised its outlook and analysis of the IC industry and presented its new findings in the Mid-Year Update to The McClean Report 2017, which originally was published in January 2017.  Entering the second half of the year, it is clear the IC industry is on course for a much stronger upturn than was initially forecast in January.  IC Insights now expects the IC market to increase 16% in 2017 due to exceptional growth in the DRAM and NAND flash memory markets. The DRAM market is now forecast to grow 55% and the NAND flash market is now expected to rise 35% this year—in both cases, almost entirely due to fast-rising prices rather than unit growth.  Excluding these two markets, the overall IC market growth is forecast to show just 6% year-over-year growth (Figure 1).  The expected 16% increase would be the first double-digit gain for the IC market since it expanded by 33% in 2010—the recession-recovery year—and the fifth double-digit increase for the IC market since 2000.

ic insights

As seen in the figure, the DRAM market has had a notable impact on total IC market growth in recent years. With market surges of 32% and 34% in 2013 and 2014, respectively, the DRAM market alone boosted the worldwide IC market growth rate by three percentage points in 2013 and four percentage points in 2014.

At $64.2 billion, the DRAM market is forecast to be by far the largest single product category in the IC industry in 2017, exceeding the expected second-ranked MPU market for standard PCs and servers ($47.1 billion) by $17.1 billion this year.

Overall, IC Insights’ global economic outlook remains on course with initial projections covered in The McClean Report. Electronic system production, capital spending as a percent of sales, and IC wafer capacity added were unchanged from the original outlook.  However, other factors and conditions that contribute to the forecast were upgraded slightly in the Mid-Year Update. For example, the worldwide GDP forecast was upgraded by 0.1 point to 2.7% for 2017, marginally ahead of what is considered to be the global recession threshold of 2.5% growth.  IC Insights believes that through the forecast period, annual IC market growth rates will closely track with the performance of worldwide GDP growth.

Following a fairly strong first half of growth, China’s 2017 GDP was raised to 6.8% for 2017 from the original forecast of 6.3%.  Also, IC Insights upgraded its U.S GDP forecast to 2.1% in the Mid-Year Updatefrom 2.0% in January. While the U.S. economy is far from perfect, it is currently one of the most significant positive driving forces in the worldwide economy.  A falling unemployment rate, PMI figures of 57.0 and 55.8 in the first and second quarters of this year, and relatively low oil prices should help the U.S. economy sustain its modest growth in the second half of this year. Growth rates for IC unit shipments, IC average selling price, and semiconductor capital spending were also revised slightly higher.

Additional details and commentary regarding the updated IC forecasts for the 2017-2021 timeperiod are covered in IC Insights’ Mid-Year Update to The McClean Report 2017.

A newly discovered collective rattling effect in a type of crystalline semiconductor blocks most heat transfer while preserving high electrical conductivity – a rare pairing that scientists say could reduce heat buildup in electronic devices and turbine engines, among other possible applications.

A team led by scientists at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) discovered these exotic traits in a class of materials known as halide perovskites, which are also considered promising candidates for next-generation solar panels, nanoscale lasers, electronic cooling, and electronic displays.

Rattling structures of halide perovskites: cesium tin iodide (left) and cesium lead iodide (right). Credit: UC Berkeley

Rattling structures of halide perovskites: cesium tin iodide (left) and cesium lead iodide (right). Credit: UC Berkeley

These interrelated thermal and electrical (or “thermoelectric”) properties were found in nanoscale wires of cesium tin iodide (CsSnI3). The material was observed to have one of the lowest levels of heat conductivity among materials with a continuous crystalline structure.

This so-called single-crystal material can also be more easily produced in large quantities than typical thermoelectric materials, such as silicon-germanium, researchers said.

“Its properties originate from the crystal structure itself. It’s an atomic sort of phenomenon,” said Woochul Lee, a postdoctoral researcher at Berkeley Lab who was the lead author of the study, published the week of July 31 in the Proceedings of the National Academy of Sciencesjournal. These are the first published results relating to the thermoelectric performance of this single crystal material.

Researchers earlier thought that the material’s thermal properties were the product of “caged” atoms rattling around within the material’s crystalline structure, as had been observed in some other materials. Such rattling can serve to disrupt heat transfer in a material.

“We initially thought it was atoms of cesium, a heavy element, moving around in the material,” said Peidong Yang, a senior faculty scientist at Berkeley Lab’s Materials Sciences Division who led the study.

Jeffrey Grossman, a researcher at the Massachusetts Institute of Technology, then performed some theory work and computerized simulations that helped to explain what the team had observed. Researchers also used Berkeley Lab’s Molecular Foundry, which specializes in nanoscale research, in the study.

“We believe there is essentially a rattling mechanism, not just with the cesium. It’s the overall structure that’s rattling; it’s a collective rattling,” Yang said. “The rattling mechanism is associated with the crystal structure itself,” and is not the product of a collection of tiny crystal cages. “It is group atomic motion,” he added.

Within the material’s crystal structure, the distance between atoms is shrinking and growing in a collective way that prevents heat from easily flowing through.

But because the material is composed of an orderly, single-crystal structure, electrical current can still flow through it despite this collective rattling. Picture its electrical conductivity is like a submarine traveling smoothly in calm underwater currents, while its thermal conductivity is like a sailboat tossed about in heavy seas at the surface.

Yang said two major applications for thermoelectric materials are in cooling, and in converting heat into electrical current. For this particular cesium tin iodide material, cooling applications such as a coating to help cool electronic camera sensors may be easier to achieve than heat-to-electrical conversion, he said.

A challenge is that the material is highly reactive to air and water, so it requires a protective coating or encapsulation to function in a device.

Cesium tin iodide was first discovered as a semiconductor material decades ago, and only in recent years has it been rediscovered for its other unique traits, Yang said. “It turns out to be an amazing gold mine of physical properties,” he noted.

To measure the thermal conductivity of the material, researchers bridged two islands of an anchoring material with a cesium tin iodide nanowire. The nanowire was connected at either end to micro-islands that functioned as both a heater and a thermometer. Researchers heated one of the islands and precisely measured how the nanowire transported heat to the other island.

They also performed scanning electron microscopy to precisely measure the dimensions of the nanowire. They used these dimensions to provide an exacting measure of the material’s thermal conductivity. The team repeated the experiment with several different nanowire materials and multiple nanowire samples to compare thermoelectric properties and verify the thermal conductivity measurements.

“A next step is to alloy this (cesium tin iodide) material,” Lee said. “This may improve the thermoelectric properties.”

Also, just as computer chip manufacturers implant a succession of elements into silicon wafers to improve their electronic properties – a process known as “doping” – scientists hope to use similar techniques to more fully exploit the thermoelectric traits of this semiconductor material. This is relatively unexplored territory for this class of materials, Yang said.

TECHCET CA, an advisory service firm providing electronic materials information, today announced that the silicon wafer supply for semiconductor device fabrication is forecasted to appreciably lag demand starting next year, and could remain in shortage through the year 2021 despite investments in China. Silicon wafer area demand is forecasted to steadily increase at a CAGR of ~3.1% over the 2016-2021 period to reach over 13,000 million square inches (MSI). Executives of silicon wafer suppliers have stated that average selling prices have remained too low to allow for investment in 300mm expansions, as detailed in a quarterly update to the TECHCET Critical Materials Report, “Silicon Wafers Market & Supply-Chain.”

The silicon wafer supply-chain is dominated by two suppliers–Shin-Etsu Handotai and SUMCO–combining to capture almost two-thirds of the global wafer market in 2016, and the top five representing over 92% of total revenues. The silicon wafer market is maturing as evidenced by recent mergers and acquisitions, the two most notable being the acquisition of SunEdison Semi by GlobalWafers (Taiwan) and the assumption of majority ownership of LG Siltron by SK Holdings (Korea).

“Over the last five years, the average selling price per square inch of semiconductor-grade silicon wafers has declined by about a third and more than a half from the 2007 level,” explained Michel Walden, lead author of the report and senior technology analyst with TECHCET. “However, current tightness in the supply-chain has led to greater stability and even price increases in some cases, all of which is likely needed for the long-term health of the wafer suppliers.”

Over the past few years, silicon suppliers decommissioned roughly 25% of the peak capacity for 200mm wafers. Of the remaining 200mm capacity, roughly 65% of the total demand is for epitaxial (epi) wafers, and a series of epi service companies have embraced this opportunity and provide a variety of layer configurations for their customers.

Sub-Fab Fault Detection and Classification (FDC) software platforms collect, integrate and analyze operational data.

BY ERIK COLLART, Edwards, Sanborn, NY

The ability to provide the reliable high-quality vacuum environment that most semiconductor manufacturing requires is an often and easily overlooked aspect of the whole fab process. The unexpected failure of a vacuum pump can bring significant disruption to the manufacturing process, potentially imposing a heavy penalty in lost productivity and scrapped product. The sub-fab, where vacuum and abatement systems are typically located and so named because it is located literally below the fab floor, has evolved dramatically over the years, from simply a location outside the fab in which to house supporting equipment, to an environment that is in many ways as sophisticated as the fab itself. Just as manufacturers have adopted advanced monitoring and data analytics to optimize fab operations, they are finding significant benefit in applying the same techniques to sub-fab operations. Sub-Fab Fault Detection and Classification (FDC) software platforms such as Edcentra, Edwards’ newest equipment monitoring, data acquisition and analytics platform collect, integrate and analyze operational data from the sub-fab, providing a comprehensive solution to vacuum security.

The challenge of cost-effective innovation

The semiconductor industry faces many challenges, including the high pace of innovation and the need to constantly improve operational efficiencies, decrease costs, reduce adverse environmental impact and ensure the safety of personnel in the fab and residents of the surrounding community. Some of the ways these challenges have been met in the past no longer apply. For instance, although there is still device scaling in new technology nodes, the type of simple geometric device scaling driven by Constant-Field Scaling rules [1] – to drive innovation, improve efficiency and reduce costs per die – effectively ran out a decade ago.

Innovation has continued, though along very different lines, introducing ever more complex device architectures and increasing the use of exotic materials and manufacturing methods, such as epitaxial and atomic layer deposition. These innovations have all extended development time and time-to-market, driven up cost, reduced efficiency (lower yields, more frequent equipment preventive maintenance cycles) and brought new and higher environmental restrictions (stringent local, national and international regulations, as on CO2 emissions) and safety challenges (toxic precursor materials and waste products). Delivering timely and cost-effective innovation is now a major issue for the semiconductor industry. In response to this challenge, manufacturers have recognized the strategic necessity of integrating and analyzing all the information available from their processes. These manufacturers are therefore starting to adopt an integrated fab data and information management approach that accounts for all the factors affecting time-to-market at the lowest possible costs. The sub-fab and associated support systems cannot be omitted from this approach.

The importance of vacuum

Most of the critical steps in a chip manufacturing process are conducted under high vacuum conditions and vacuum quality is one of the most important parameters in these process step. Vacuum quality is a combination of vacuum level and vacuum content. No vacuum is absolute, and there are always trace amounts of non-process gases present in process chambers that can have a major impact on the process, if not controlled.

As any fab equipment or process engineer will tell you, maintaining vacuum quality is so important that pumps are almost never shut off and process chambers are almost never brought to atmospheric pressure, even when idle for long periods of time. Maintenance activities on process chambers are performed, whenever possible, with minimal or no exposure to atmosphere. This is for a very good reason: once a chamber has been vented to atmosphere it may take a very long time to return it to the previous known-good-vacuum state, affecting equipment uptime and process yield.

The vacuum state can therefore affect wafer quality and overall fab costs through its effect on yield or through losses incurred as a result of unplanned vacuum failures during wafer processing. For example, insufficient vacuum levels or trace amounts (ppm level) of unintended gases, such as O2 or H2O, in an ion implant process can greatly reduce the stability of high voltage power supplies, leading, in turn, to fluctuations in ion beam current, non-uniform implant conditions on the wafer, and ultimately to poor and non-reproducible wafer yields. A pump “crash” during a batch process that causes the scrap of an entire production batch–normally 125 wafers–is very costly in both direct product loss and process downtime. Even in single wafer process, unplanned pump failure can cause significant losses as some process tools require days or weeks to requalify.

Fab managers face a difficult choice between the costs of vacuum failure and the costs of too frequent maintenance. Optimizing this choice is one area where sub-fab equipment monitoring and advanced analytics can make an important contribution. Most effective optimization occurs in an adaptive maintenance regime, where pump maintenance is performed in parallel to tool mainte- nance, thereby virtually eliminating vacuum pumps as a cause of lost tool time. Long prediction horizons are required for successful adaptive maintenance, enabling the longer PM intervals (months) typical of sub-fab equipment to be synchronised to the shorter PM intervals (weeks) of the fab process equipment. For this to happen, and thereby assuring sustained vacuum quality, additional types of sensors and improved predictive capabilities and time horizons will be needed. The remainder of this paper highlights Edwards’ exploratory work on using mechanical vibration sensor data to obtain a reliable and long prediction horizon for mechanical failure modes [2].

Failure prediction using vibrational sensor data

Monitoring vibrations to assess the health of rotating machines has a long and successful history. Intrinsic bearings frequencies can be calculated from rotation speeds, and wear-generated perturbations to these frequencies can be detected to predict bearing failures and other mechanical failure modes. However, these existing methods do not translate well to a semicon- ductor environment where process-induced failure modes are more frequent. The sub-fab working environment also tends to be extremely noisy from a vibration spectrum perspective and the effects of process induced failure modes on standard vibration spectra are largely unknown.

We have developed a new method of unlocking key predictive information (Fault Detection or FD) from vibration data, based on a “fingerprinting” technique, which translates complex, noisy data into a single dynamic coefficient that can be compared easily with existing predictive maintenance parameters. Further vibrational sub-band analysis provides specific failure mode identifi- cation and root-cause analysis, thus providing a key fault classification (FC) capability. This method will be referred to as Vibration Indicator or VI from here on.

Results

FIGURE 1 shows an example of the power of VI to extend visibility of a catastrophic bearing failure in a fab working environment. A departure of VI from zero indicates the emerging signature of mechanical bearings wear. The time horizon in this example is at least 60 days, providing extended visibility and increased process security.

A second fab-based production environment example, taken from an LP-CVD Si3N4 batch deposition process and shown in FIGURE 2, illustrates the sensitivity and predictive power of VI compared to traditional pump parameters: power and temperature. The ultimate cause of failure in this case was deposition-related. As can be seen, from day 60 onward changing process conditions caused a step-change in the temperature. The power curve develops patterns of spike behavior around day 120. Previously existing best-known-methods (BKM) for predictive maintenance, based on analysis of power and temperature data, can detect this emerging behavior using spike- area and frequency-based techniques, in this case with a time horizon of 40 days. The key obser- vation in this example is that VI (blue curve) reacted immediately to an increased deposition of condensable materials, which led directly to an equipment failure 90 days later. The VI provided a time-to- failure horizon of 90 days (55% of observed pump life), more than double that of traditional parameters.

Accelerated lab testing provides further evidence of the extended time horizon VI affords. FIGURE 3 shows the results of a lab-based accelerated fluorine (F2) corrosion induced mechanical failure mode, with large F2 gas flows injected into the vacuum system and pump. The traditional power parameter is completely insensitive to the F2 flow and resulting corrosion. The VI, by contrast, shows a linear correlation with total accumulated flow, providing both early detection and a measure of the severity of the developing problem.

Screen Shot 2017-07-28 at 2.28.21 PM

A second lab-based test (not shown) investigated the effects of oil contaminants and again confirmed the ability of VI to detect and quantify failure modes inaccessible to established methods. As in the corrosion example, a linear correlation was found between accumulated contamination and VI, while power measurements proved to be completely insen- sitive to oil contamination levels.

These show that VI can significantly extend the time horizon of equipment failure modes, well beyond current predictive capabilities and into the regime where effective maintenance pooling and the resultant cost savings can be realized. Moreover, these results can be translated into precise RUL predictions using various parameter estimator techniques, complementing standard Weibull techniques. FIGURE 4 shows the results of an accelerated bearings failure lab test for a dry pump, comparing VI and estimated RUL.

Screen Shot 2017-07-28 at 2.28.33 PMScreen Shot 2017-07-28 at 2.28.38 PM

Performance comparison

Tables 1 and 2 compare and contrast VI performance with mainstream SPC-like control methods, such a single parameter threshold monitoring and multi-variate analysis (BKMS-F), in terms of detection capability, sensitivity, prediction time horizon and hit rate vs. false positives. Table 1 shows that VI considerably extends prediction time horizon and, based on data gathered to date for detectable results, has demon- strated a 100 percent hit rate with no false positives. From table 2 we see that VI extends predictability to mechanical failures, has high sensitivity, and detects problems as soon as they begin.

Screen Shot 2017-07-28 at 2.28.45 PM

Summary and conclusions

The need for increased operational efficiency in semiconductor manufacturing is driving the development of smarter interconnected vacuum sub-systems and the adoption of integrated data and information management technologies. A case study described the combined use of the EdCentra sub-fab information management system and an innovative approach to vibrational analysis. Compared to current mainstream methods, VI provided an extended, and in some cases unique, predictive maintenance capability for mechanical pump failures and a very high level of sensitivity. For the data gathered so far on detectable faults, the hit rate has been 100 percent, with no false positives. Finally, advanced analytics and VI consid- erably extended the prediction time horizon from weeks to months. Together with existing predictive algorithms and methodologies for pumps, abatement and ancillary equipment, the capabilities provided by advanced information management and innovative monitoring technologies like VI have the potential to significantly reduce costs and increase productivity.

Acknowledgements

The author would like to acknowledge and thank Antonio Serapligia and Angelo Maiorana for their ground-breaking work on vibrational analysis, and David Hacker and Alan Ifould for their inputs on the challenges and opportunities of sub-fab equipment maintenance and many fruitful discussions.

References

1. Dennard, Robert H.; Gaensslen, Fritz; Yu, Hwa-Nien; Rideout, Leo; Bassous, Ernest; LeBlanc, Andre (October 1974). “Design of ion-implanted MOSFET’s with very small physical dimensions” (PDF). IEEE Journal of Solid State Circuits. SC–9 (5).
2. Antonio Serapiglia, David Hacker, Erik J Collart, Alan Ifould, and Angelo Maiorana 28th Advanced Process Control Conference Proceedings, Mesa, Arizona, 2016

North America-based manufacturers of semiconductor equipment posted $2.29 billion in billings worldwide in June 2017 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in June 2017 was $2.29 billion. The billings figure is 0.8 percent higher than the final May 2017 level of $2.27 billion, and is 33.4 percent higher than the June 2016 billings level of $1.72 billion.

“Through the first half of the year, 2017 equipment billings are 50 percent above the same period last year,” said Dan Tracy, senior director, Industry Research & Statistics, SEMI.  “While month-to-month growth is slowing, 2017 will be a remarkable growth year for the semiconductor capital equipment industry.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)
Year-Over-Year
January 2017
$1,859.4
52.3%
February 2017
$1,974.0
63.9%
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017 (final)
$2,270.5
41.8%
June 2017 (prelim)
$2,288.9
33.4%

Source: SEMI (www.semi.org), July 2017
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.