Category Archives: Wafer Processing

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released at the end of July), IC Insights forecasts that the 2017 global electronic systems market will grow by only 2% to $1,493 billion while the worldwide semiconductor market is expected to surge by 15% this year to $419.1 billion. Moreover, IC Insights forecasts that the total semiconductor market will exceed $500.0 billion four years from now in 2021.  If the 2017 forecasts come to fruition, the average semiconductor content in an electronic system will reach 28.1%, an all-time record (Figure 1).

Figure 1

Figure 1

Historically, the driving force behind the higher average annual growth rate of the semiconductor industry as compared to the electronic systems market is the increasing value or content of semiconductors used in electronic systems.  With global unit shipments of cellphones (0%), automobiles (2%), and PCs (-2%) forecast to be weak in 2017, the disparity between the slow growth in the electronic systems market and high growth of the semiconductor market is directly due to the increasing content of semiconductors in electronic systems.

While the trend of increasing semiconductor content has been evident for the past 30 years, the big jump in the average semiconductor content in electronic systems in 2017 is expected to be primarily due to the huge surge in DRAM and NAND flash ASPs and below average electronic system sales growth this year. After dipping slightly to 28.6% in 2020, the semiconductor content figure is expected to climb to 28.9% in 2021, an average yearly gain over the 2016-2021 timeperiod of about 0.8 percentage points.

Of course, the trend of increasingly higher semiconductor value in electronic systems has a limit. Extrapolating an annual increase in the percent semiconductor figure indefinitely would, at some point in the future, result in the semiconductor content of an electronic system reaching 100%.  Whatever the ultimate ceiling is, once it is reached, the average annual growth for the semiconductor industry will closely track that of the electronic systems market (i.e., about 4% per year).  In IC Insights’ opinion, the “ceiling” is at least 30% but will not be reached within the forecast period.

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ IC market forecast data for 2017-2021.

ASM International introduced the Intrepid® ESTM 300mm epitaxy (epi) tool for advanced-node CMOS logic and memory high-volume production applications. Intrepid ES introduces innovative closed loop reactor control technology that enables optimal within wafer and wafer-to-wafer process performance, critical for today’s advanced transistors and memories. Furthermore, Intrepid ES reduces the cost per wafer significantly for a 7nm epi process compared with prior node processes. The new tool has been qualified for production at a leading-edge foundry customer, and is targeting production applications in other industry segments as well. To date, over 40 reactors have been delivered.

“Over the past several years, multiple customers have been very clear that there is a need to address several technical and cost challenges in the epi market,” said Chuck del Prado, President and Chief Executive Officer of ASM International. “Intrepid ES is the result of a focused development program to address major challenges in this market, including film non-uniformity, process repeatability, tool uptime and high cost per wafer. This early success of the Intrepid ES clearly demonstrates that we are on track in addressing our customers’ emerging epi requirements.”

The new Intrepid ES tool is based on a combination of reactor and platform design improvements. It demonstrates improved film performance and enhanced reactor stability. Fundamental to its technology is an isothermal reactor environment in which the wafer is processed. This provides consistent and repeatable temperature control across the wafer and wafer-to-wafer.

By Pete Singer

Semiconductor manufacturers use a variety of high global warming potential (GWP) gases to process wafers and to rapidly clean chemical vapor deposition (CVD) tool chambers. Processes use high GWP fluorinated compounds including perfluorocarbons (e.g., CF4, C2F6 and C3F8), hydrofluorocarbons (CHF3, CH3F and CH2F2), nitrogen trifluoride (NF3) and sulfur hexafluoride (SF6). Semiconductor manufacturing processes also use fluorinated heat transfer fluids and nitrous oxide (N2O).

Of these, the semiconductor industry naturally tends to focus its attention on CF4 since it is one of the worst offenders, with an atmospheric half-life of 50,000 years. “CF4 the hardest to get rid of and it’s one of the worst global warming gases,” said Kate Wilson, VP Marketing, Subfab Solutions – Semiconductor Division of Edwards. “We tend to use that as an indicator of how much of the other global warming gases, as well, are being emitted by the industry. If we’re dealing with that (CF4) well, we tend to be managing the rest of the gases pretty effectively.”

According to the Environmental Protection Agency (EPA), estimating fluorinated GHG emissions from semiconductor manufacture is complicated and has required a significant and coordinated effort by the industry and governments. It was historically assumed that the majority of these chemicals were consumed or transformed in the manufacturing process. It is now known that under normal operating conditions, anywhere between 10 to 80 percent of the fluorinated GHGs pass through the manufacturing tool chambers unreacted and are released into the air.

In addition, fluorinated GHG emissions vary depending on a number of factors, including gas used, type/brand of equipment used, company-specific process parameters, number of fluorinated GHG-using steps in a production process, generation of fluorinated GHG by-product chemicals, and whether appropriate abatement equipment has been installed. Companies’ product types, manufacturing processes and emissions also vary widely across semiconductor fabs.

The good news is that many companies in the semiconductor manufacturing industry have successfully identified, evaluated and implemented a variety of technologies that protect the climate and improved production efficiencies. Solutions have been investigated and successfully implemented in the following key technological areas:

  • Process improvements/source reduction
  • Alternative chemicals
  • Capture and beneficial reuse
  • Destruction technologies (known as abatement)

In 2011 the industry set new targets for 2020, which it summarizes as:

  • The implementation of best practices for new semiconductor fabs. The industry expects that the implementation of best practices will result in a normalized emission rate (NER) in 2020 of 0.22 kgCO2e/cm2, which is a 30 percent NER reduction from the 2010 aggregated baseline.
  • The addition of “Rest of World” fabs (fabs located outside the World Semiconductor Council (WSC) regions that are operated by a company from a WSC association) in reporting of emissions and the implementation of best practices for new fabs.
  • NER based measurement in kilograms of carbon equivalents per area of silicon wafers processed (kgCO2e/cm2), which will be the single WSC goal at the global level.

“We’re finding as we get down to the lower levels and different things come up as the highest priority in the fab where we’re moving into more and more lower usage processes, which are requiring abatement now in order to get those levels down to meet the targets of 2020 in the industry,” Wilson explained.

The main area for potential improvement now is etch, especially in older 200mm fabs where etch processes may not have been fitted with PFC abatement devices. This is particularly true for etch processes making extensive use of CF4. “The area where we still have the most gaps is clearly etch,” Wilson said. In CVD processes, most of the benefit was done by material shifts rather than actual abatement, although we clearly do need to abate the other gases in those processes. For the etch side, there are still quite a few customers that really only do the toxic emission abatement rather than the global warming gas emission abatement. But we do see, across almost all of our customer base, people have either fairly recently moved to fully abating all the PFC type gases or will be shortly.”

Wilson said some other gases have been coming up more recently in terms of things like N2O, which people are putting more focus on now as it’s becoming a larger part of the fab footprint of global warming materials.

For PFC abatement, Edwards offers the Atlas range of products, which destroys PFCs by burning them. This is followed by a wet scrub of the byproducts. This works quite well, but Wilson cautions that in can be tricky for some processes, such as chamber cleans with NF3. “If the burn is not correct and you get too hot, there’s actually the potential to create PFC’s. And so, it is quite critical to have well-controlled burn technology to make sure that you don’t actually cause issues where we didn’t have them before.”

Wilson said another area where they have seen some issues with PFCs being created is with processing of carbon-doped materials, such as low-k dielectrics. “When they do the chamber clean, they’re cleaning off predominately silicon dioxide but there’s carbon in there so that can create PFCs and CF4 as well so there’s a requirement to look at abatement in those areas,” she said.

Another piece of good news is that no company in the supply chain is waiting for legislation to be enacted before they act themselves. “Right from consumers to the consumer manufacturers, the car manufacturers, consumer electric manufacturers, our direct customers, the equipment manufacturers plus the major players within semiconductor and flat panel display, it seems that at every level there’s a commitment that this is the right thing to do,” Wilson said. “At every level people are pushing to get the requirements more stringent and it’s almost not about legislation anymore, it’s about everybody actually thinks it’s a good idea and they want to do it.”

Across all process areas in the fab effective abatement technologies reduce the GHG emissions significantly. The reductions per process area are shown in the diagram.

Across all process areas in the fab effective abatement technologies reduce the GHG emissions significantly. The reductions per process area are shown in the diagram.

When it comes to defects and contamination in the semiconductor manufacturing industry, most people tend to think of small, sub-nm defects at the transistor level. As important as those are, there are plenty of things that can go wrong and be seen at the macro level. Scratches, fingerprints, hot spots, spin defects, edge chips, poly haze, missing patterns, etc. are usually visible with the naked eye, perhaps aided by a green light or a microscope.

Fabs often do manual visual inspections, but it tends to be fairly random, only sampling a few wafers at a time. “You put some wafers on the screen, and you look sporadically at five, ten points on a few of the wafers,” notes Reiner Fenske, founder, CEO and president of Microtronic (Hawthorne, NY). “If you find something, typically it’s very difficult to feed that information forward. You might take a picture, but then where does that picture go?” It’s also difficult to compare defects, such as scratches, with previously seen defects. “How many scratches did you have last week? Does that scratch look like the one that you had last night?” Reiner asks.

An automated macro inspection tool – such as the newly released Microtronic EAGLEview 5, which will be running wafers at North Hall Booth #5467 at Semicon West this week — solves those problems, without requiring any recipes and quickly scanning every wafer in the cassette, noting and logging various defects. The EAGLEview 5 represents a big upgrade over the company’s previous offering. “There’s really a dramatic difference in terms of defect detection, defect resolution, defect sensitivity, and there’s no hit to throughput, so we’re still looking at 3,000 wafers a day, which is incredibly fast,” said Mike LaTorraca, Microtronic’s Chief Marketing Officer. Errol Akomer, Applications Director at Microtronic, adds that in addition to the higher resolution, it’s a much cleaner signal. “The signal-to- noise ratio is much better — there’s a 5X improvement in that as well,” he said. Internally developed software algorithms also results in less nuisance defects and increased defect detection.

With these new capabilities, LaTorraca said they’ve created a bridge between micro and macro, and manual and automated. “We can take manual microscope images and put them into the same software that runs on EagleView. We can start to integrate defect information and the actual defect images from the manual microscope world into our tool, and that gives the fab owners a much more unified approach, a better, more comprehensive view, to make better decisions,” he said.

EAGLEview 5 is equipped with advanced imaging technology, analytical software, robotics and a 4-cassette multi-size (100mm-300mm) wafer platform. EAGLEview ProcessGuard Client Software provides defect visualization, digital guard-banding, wafer randomization/slot positional analysis, together with integration with manual microscopes for fab-wide defect tracking and reporting.

Every wafer is automatically OCR read, imaged, 100% inspected and stored for any step throughout the manufacturing process providing a comprehensive, centralized record – or ‘waferbase’ – that is also compatible with the fab’s manual microscope inspection data providing a more integrated, wholistic view of both micro and macro defects.

EAGLEview 5 acts as a hub for defect management across the fab by integrating manual microscope inspection, high resolution EAGLEview wafer images. EAGLEview 5 replaces legacy manual/micro wafer inspection by automating and standardizing wafer inspection processes. Blindly sampling 5 sites on a wafer is no longer needed. The newly developed ProcessGuard microscope interface software records micro defect classifications. This coupled with on-board commonality analysis allows root cause to be determined for micro defects and breathes new life into existing microscope inspection strategies. EAGLEview was originally designed to be comparable to naked eye 1x green light inspection.   EAGLEview 5 shifts the line between a macro green light inspection and microscope inspection.

“You can put all the micro defects into our database in the same ways you did the macro, so you classify your macro defects and you classify all your micro defects,” Fenske explained. “Now you have a record of what, where, how many, and because we collect all the history of where the lot went to, which tools it went through, we can then use that information to do commonality studies to figure out which tool caused the problem. With the microscope, there hasn’t been that type of integration, so we can now take all of those legacy things everyone needs to use and actually give them a new life.”

By Pete Singer

At a SEMICON West press conference yesterday, SEMI released its Mid-year Forecast. Worldwide sales of new semiconductor manufacturing equipment are projected to increase 19.8 percent to total $49.4 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the market high of $47.7 billion set in 2000. In 2018, 7.7 percent growth is expected, resulting in another record-breaking year ─ totaling $53.2 billion for the global semiconductor equipment market.

Figure 1 copy

“It’s really an exciting time for the industry in the terms of technology, the growth in information and data and that’s all going to require semiconductors to enable that growth,” said Dan Tracy, senior director, IR&S at SEMI.

The average of various analysts forecast the semiconductor industry in general 12% growth for the year. “It’s a very good growth year for the industry,” Tracy said. “In January, the consensus was about 5% growth for the year and with the improvement in the market and the firmer pricing for memory we see an increase in the outlook for the market.”

The SEMI Mid-year Forecast predicts wafer processing equipment is anticipated to increase 21.7 percent in 2017 to total $39.8 billion. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, will increase 25.6 percent to total $2.3 billion. The assembly and packaging equipment segment is projected to grow by 12.8 percent to $3.4 billion in 2017 while semiconductor test equipment is forecast to increase by 6.4 percent, to a total of $3.9 billion this year.

“Based on the May outlook, we are looking at a record year in terms of tracking equipment spending. This is for new equipment, used equipment, and spending related to the facility that installed the equipment. It will be about a $49 billion market this year. Next year, it’s going to grow to $54 billion, so we have two years in a row of back to back record spending,” Tracy said.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 68.7 percent, followed by Europe at 58.6 percent, and North America at 16.3 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 61.4 percent, to a total of $11.0 billion, following 5.9 percent growth in 2017. In 2018, South Korea, Taiwan, and China are forecast to remain the top three markets, with South Korea maintaining the top spot to total $13.4 billion. China is forecasted to become the second largest market at $11.0 billion, while equipment sales to Taiwan are expected to reach $10.9 billion.

Figure 2

What would a simple technique to remove thin layers from otherwise thick, rigid semiconductor crystals mean for the semiconductor industry? This concept has been actively explored for years, as integrated circuits made on thin layers hold promise for developments including improved thermal characteristics, lightweight stackability and a high degree of flexibility compared to conventionally thick substrates.

In a significant advance, a research group from IBM successfully applied their new “controlled spalling” layer transfer technique to gallium nitride (GaN) crystals, a prevalent semiconductor material, and created a pathway for producing many layers from a single substrate.

As they report in the Journal of Applied Physics, from AIP Publishing, controlled spalling can be used to produce thin layers from thick GaN crystals without causing crystalline damage. The technique also makes it possible to measure basic physical properties of the material system, like strain-induced optical effects and fracture toughness, which are otherwise difficult to measure.

The same 20-micron spalled GaN film, demonstrating the film's flexibility. Credit: Bedell/IBM Research

The same 20-micron spalled GaN film, demonstrating the film’s flexibility. Credit: Bedell/IBM Research

Single-crystal GaN wafers are extremely expensive, where just one 2-inch wafer can cost thousands of dollars, so having more layers means getting more value out of each wafer. Thinner layers also provide performance advantages for power electronics, since it offers lower electrical resistance and heat is easier to remove.

“Our approach to thin film removal is intriguing because it’s based on fracture,” said Stephen W. Bedell, research staff member at IBM Research and one of the paper’s authors. “First, we first deposit a nickel layer onto the surface of the material we want to remove. This nickel layer is under tensile strength — think drumhead. Then we simply roll a layer of tape onto the nickel, hold the substrate down so it can’t move, and then peel the tape off. When we do this, the stressed nickel layer creates a crack in the underlying material that goes down into the substrate and then travels parallel to the surface.”

Their method boils down to simply peeling off the tape, nickel layer and a thin layer of the substrate material stuck to the nickel.

“A good analogy of how remarkable this process is can be made with a pane of glass,” Bedell said. “We’re breaking the glass in the long direction, so instead of a bunch of broken glass shards, we’re left with two full sheets of glass. We can control how much of the surface is removed by adjusting the thickness of the nickel layer. Because the entire process is done at room temperature, we can even do this on finished circuits and devices, rendering them flexible.”

The group’s work is noteworthy for multiple reasons. For starters, it’s by far the simplest method of transferring thin layers from thick substrates. And it may well be the only layer transfer method that’s materially agnostic.

“We’ve already demonstrated the transfer of silicon, germanium, gallium arsenide, gallium nitride/sapphire, and even amorphous materials like glass, and it can be applied at nearly any time in the fabrication flow, from starting materials to partially or fully finished circuits,” Bedell said.

Turning a parlor trick into a reliable process, working to ensure that this approach would be a consistent technique for crack-free transfer, led to surprises along the way.

“The basic mechanism of substrate spalling fracture started out as a materials science problem,” he said. “It was known that metallic film deposition would often lead to cracking of the underlying substrate, which is considered a bad thing. But we found that this was a metastable phenomenon, meaning that we could deposit a thick enough layer to crack the substrate, but thin enough so that it didn’t crack on its own — it just needed a crack to get started.”

Their next discovery was how to make the crack initiation consistent and reliable. While there are many ways to generate a crack — laser, chemical etching, thermal, mechanical, etc. — it turns out that the simplest way, according to Bedell, is to terminate the thickness of the nickel layer very abruptly near the edge of the substrate.

“This creates a large stress discontinuity at the edge of the nickel film so that once the tape is applied, a small pull on the tape consistently initiates the crack in that region,” he said.

Though it may not be obvious, gallium nitride is a vital material to our everyday lives. It’s the underlying material used to fabricate blue, and now white, LEDs (for which the 2014 Nobel Prize in physics was awarded) as well as for high-power, high-voltage electronics. It may also prove useful for inherent biocompatibility, which when combined with control spalling may permit ultrathin bioelectronics or implantable sensors.

“Controlled spalling has already been used to create extremely lightweight, high-efficiency GaAs-based solar cells for aerospace applications and flexible state-of-the-art circuits,” Bedell said.

The group is now working with research partners to fabricate high-voltage GaN devices using this approach. “We’ve also had great interaction with many of the GaN technology leaders through the Department of Energy’s ARPA-E SWITCHES program and hope to use controlled spalling to enable novel devices through future partnerships,” Bedell said.

Worldwide industrial semiconductor revenues grew by 3.8 percent year-over-year in 2016, to $43.5 billion, according to the latest analysis from business information provider IHS Markit (Nasdaq: INFO).

Industrial electronics equipment demand was broad-based, with continued growth in commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and various medical electronics such as cardiac equipment, hearing aids and imaging systems, IHS Markit said.

The U.S. economy continued to boost industrial spending while improved economic conditions in Europe and large emerging countries like China, India and Brazil toward the end of 2016 that propelled growth. These economic conditions are expected to continue thorough 2017, according to the IHS Markit analysis.

Top 20 company ranks: Global industrial semiconductor market share

Texas Instruments (TI) maintained its position as the largest industrial semiconductor supplier in 2016 followed by Intel, STMicroelectronics, Infineon Technologies and Analog Devices. Intel surged to second place, swapping spots with Infineon, which dropped to fourth. The Intel IoT group’s double-digit revenue growth is attributed to strength in factory automation, video surveillance and medical segments.

“Toshiba, ON Semiconductor and Microchip Technology climbed into the top 10 industrial semiconductor supplier ranks in 2016,” said Robbie Galoso, principal analyst, industrial semiconductors for IHS Markit. Toshiba’s industrial market share rank jumped to number six, according to survey feedback. Toshiba’s industrial electronics revenue grew from $1.1 billion in 2015 to $1.4 billion in 2016—a 30.5 percent bounce driven by discretes, microcomponent integrated circuits (ICs), memory and logic IC solutions in manufacturing and process automation, power and energy as well as security and video surveillance.

Mergers and acquisitions make an impact

The semiconductor industry had another cycle of merger and acquisition in 2016 that affected the competitive landscape. The combined ON Semiconductor – Fairchild organization generated $1.3 billion in 2016 industrial revenues, catapulting the consolidated company into seventh place. The acquisition of Fairchild allowed On Semiconductor to leapfrog to the top ranks of the power discrete market, forecast to be one of the higher growth markets over the next five years, IHS Markit said

On Semiconductor has been a relatively small player in the power discrete segment; with the Fairchild acquisition, it now has the scale and product portfolio to compete effectively with the combined Infineon International Rectifier. On Semiconductor’s 2016 revenue grew nearly 60 percent, largely driven by analog and discretes in the manufacturing and process automation and the power and energy sectors, both of which were sizeable segments for Fairchild.

The Microchip Technology – Atmel merger generated $1.2 billion in revenues in 2016, propelling the combined company into 10th place. The acquisition of leading microcontroller supplier, Atmel, positioned Microchip as the third-ranked supplier of microcomponent ICs in the industrial market, after Intel and TI. The combination of Microchip and Atmel created an MCU powerhouse, allowing it to compete effectively against the combined NXP Freescale. Microchip Technology’s 2016 revenue growth of 53 percent was driven by microcomponent ICs in manufacturing and process automation, Atmel’s bread and butter. Toshiba, Micron and ON Semiconductor displaced Nichia, Renesas and Xilinx in the top 10 rankings.

China’s massive investments in light-emitting diode (LED) manufacturing capacity propelled Chinese firm MLS into the 2016 top 20 industrial semiconductor supplier ranks, displacing Maxim. “MLS posted revenue growth of 27 percent, to $640 million, building its share against competition including top-20 firms Nichia, Osram and Cree,” added Galoso.

Strategic acquisitions will continue to play a major role in shaping the overall semiconductor market rankings in key industrial semiconductor segments. IHS Markit expects Analog Devices to increase its lead in 2017 market shares among the top semiconductor suppliers, due to an acquisition of Linear Technology. A joint Analog Devices – Linear Technology would battle for the number four spot and impressive gains in test and measurement, manufacturing and process automation as well as medical electronics.  Among the top 10 semiconductor suppliers, eight companies achieved growth in 2016, with two companies posting double-digit growth due to mergers.

industrial semi growth

Industrial semiconductor key growth drivers

Optical semiconductors delivered solid performance, driven by continued strength in the LED lighting market. IHS Markit expects the LED segment to grow from $9.4 billion in 2016 to $14.3 billion in 2021. With many countries phasing out incandescent bulbs, mass adoption of energy-efficient LED lighting solutions will continue to gain traction as prices for LED lamps fall to affordable levels for average-income households. Discrete power transistors, thyristors, rectifiers and power diodes are expected grow from $5.7 billion in 2015 to $8 billion in 2021 due to policy shifts toward energy efficiency in the factory automation market. IHS Markit projects that the microcontrollers (MCUs) segment  will grow robustly in the long term, expanding from $4.4 billion in 2016 to $7 billion in 2021, attributing this growth to both shipments and average selling price driven by system level cost savings provided by MCUs through advances in power efficiency and integration integrated features supporting connectivity, security, sensors and HMI.

By Jamie Liao, SEMI Taiwan

Market demand is driving development of 5G network standards, and commercial applications are expected to be introduced by 2020. As applications for next-generation communications are evolving, mobile devices need to promise better performance and higher resistance to heat, high power, voltage and radiation. For existing technologies, compound semiconductors like SiC and GaN are no doubt the best solutions because they perform better in terms of energy band gaps, saturation velocities, heat conductivity and breakdown field strength. In order to facilitate development of the industry, SEMI Taiwan worked with the National Chung-Shan Institute of Science and Technology (NCSIST) and the Taiwan Institute of Economic Research (TIER) to organize the Compound Semiconductor Seminar ─ Enabling Next Generation of Communications. ASE Group, Airoha Technology Corp., eLaser and WIN Semiconductors Corp. joined with SEMI Taiwan to explore the materials and technology trends of compound semiconductors.

Compound Semiconductor Technologies Continue to Advance

Speaking on upcoming 5G network with the theme “Highly Efficient 5G PA Design,” Dr. Jerry Lin, CTO of Airoha Technology Corp., said that while 5G networks perform better than existing standards in data speed and capacity, power consumption may not increase simultaneously. In order to achieve that, interior design of communications devices also need to evolve. As power amplifier (PA) is normally the most power-consuming component in traditional cellular networks, developers should start with PA if they want to address the challenge.

Dr. Lin added that in addition to optimizing circuit design, developers should also consider connectivity, modem chips, PA structure and PA devices. So which process will prevail in the area of 5G PA? Is it CMOS? Or GaAs/GaN? Dr. Lin presented a table and pointed out that GaAs/GaN has more advantage in “breakdown voltage,” “power handling,” “through wafer via” and “substrate loss,” while CMOS is doing better in self-testing, complex bias circuit design, signal processing, integration, configuration flexibility and low power voltage. Therefore, Dr. Lin believed that GaAa/GaN will continue to exist as performance is the main concern for the design of base stations used in 5G, 6G or even millimeter-wave networks. Meanwhile, CMOS will have a bigger chance with price-sensitive IoT equipments because it is energy efficient and cheap. As for hand-held devices, sub-6GHz equipments may still adopt hybrid structures like GaAs/GaN or CMOS+GaAs. CMOS is likely to dominate in the millimeter-wave market.

Dr. Kun Chuan Lin, General Manager of eLaser’s branch in the Hsinchu Science and Industrial Park, shared insight on the development of GaN epitaxial wafer process with a speech entitled “GaN on Si Epitaxy Technology Innovation.” He said that when electronics product design requires better heat resistance, breakdown voltage, electron saturation velocity and current density, semiconductor devices made with the GaN process can deliver high-power output in high-frequency environment. Therefore, the technology will have great potential in next-generation applications like automotive electronics, power management systems, industrial lighting, portable electronics devices, communications equipment, and consumer electronics products.

Dr. Lin said when GaN epi-wafer was adopted in LED devices, one 150mm wafer would contain tens of thousands, or even hundreds of thousands LED units so the yield loss caused by thousands of particles would be minor. But in the case of large-sized GaN power devices made of epi-wafers, each 150mm wafer has only 1,000 to thousands of chips and the number of particles pretty much decides the yield of power devices on epi-wafers. In comparison, the epitaxy technology of GaN-on-Si is more important because of its low particle counts, and innovative technologies will be needed in this area of epi-wafer manufacturing.

Next-generation Communications Frameworks Emerge: From Modules to Packaging and Testing

Dr. W.K. Wang, Technical Director of WIN Semiconductors Corp., discussed GaAs solutions for millimeter-wave front-end modules with a speech entitled “Advanced GaAs Solution for mmw FEM.” According to Dr. Wang, the GaAs pHEMT process has been long adopted in the area of wireless communications, such as peer-to-peer RF transmission and very small aperture terminal (VSAT.) Now, Win Semiconductors’ pHEMT and PIN diode technology platforms are already capable of providing solutions to performance and circuit requirements. He said GaAs technologies have been rapidly evolving in recent years so wafer package and multi-function devices can now be integrated into GaAs wafer fabrication. In addition, the technology to integrate pHEMT and PIN diode into PINHEMT will also enjoy great potential in the area of millimeter-wave front-end modules.

Dr. Wang also pointed out that 0.1um pHEMT can now be used to run E-band and D-band amplifiers, while Ka-Band Doherty amplifiers and low-noise amplifiers have been made possible through 0.15um pHEMT. As KA-band switches can be demonstrated in a GaAs PIN diode process, it proves that GaAs pHEMT/PIN is a suitable verification solution in millimeter-wave communications.

In a speech entitled “Next Wave RF & Photonics Packaging Solution,” Dr. Vincent Lin, Technical Director of ASE Group shared his insight on the challenge that Moore’s Law has slowed down. He said while volumes of data from existing mobile devices and cloud computing services are increasing, all chip technologies in the semiconductor industry have advanced in a slower manner. Therefore, cross-system integration will be the solution to bandwidth issues.

Dr. Lin said that mobile devices’ RF modules and silicon photonics in data centers are the key devices in cloud computing platforms now. Both of them need various materials, including compound semiconductors, silicon, passive devices, special crystals or multi-material high-speed connecting chips — with impedance matching and low insertion loss being the two key indicators to performance. Dr. Lin also demonstrated a new packaging platform of RF modules and silicon photonics modules that can serve as the best solution for the local industry.

In addition to these keynote speeches on latest trends and technologies in the market, the seminar also offered an opportunity for participants to interact and expand connections. Terry Tsao, president of SEMI Taiwan, said to promote development of Taiwan’s compound semiconductor industry, SEMI will continue to organize events where people in the industry can exchange opinions. SEMICON Taiwan 2017 will establish a Compound Semiconductor Pavilion for the first time, where international forums and get together to be held for industry insiders to share insight on future trends and technologies to help promote exchanges, collaboration and opportunities in the market.

By James Amano, International Standards, SEMI

At its recent Spring 2017 meeting, the North American Regional Standards Committee (NARSC) approved formation of a Taiwan chapter of the global SEMI Standards Automation Technology Committee. Taiwan joins existing Automation Technology chapters active in Japan and Europe. The Taiwan chapter will be led by K.C. Chou (ASE), C.S. Wu (MIRDC), Jen-Hui Tsai (Mechanical & Mechatronics Systems Research Laboratories, ITRI), and Gwo-Sheng Peng (Center for Measurement Standards, ITRI).

Co-Chair Chou explains the need for the Taiwan chapter:  “SEMI has a strong reputation for successful standardization, which is why the Taiwan PCB industry has selected the global SEMI Standards platform to develop consensus on equipment communication and other manufacturing areas where standards are needed to drive down cost.”

The initial focus of the Taiwan chapter will be to develop a guide for PCB equipment communication interfaces. The guide will be based on SEMI E4: SEMI Equipment Communications Standard 1 Message Transfer (SECS-I), SEMI E5: SEMI Equipment Communications Standard 2 Message Content (SECS-II), E37: High-Speed SECS Message Services (HSMS) Generic Services, E37.1: High-Speed SECS Message Services (HSMS) Generic Services, and E30: Generic Model for Communications and Control of Manufacturing Equipment (GEM).

David Lai of the Taiwan Printed Circuit Association comments: “Without automation standards, it will be difficult for the PCB industry to achieve its ambitious performance targets. In order to fulfill the goal of PCB automation, the standard will simplify the implementation of data collection & analytics, M2M communication and datamation step by step. Therefore, I am pleased that activities in the Taiwan SEMI Standards Automation Technology TC Chapter are underway.”

While the initial chapters of the Automation Technology Committee are located in Europe, Japan, and Taiwan, all interested parties, regardless of location, are invited to join in the global effort. To get involved, please contact your local SEMI Standards staff or visit: www.semi.org/standards.

 

The SEMI Foundation and the Micron Technology Foundation announced their partnership this week to deliver the 213th SEMI High Tech U (HTU) program which kicks off in earnest today at Micron’s facilities in Milpitas. Forty students from local high schools are attending the three-day science, technology, engineering and math (STEM) program.

The nonprofit SEMI Foundation has been holding its flagship program, SEMI High Tech U, at industry sites around the world since 2001 to emphasize the importance of STEM skills and inspire young people to pursue careers in high technology fields. HTU allows students to meet engineers and volunteer instructors from industry in a face-to-face setting with tech-related, hands-on activities such as etching wafers, making circuits, coding and professional interviews training.

“We are delighted to partner with Micron in our common goal to motivate the next generation of innovators,” said Ajit Manocha, president and CEO of SEMI and the SEMI Foundation. “HighTech U has reached more than 6,000 students in eleven states as well as nine countries internationally. We are pleased to join with Micron to serve students here in Silicon Valley.”

“Micron Technology Foundation has been inspiring learners of all ages and supporting early exposure to technology through our own Micron Chip Camp for 17 years,” said Sanjay Mehrotra, Micron president and CEO. “SEMI High Tech U is complementary to these efforts and we are proud to partner with the SEMI Foundation to deliver our first joint program focused on high school students to promote careers in STEM-related high tech industries such as semiconductor manufacturing.”

 

Ajit Manocha, president and CEO of SEMI, and Sanjay Mehrotra, president and CEO of Micron, with SEMI High Tech U students.

Ajit Manocha, president and CEO of SEMI, and Sanjay Mehrotra, president and CEO of Micron, with SEMI High Tech U students.

Manocha and Mehrotra jointly welcomed participating students to the SEMI HTU program and shared highlights of their professional experience during a pre-event kick-off at Micron in Milpitas on Monday, June 26. Students will spend Tuesday at Micron working on STEM focused, hands-on activities. Micron team members will assist in teaching the modules, offering students a connection to semiconductor professionals. On Wednesday, the program convenes at San Jose State University where students will learn about etching wafers and tour the SJSU campus. The program will culminate Thursday at Micron with critical thinking and soft skills development activities along with mock interviews. Students will “graduate” from SEMI High Tech U on Thursday afternoon at Micron.