Category Archives: Wafer Processing

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 26,000 professionals from the electronics manufacturing supply chain attend SEMICON West and the co-located Intersolar. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

Selected from over 600 exhibitors, SEMI announced today that the following Best of West 2017 Finalists will be displaying their products on the show floor at Moscone Center from July 11-13:

  • Mentor, a Siemens Business: Tessent® Cell-Aware Diagnosis – With FinFETs in high volume, finding systematic yield issues at the transistor level is important. The Tessent Cell-Aware Diagnosis technology significantly improves diagnosis of defects beyond the inter-connect and inside the logic cells. (Process Control, Metrology and Test Category; North Hall Booth #6661)
  • Microtronic Inc.: EAGLEview 5 Macro Defect Management Platform – EagleView 5 is the new, yield-enhancing, breakthrough macro defect inspection platform that was developed – and deployed in production — through collaboration with several leading device manufacturers who wanted to standardize and unify wafer defect management throughout their fab. Innovations include: dramatically improved defect detection; level-specific sorting; and integration with manual microscopes. (Process Control, Metrology and Test Category; North Hall Booth #5467)
  • SPTS Technologies Ltd: SentinelTM End-Point Detection System for Plasma Dicing after Grind – The Sentinel™ End-Point Detection System improves the control of plasma dicing processes and protects taped wafers for improved yields.  In addition to signaling exposure of the tape, Sentinel™ also detects loss of active cooling during the process to enable intervention to prevent yield loss. (Process Control, Metrology and Test Category; West Hall Booth #7617)
  • TEL: Stratus P500 – The Stratus P500 system electroplates panel substrates with wafer level processing precision.  As redistribution layers (RDL) reduce to widths below 10 µm line/space, and package sizes increase, conventional plating systems are challenged to meet system-on-package requirements. The P500 makes panel scale fine line RDL and feature filling applications possible. (Assembly/Packaging Solutions Category; North Hall Booth #6168)

Congratulations to each of the Finalists. The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 12, 2017.

BY PETE SINGER, Editor-in-Chief

What if the automotive industry had achieved the incredible pace of innovation as the semiconductor industry during the last 52 years? A Rolls Royce would cost only $40, go around the world eight times on a gallon of gas, and have a top speed of 2.4 million miles per hour.

That point was made by Subi Kengeri speaking at The ConFab in May. Kengeri is vice president, CMOS Business Unit, at GlobalFoundries. He also noted that if one of today’s high performance graphics chips were produced using 1960 vs state-of-the-art “it would be the size of a football field.”

Clearly, no other industry can match the pace of innovation of the semiconductor industry. “The transistor count per square inch in 1965 was roughly 100. In 52 years, if you follow Moore’s Law of 2 years per innovation cycle, that gives 26 innovation cycles. That’s 100 millionX improvement (2X26),” Kengeri noted.

Of course, there has been plenty of innovation in the automotive industry. Interestingly, most of the exciting new innovations such as backup cameras, collision avoidance, navigation/ infotainment, self-parking, and anti-lock brakes are only possible because of semiconductor technology.

Kengeri said that Moore’s Law scaling will continue – “there’s no question about it,” he said – but there’s a growing need for new innovation to address the increasingly diverse array of semicon- ductor applications. These are driven by growth in mobile computing, development in IoT computing, the emergence of intelligent computing and augmented/virtual reality.

“Leading edge innovation will continue and all the leading manufacturers continue to invest, whether it is litho scaling in terms of EUV, or device archicture,” Kengeri said. “What is really important is how do we continue to innovate, how do we continue to get the value at competitive costs? Trying to get the scaling at any cost is not what is needed in the majority of the markets. It’s still okay at the very high end, for CPUs and servers, but in all markets, managing cost is really critical.”

“On top of all of that, we have to continue to deliver on time. Because of the complexity, things aren’t getting slower. We’re doing everything we can do continue to keep the same pace as we used to,” he added.

Kengeri said continued advances mean changing the way we think about innovation. It will require continued technical Innovation (materials and processes, device architecture and design-technology co-optimization), but – perhaps more importantly – business model innovation. This includes new thinking about long-term R&D focus/ investment, shared investments/learning/reuse, and consolidation and collaboration.

Industry experts answer questions about the new standard in a virtual roundtable.

In recent years, energy consumption has decreased due to several innovations that have helped to improve the energy efficiency of process tools and sub-fab equipment, but an increase in the number of processes and the growing complexity of processing at the current node has resulted in a spike in energy consumption in the fab. Approximately 43% of the energy consumed in the fab is due to the processing equipment and, of this, 20% is vacuum and abatement (8% overall).

A new standard from SEMI, E175, defines energy saving modes, which combined with the EtherCAT signaling standard, can help fabs save energy and other gas/utility costs when the tool is not processing and with no impact on subsequent wafer processing.

EtherCAT, based on industrial Ethernet, provides high- speed control and monitoring. It is the communication standard of choice for the latest semiconductor tool controllers to connect to sensors and actuators around the tool, including vacuum and abatement systems.

SEMI E175 defines how process tools communicate with sub-fab equipment, such as vacuum pumps and gas abatement systems, to reduce utility consumption at times when wafers are not being processed by the tool, and returning to full performance when the tool is again required to process wafers. It builds on SEMI E167, which defines communication between the fab host/ WIP controller and the process tools for the purpose of utility saving.

Collaboration between the E175 and EtherCAT groups has seen a harmonization of the communication standards to provide co-ordinated energy saving across devices in the fab.
We invited experts in this area to answer a few questions in a virtual roundtable. The participants are:

• GERALD SHELLEY, Senior Product Manager Communication and Control at Edwards, and the EtherCAT Chair Abatement / Roughing pump working groups, E175 task force.

• MIKE CZERNIAK, Environmental Solutions Business Development Manager at Edwardsm Co-Chair of SEMI International Standards E167 & E175, and campaigner for energy saving

• GINO CRISPIERI, Applied Materials – Past Co-chair of E175 (originally SEMATECH/ISMI, then independent consultant, prior to Applied Materials)

• MARTIN ROSTAN, Executive Director, EtherCAT Technology Group

Q: Please explain what drove the standards work on energy saving and the achievements to date.

SHELLEY: There is increased pressure on the industry to reduce energy and utility saving from both a cost and environmental standpoint. Subfab equipment is a major consumer of utilities, which is wasted when a tool is not in use. Different manufacturers have implemented energy saving solutions, with minimal direct connection to the tool. However, direct tool connection has emerged as the best way to maximize saving without any risk to wafer processing.

CZERNIAK: This work originated in the ISMI part of SEMATECH as a follow-on to generic work aimed at reducing the overall utilities footprint of modern fabs. In response to this and requests from customers, Edwards developed vacuum pumps and gas abatement systems that had energy-saving functionality. However, it soon became clear that the limitation to implementing such savings was the absence of standardised signalling between the process tool and sub-fab equipment.

CRISPIERI: A SEMATECH project around 2009 started to look into opportunities for saving energy in the semiconductor factories. At that time, suppliers of pumps and abatement systems already had started initiatives to provide their own solutions to the initiative. Since that time, the industry has adopted two new standards: SEMI E167 Specification for Equipment Energy Saving Mode Communication (between factory and semicon- ductor equipment) and SEMI E175 Specification for Subsystem Energy Saving Mode Communication (between semiconductor equipment and subsystems).

Q: Please describe how the energy saving task force was born and why you decided to get involved.

CRISPIERI: Back in 2009 while working for SEMATECH in Austin, Texas, prior to SEMATECH’s move the New York, Thomas Huang an assignee for GlobalFoundries to the EHS Program approached and asked me if I would be interested in helping him drive a standard for equipment suppliers to enable their equipment to save energy during idle times. Because of my previous experience working with equipment suppliers and developing standards for equipment and factory communication, I accepted to chair a task force to drive the equipment supplier’s new capability requirement into a standard. At first, we thought it would be an easy task and that everyone would jump to help create and approve the standard in a short amount of time because of its benefits. A two phase approach was defined to drive the standardization process and engage semiconductor and sub-fab equipment suppliers accordingly. It took almost three years to complete the Phase I (2013) and another three to complete the Phase II (2016) standards.

SHELLEY: The task force was an extension of E167 which previously defined the communication into the tool from the supervisory systems, however to achieve maximum benefit signalling to tool subsystems was key and the E175 task force was the result.

CZERNIAK: Following-on from the above, the ISMI working group became a SEMI Standards Task Force and began work at developing a standard, initially for Host to process tool (E167) and then from tool to sub-fab (E175), which I was co-chair for to ensure continuity and clear the signalling “roadblock”.

Q: How have suppliers collaborated on E175?

CRISPIERI: Compared with the suppliers who partic- ipated in SEMI E167 development, the suppliers involved in the development and approval of SEMI E175 were more committed to make it happen and helped drive the standardization process to conclusion much more efficiently. Edwards, AMAT, TEL, Hitachi- Kokusai and DAS-Europe regularly participated and provided inputs to standardize behavior and require- ments for their own equipment. We run into some difficulty getting aligned with other standard activities that were driven by SEMI’s EHS Committee because their changes affected our standardization process. I must note that the overall participation was excellent in particular from Edwards Vacuum and AMAT.

ROSTAN: Within the ETG Semiconductor Technical Working Group individual task groups already had multiple suppliers collaborating on the detail of the EtherCAT profiles for all devices, with technical support from the EtherCAT Technical Group. We were fortunate to have a delegate from Edwards in both the Semi E175 Task Force and key EtherCAT Task Groups to informally broker agreement between the teams.

SHELLEY: The suppliers were able to use their collective experience to work through a number of options to find the optimum way of controlling subfab equipment, tackling variability in wakeup time and control architec- tures between device types and equipment technology.

CZERNIAK: Suppliers, automation providers, tool OEMs and end-users have all collaborated to help develop a standard that works for everyone and aligns with earlier standards like S23.

Q: How was the EtherCAT collaboration beneficial to E175?

SHELLEY: By sharing information and understanding in real time we demonstrated the E175 concept is achievable using the favored protocol for new tool platforms and defined how it would be implemented. We co-operated to take both these standards to alignment in one simul- taneous step, saving considerable committee time on both sides that would have been necessary to resolve any divergence of the detail.

ROSTAN: By devising the implementation of E175 in parallel the EtherCAT Task Groups involved were able to feedback detailed technical proposals and show the E175 standard could be implemented relatively easily within the existing EtherCAT standards.

CRISPIERI: Participation and collaboration from the EtherCAT Working Group was critical to accelerate the implementation and adoption of the standard. Dry Contacts and EtherCAT communication protocol messages were added to two Related Information sections and included in the SEMI E175 standard at the time of its publication.

CZERNIAK: This enables a “richer” signalling environment than simple dry contacts (which are also supported) that enables even greater utility savings to be made.

Q: How has EtherCAT been able to support the require- ments of the tool and Semi E175?

CZERNIACK: By providing timing information; the longer the time the tool is inactive, the greater the savings possible.

ROSTAN: As the control network of choice for the latest semiconductor tools, EtherCAT has been ideally placed to support enhancements, such as the energy saving connectivity increasingly being requested by the fabs. In particular, it was good to see the Pump and Abatement Task Groups of the existing Semiconductor Technical Working Group formulate an E175 compliant solution within the timescales of the second release of the EtherCAT semiconductor device profiles. The EtherCAT Technology Group was also more than happy to support the publication of extracts of the EtherCAT standards being used as protocol examples in the Imple- mentation guidelines of the Semi E175 document.

SHELLEY: EtherCAT has the fast / deterministic connec- tivity and proven integration with tool controllers that allows E175 functionality to be easily added without any loss of performance. By including the requirements of Semi E175 in the EtherCAT standards, both equipment suppliers and tool vendors can establish energy saving communication quickly and easily.

CRISPIERI: The coordination between EtherCAT Working Group and the SEMI ESEC task force group was conducted by Mr. Gerald Shelley from Edwards Vacuum. With his help and leadership, we reached effortlessly agreement and acceptance for the required messages, parameters and values into the EtherCAT respective Pump and Abatement Profile documents. Havingworking usage scenarios and support from the EtherCAT Working Group has been invaluable.

Q: Why is energy saving important to the industry?

ROSTAN: In the industrial world, EtherCAT users are increasingly using our communication and control technologies to drive down energy consumption. The semiconductor industry operates in parts of the world where energy is a limited and expensive resource, whilst the latest wafer processing requires more power. The manufacturers are therefore in great need for energy saving opportunities, such as when the tool subsystems are not in use.

SHELLEY: The fabs are being squeezed by an increase in the complexity and number of processes involved in manufacturing a wafer, driving consumption up and increasing scarcity of energy supply. This is further compli- cated with associated cost and government pressure to “keep the lights on”.

CRISPIERI: It is not hard to see why is so important for device makers or the semiconductor manufacturing industry to adopt and require energy conservation capabilities in their factories. Energy consumed by many equipment components and support systems, such as pumps and abatement systems, never stop from running even when the equipment is idle and waiting for product to be delivered for processing. These components and support systems can save millions of dollars each year if their power consumption is reduced. This energy consumption reduction extends their life cycle thus reducing costs of maintenance and parts replacement. Any effort to reduce energy consumption helps lower costs and adds gains to not only the manufacturer but to those who have to generate the energy for consumption.

CZERNIACK: Cost reduction is always important, but electrical supply is limited in some areas.

The ongoing slump in shipments of standard personal computers along with the drop-off in tablets are setting the stage for cellphone IC sales to finally surpass integrated circuit revenues in total personal computing systems this year, based on new forecasts in the recently released update of IC Insights’ 2017 IC Market Drivers Report.

IC sales for cellular phone handsets are projected to grow 16% in 2017 to $84.4 billion, as shown in Figure 1, while the integrated circuit market for personal computing systems (desktop and notebook PCs, tablets, and thin-client Internet-centric units) is now forecast to increase 9% to $80.1 billion this year, according to the 150-page update to the 590-page report, originally released in 4Q16.

Fig 1

Fig 1

IC sales for both cellphones and total personal computing systems are strengthening significantly in 2017 primarily because of strong increases in the amount of money being spent on memory, with the average selling price (ASP) of DRAM expected to climb 53% and NAND flash ASP forecast to rise 28% this year. In 2016, IC sales for cellphone handsets grew 2% after rising 1% in 2015, while dollar volume for integrated circuits used in personal computing systems increased just 1% last year after falling 6% in 2015. Cellphone IC sales are also getting a lift from a projected 5% increase in shipments of smartphones, which are being packed with more low-power DRAM and nonvolatile flash storage, while growth in personal computing is expected to be held back by 3% declines in both standard personal computer and tablet unit volumes in 2017.

Shrinking shipments of desktop and notebook computers enabled cellphone IC sales to surpass integrated circuit revenues for standard PCs in 2013.  During 2015 and 2016, cellphone IC sales came close to catching up with integrated circuit sales for total personal computing systems.  In 2017, cellular phone handsets are now forecast to take over as the largest end-use systems category for IC sales.  The gap between IC sales for cellphones and total personal computing systems is projected to widen by the end of this decade.  Cellphone integrated circuit sales are expected to increase by a compound annual growth average (CAGR) of 5.3% in the 2015-2020 forecast period to $92.1 billion versus personal computing IC revenues rising by CAGR of just 2.9% to $83.8 billion in 2020, says the Update of IC Insights’ 2017 IC Market Drivers Report.

The refreshed forecast shows IC sales for standard PCs climbing 11.2% in 2017 to $67.5 billion after increasing about 4% in 2016 to $60.7 billion.  Tablet IC sales are now expected to drop 2% to $11.8 billion in 2017 after falling 11% in 2016 to $12.1 billion, based on the updated outlook.  IC sales for thin-client and Internet/cloud computing centric systems—such as laptops based on Google’s Chromebook platform design—are projected to rise 15% in 2017 to a $838 million after surging 21% in 2016 to $728 million.  Between 2015 and 2020, IC sales for standard PCs are expected to grow by a CAGR of 4.1% to $71.6 billion in the final year of the updated outlook, while table integrated circuit revenues are projected to fall by -3.9% annual rate in the period to about $11.0 billion and ICs in Internet/cloud computing are forecast to rise by CAGR of 13.8% to more than $1.1 billion.

New research into the largely unstudied area of heterostructural alloys could lead to greater materials control and in turn better semiconductors, advances in nanotechnology for pharmaceuticals and improved metallic glasses for industrial applications.

Heterostructural alloys are blends of compounds made from materials that don’t share the same atom arrangement. Conventional alloys are isostructural, meaning the compounds they consist of, known as the end members, have the same crystal structure.

“Alloys are all around us,” said study co-author Janet Tate, a physicist at Oregon State University. “An example of an istostructural alloy is an LED; you have a semiconductor like aluminum gallium arsenide, dope it with a particular material and make it emit light, and change the color of the light by changing the relative concentration of aluminum and gallium.”

Structure and composition are the two means of controlling the behavior of materials, Tate said. Combining materials gives the alloy properties between those that the end members have on their own.

“If two materials have different structures, as you mix them together it’s not so clear which structure will win,” said Tate, the Dr. Russ and Dolores Gorman Faculty Scholar in the College of Science. “The two together want to take different structures, and so this is an extra way of tuning an alloy’s properties, a structural way. The transition between different crystal structures provides an additional degree of control.”

Tate and collaborators from around the world, including the National Renewable Energy Laboratory, published their findings in Science Advances.

“This is a very interesting piece of materials science that represents a somewhat uncharted area and it may be the beginning something quite important,” Tate said. “The heterostructural alloy concept had been known before, but it’s different enough that it hadn’t really been explored in a detailed phase diagram – the mapping of exactly how, at what temperature and what concentration, it goes from one structure to another.

“This paper is primarily the NERL’s theoretical work being supported by other collaborators’ experimental work,” Tate said. “Our involvement at OSU was in making one of the kinds of heterostructural alloys used in the research, the combination of tin sulfide and calcium sulfide.”

Tate and graduate student Bethany Matthews have been focusing on the semiconductor application.

“Tin sulfide is a solar cell absorber, and the addition of calcium sulfide changes the structure and therefore the electrical properties necessary for an absorber,” Tate said “Combining tin sulfide with calcium sulfide makes it more isotropic – properties being the same regardless of orientation – and that’s usually a useful thing in devices.”

In this study, thin-film synthesis confirmed the metastable phases of the alloys that had been predicted theoretically.

“Many alloys are metastable, not stable – if you gave them enough time and temperature, they’d eventually separate,” Tate said. “The way we make them, with pulsed laser deposition, we allow the unstable structure to form, then suppress the decomposition pathways that would allow them to separate; we don’t give them enough time to equilibrate.”

Metastable materials – those that are thermodynamically stable provided they are not subjected to large disturbances – are in general understudied, Tate said.

“When theorists predict properties, they tend to work with materials that are stable,” she said. “In general the stable compounds are easier to attack. The idea here with heterostructural alloys is that they give us a new handle, a new knob to turn to change and control materials’ properties.”

North America-based manufacturers of semiconductor equipment posted $2.27 billion in billings worldwide in May 2017 (three-month average basis), according to the May Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in May 2017 was $2.27 billion. The billings figure is 6.4 percent higher than the final April 2017 level of $2.14 billion, and is 41.9 percent higher than the May 2016 billings level of $1.60 billion.

“Semiconductor equipment billings for North American headquartered equipment manufacturers increased for the fourth month in a row and are 42 percent higher than the same month last year,” said Ajit Manocha, president and CEO of SEMI.  “The strength of this cycle continues to be driven by Memory and Foundry manufacturers as the industry invests in 3D NAND and other leading-edge technologies.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)
Year-Over-Year
December 2016
$1,869.8
38.5%
January 2017
$1,859.4
52.3%
February 2017
$1,974.0
63.9%
March 2017
$2,079.7
73.7%
April 2017 (final)
$2,136.4
46.3%
May 2017 (prelim)
$2,273.0
41.9%

Source: SEMI (www.semi.org), June 2017

SEMI ceased publishing the monthly North America Book-to-Bill report in January 2017. SEMI will continue publish a monthly North American Billings report and issue the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ).

UMC (NYSE: UMC; TWSE: 2303), a global semiconductor foundry, today announced that its board of directors has appointed senior vice presidents SC Chien and Jason Wang as co-presidents of the company, following Po-Wen Yen’s retirement as UMC CEO. The co-presidents are collectively accountable for the overall performance of UMC, and will report to Chairman Stan Hung directly. The transition will become effective immediately.

“Co-presidents Chien and Wang bring complimentary experience and capabilities to enable UMC to have the best minds committed to our most critical decisions and execution ability,” said Chairman Hung. “With their respective roles clearly defined, I anticipate a very smooth transition as we enter the next stage of UMC’s growth. Our priorities going forward will include a high degree of customer focus, consistent operational excellence, clear investment strategy, and maximizing shareholder value.”

Chairman Hung continued, “We would like to extend our sincere appreciation to CEO Yen for his 30+ years of dedicated service. Under his leadership, UMC has established a solid foundation and legacy for our co-presidents to build upon, and we wish him all the best on his retirement as he continues to provide his knowledge, experience, and service to our community and society.”

CEO Yen commented, “It has been a rewarding opportunity to have helped UMC evolve during my five years as the company’s CEO. I am honored to have worked with an exceptionally dedicated and skilled team of executives and managers to bring benefits to UMC and its customers, and firmly believe in the company’s positive direction going forward. I have worked closely with Mr. Chien and Mr. Wang for many years, and am convinced in their ability to lead UMC to new heights as co-presidents. Meanwhile, after my retirement, I look forward to further increasing my involvement in social and charitable activities in order to bring heightened awareness to the importance of mutual prosperity with our surrounding environment and society.”

The responsibilities of the co-presidents will be structured as follows:

  • SC Chien will focus on the core manufacturing and technology aspects of UMC including R&D and operations. Mr. Chien possesses more than 30 years of semiconductor R&D experience. He joined UMC in 1989, and throughout his 28 years at UMC, he has led multiple functions within the company, including ATD (advanced technology development), STD (specialty technology development), CE (customer engineering), TTD (technology transfer and development), IPDS (IP & design support) and CM (Corporate marketing).
  • Jason Wang will focus on the business aspects of UMC, including corporate strategy & planning, sales & marketing, and customer engineering. Mr. Wang joined UMC as vice president of Corporate Marketing in 2008. From 2009 to 2014, he served as president of UMC-USA responsible for UMC North American business. Most recently, he was senior vice president in charge of Worldwide Sales and Corporate Marketing.

GLOBALFOUNDRIES this week announced the availability of its 7nm Leading-Performance (7LP) FinFET semiconductor technology, delivering a 40 percent generational performance boost to meet the needs of applications such as premium mobile processors, cloud servers and networking infrastructure. Design kits are available now, and the first customer products based on 7LP are expected to launch in the first half of 2018, with volume production ramping in the second half of 2018.

In September 2016, GF announced plans to develop its own 7nm FinFET technology leveraging the company’s unmatched heritage of manufacturing high-performance chips. Thanks to additional improvements at both the transistor and process levels, the 7LP technology is exceeding initial performance targets and expected to deliver greater than 40 percent more processing power and twice the area scaling than the previous 14nm FinFET technology. The technology is now ready for customer designs at the company’s leading-edge Fab 8 facility in Saratoga County, N.Y.

“Our 7nm FinFET technology development is on track and we are seeing strong customer traction, with multiple product tapeouts planned in 2018,” said Gregg Bartlett, senior vice president of the CMOS Business Unit at GF. “And, while driving to commercialize 7nm, we are actively developing next-generation technologies at 5nm and beyond to ensure our customers have access to a world-class roadmap at the leading edge.”

GF also continues to invest in research and development for next-generation technology nodes. In close collaboration with its partners IBM and Samsung, the company announced a 7nm test chip in 2015, followed by the recent announcement of the industry’s first demonstration of a functioning 5nm chip using silicon nanosheet transistors. GF is exploring a range of new transistor architectures to enable its customers to deliver the next era of connected intelligence.

GF’s 7nm FinFET technology leverages the company’s volume manufacturing experience with its 14nm FinFET technology, which began production in early 2016 at Fab 8. Since then, the company has delivered “first-time-right” designs for a broad range of customers.

To accelerate the 7LP production ramp, GF is investing in new process equipment capabilities, including the addition of the first two EUV lithography tools in the second half of this year. The initial production ramp of 7LP will be based on an optical lithography approach, with migration to EUV lithography when the technology is ready for volume manufacturing.

Imec, a research and innovation hub in nano-electronics and digital technology, announced today that it has developed 200V and 650V normally-off/enhancement mode (e-mode) on 200mm/8-inch GaN-on-Silicon wafers, achieving a very low dynamic Ron dispersion (below 20 percent) and state-of-the-art performance and reproducibility. Stress tests have also shown a good device reliability. Imec’s technology is ready for prototyping, customized low-volume production as well as for technology transfer.

GaN technology offers faster switching power devices with higher breakdown voltage and lower on-resistance than silicon (Si), making it an ideal material for advanced power electronic components. Imec’s GaN-on-Si device technology is Au-free and compatible with the wafer handling and contamination requirements for processing in a Si fab. A key component of the GaN device structure is the buffer layer, which is required to accommodate the large difference in lattice parameters and thermal expansion coefficient between the AlGaN/GaN materials system and the Si substrate. Imec achieved a breakthrough development in the buffer design (patent pending), allowing to grow buffers qualified for 650 Volt on large diameter 200mm wafers. This, in combination with the choice of the Si substrate thickness and doping increased the GaN substrate yield on 200mm to competitive levels, enabling low-cost production of GaN power devices. Also, the cleaning and dielectric deposition conditions have been optimized, and the field plate design (a common technique for achieving performance  improvement) has been extensively studied. As a result, the devices exhibit dynamic Ron dispersion below 20% up till 650 Volt over the full temperature range from 25°C to 150°C. This means that there is almost no change in the transistor on-state after switching from the off-state, a challenge typical for GaN technology.

“Having pioneered the development of GaN-on-Si power device technology on large diameter substrates (200mm/8-inch), imec now offers companies access to its normally-off/e-mode GaN power device technology through prototyping, low-volume manufacturing as well as via a full technology transfer” stated Stefaan Decoutere, program director for GaN technology at imec. “Next to enhancement mode power device switches, imec also provides lateral Schottky diodes for power switching applications. Based on imec’s proprietary device architecture, the diode combines low turn-on voltage with low leakage current, up to 650V – a combination that is very challenging to achieve.”

si wafer

A multi-institutional team led by the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) discovered a way to create new alloys that could form the basis of next-generation semiconductors.

Semiconductor alloys already exist-often made from a combination of materials with similar atomic arrangements-but until now researchers believed it was unrealistic to make alloys of certain constituents.

“Maybe in the past scientists looked at two materials and said I can’t mix those two. What we’re saying is think again,” said Aaron Holder, a former NREL post-doctoral researcher and now research faculty at the University of Colorado Boulder. Holder is corresponding author of a new paper in Science Advances titled Novel phase diagram behavior and materials design in heterostructural semiconductor alloys. “There is a way to do it.”

Scientists connected to the Center for Next Generation of Materials by Design (CNGMD) made the breakthrough and took the idea from theory to reality. An Energy Frontier Research Center, which is supported by the Energy Department’s Office of Science and researchers from NREL, the Colorado School of Mines, Harvard University, Lawrence Berkeley National Laboratory, Massachusetts Institute of Technology, Oregon State University, and SLAC National Accelerator Laboratory.

“It’s a really nice example of what happens when you bring different institutions with different capabilities together,” said Holder. His co-authors from NREL are Stephan Lany, Sebastian Siol, Paul Ndione, Haowei Peng, William Tumas, John Perkins, David Ginley, and Andriy Zakutayev.

A mismatch between atomic arrangements previously thwarted the creation of certain alloys. Researchers with CNGMD were able to create an alloy of manganese oxide (MnO) and zinc oxide (ZnO), even though their atomic structures are very different. The new alloy will absorb a significant fraction of natural sunlight, although separately neither MnO nor ZnO can. “It’s a very rewarding kind of research when you work as a team, predict a material computationally, and make it happen in the lab,” Lany said.

Using heat, blending a small percent of MnO with ZnO already is possible, but reaching a 1:1 mix would require temperatures far greater than 1,000 degrees Celsius (1,832 degrees Fahrenheit), and the materials would separate again as they cool.

The scientists, who also created an alloy of tin sulfide and calcium sulfide, deposited these alloys as thin films using pulsed laser deposition and magnetron sputtering. Neither method required such high temperatures. “We show that commercial thin film deposition methods can be used to fabricate heterostructural alloys, opening a path to their use in real-world semiconductor applications,” co-author Zakutayev said.

The research yielded a first look at the phase diagram for heterostructural alloys, revealing a predictive route for properties of other alloys along with a large area of metastability that keeps the elements combined. “The alloy persists across this entire space even though thermodynamically it should phase separate and decompose,” Holder said.