Category Archives: Wafer Processing

North America-based manufacturers of semiconductor equipment posted $2.03 billion in billings worldwide in March 2017 (three-month average basis), according to the March Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in March 2017 was $2.03 billion. The billings figure is 2.6 percent higher than the final February 2017 level of $1.97 billion, and is 69.2 percent higher than the March 2016 billings level of $1.20 billion.

“March billings reached robust levels not seen since March 2001,” said Dan Tracy, senior director, Industry Research and Statistics, SEMI. “The equipment industry is clearly benefiting from the latest semiconductor investment cycle.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Year-Over-Year

 October 2016

$1,630.4

20.0%

 November 2016

$1,613.3

25.2%

 December 2016

$1,869.8

38.5%

 January 2017

$1,859.4

52.3%

 February 2017 (final)

$1,974.0

63.9%

 March 2017 (prelim)

$2,026.2

69.2%

Source: SEMI (www.semi.org), April 2017

SEMI ceased publishing the monthly North America Book-to-Bill report in January 2017. SEMI will continue publish a monthly North American Billings report and issue the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions.

ClassOne Technology (classone.com), manufacturer of budget-friendly Solstice plating systems, announced it’s new CopperMax chamber — a design that is demonstrating major copper plating cost reductions for users of ≤200mm wafers.

ClassOne cited actual performance data from a CopperMax pilot installation on a Solstice tool at a Fortune 100 customer. Over a six-month period the customer tracked their actual production operating costs while using the new chamber for copper TSV, Damascene and high-rate copper plating. For the three processes with CopperMax they reported that operating costs were reduced between 95.8% and 98.4% compared with previously used conventional plating chambers.

“Many of our emerging market customers are starting to do copper plating,” said Kevin Witt, President of ClassOne Technology. “So we’ve spent a lot of time on the process, working to reduce customer costs and also increase performance. And the new CopperMax chamber is proving to do both.”

ClassOne pointed out that consumables are the largest cost factor in copper plating. Optimizing copper plating generally requires the use of expensive organic additives — which are consumed very rapidly and need to be replenished frequently.

CopperMax chamber

“We learned, however, that over 97% of those expensive additives were not being consumed by the actual plating process,” said Witt. “Most were being used up simply by contact with the anode throughout the process! So, we designed our new copper chamber specifically to keep additives away from the anode — and the results are pretty dramatic. Significant savings can be realized by high- and medium-volume users with high throughputs as well as by lower-volume and R&D users that have long idle times.”

The company explained that the CopperMax chamber employs a cation-exchange semipermeable membrane to divide the copper bath into two sections. The upper section contains all of the additives, and it actively plates the wafer. The lower section of the bath contains the anode that supplies elemental copper — which is able to travel through the membrane and into the upper section to ultimately plate the wafer. However, the membrane prevents additives from traveling down to the anode, where they would break down and form process-damaging waste products.

As a result, the CopperMax bath remains much cleaner, and bath life is extended by over 20x. This increases uptime, enables higher-quality, higher-rate Cu plating, and it reduces cost of ownership very substantially.

For example, a customer using a Solstice system with six CopperMax chambers and running TSV and high-rate copper plating will save over $300,000 per year just from additive use reductions.

In addition, the CopperMax also reduces Cu anode expenses. The chamber is designed to use inexpensive bulk anode pellets instead of solid machined Cu material, which cuts anode costs by over 50%. And since the pellets have 10x greater surface area they also increase the allowable plating rates.

“Like the rest of our equipment, this new chamber aims to serve all those smaller wafer users who have limited budgets,” said Witt. “Simply stated, CopperMax is going to give them a lot more copper plating performance for a lot less.”

Solstice plating system

Worldwide semiconductor wafer-level manufacturing equipment (WFE) revenue totaled $37.4 billion in 2016, an 11.3 percent increase from 2015, according to final results by Gartner, Inc. The top 10 vendors accounted for 79 percent of the market, up 2 percent from 2015.

“Spending on 3D NAND and leading-edge logic process drove growth in the market in 2016,” said Takashi Ogawa, research vice president at Gartner. “This spending was driven by momentum for high-end services in data centers and requirements for faster processors and high-volume memory for mobile devices.”

Applied Materials continued to lead the WFE market with 20.5 percent growth in 2016 (see Table 1). The active investment in 3D device manufacturing provided significant momentum in Applied’s etch revenue, specifically in the conductor etch segment. Screen Semiconductor Solutions experienced the highest growth in the market, with 41.5 percent. This was due to a combination of the appreciation of the Japanese Yen against the U.S. dollar, which elevated dollar-based sales estimates and the demand in premium smartphone and data center servers for big data analysis that drove investment in 3D-NAND capacity and leading-edge technology in foundries.

Table 1

Top 10 Companies’ Revenue From Shipments of Total Wafer-Level Manufacturing Equipment, Worldwide (Millions of U.S. Dollars)

Rank 2015

Rank 2014

Vendor

2016 Revenue

2016 Market Share (%)

2015

Revenue

2015 Market Share (%)

2015-2016 Growth (%)

1

1

Applied Materials

7,736.9

20.7

6,420.2

19.1

20.5

2

4

Lam Research

5,213.0

13.9

4,808.3

14.3

8.4

3

2

ASML

5,090.6

13.6

4,730.9

14.1

7.6

4

3

Tokyo Electron

4,861.0

13.0

4,325.0

12.9

12.4

5

5

KLA-Tencor

2,406.0

6.4

2,043.2

6.1

17.8

6

6

Screen Semiconductor Solutions

1,374.9

3.7

971.5

2.9

41.5

7

7

Hitachi High-Technologies

980.2

2.6

788.3

2.3

24.3

8

8

Nikon

731.5

2.0

724.2

2.2

1.0

9

9

Hitachi Kokusai

528.4

1.4

633.8

1.9

-16.6

10

13

ASM International

496.9

1.3

582.5

1.7

-14.7

Others

7,988.0

21.4

7,586.2

22.6

5.3

Total Market

37,407.3

100.0

33,613.7

100

11.3

Source: Gartner (April 2017)

Additional information is provided in the Gartner report “MarketShare: SemiconductorWaferFab Equipment, Worldwide, 2016.” The report provides rankings and market share for the top 10 vendors. In 2015, Gartner changed the segment reporting to focus on wafer-level manufacturing and is no longer providing segment details for die-level packaging or automatic test. This report is limited to wafer-level manufacturing equipment.

Brewer Science announced the achievement of Zero Waste to Landfill Certification for the second consecutive year. GreenCircle Certified, LLC (GreenCircle), has completed extensive audits to verify that the Rolla and Vichy Brewer Science manufacturing locations contribute zero waste to landfills. The certification is valid through 2017 and can be viewed in GreenCircle’s Certified Product Database.

Brewer Science is regarded as a champion for environmental responsibility in the microelectronics and semiconductor industry and is the only business in the industry to achieve Zero Waste to Landfill Certification through GreenCircle. Brewer Science remains committed to a robust environmental management system with the objective of preventing pollution of the environment and providing a healthy, safe, and secure workplace.

For many years Brewer Science leadership has made it a priority to lead an environmentally responsible organization. Some of the initiatives include:

  • In 2002, Brewer Science instituted a mini-bin recycling program, a simple step that had a huge impact. To date, over 597 tons of waste have been recycled.
  • At its headquarters in Rolla, Missouri, Brewer Science promotes a community collection program. Through partnering with waste disposal companies and volunteer crews, they have collected more than 800,000 pounds of appliances, electronics, and tires that would have otherwise been a part of a landfill.
  • In 2015, a giant trash compactor known as “Big Blue” found a home in Brewer Science’s Rolla facility. Big Blue collects and compacts tons of non-recyclable waste and sends it to a waste-to-energy facility. The waste is combusted to produce enough electricity to power four houses for a month.
  • Brewer Science also diverts some of its waste into fuel blending processes, resulting in the conversion of over 520,000 pounds of waste into fuel that can replace natural gas and coal.

Samsung Electronics Co., Ltd. announced today that its second generation 10-nanometer (nm) FinFET process technology, 10LPP (Low Power Plus), has been qualified and is ready for production. With further enhancement in 3D FinFET structure, 10LPP allows up to 10-percent higher performance or 15-percent lower power consumption compared to the first generation 10LPE (Low-Power Early) process with the same area scaling.

Samsung was the first in the industry to begin mass production of system-on-chips (SoCs) products on 10LPE last October. The latest Samsung Galaxy S8 smartphones are powered by some of these SoCs.

To meet long-term demand for the 10nm process for a wide range of customers, Samsung has started installing production equipment at its newest S3-line in Hwaseong, Korea. The S3-line is expected to be ready for production by the fourth quarter of this year.

“With our successful 10LPE production experience, we have commenced production of the 10LPP to maintain our leadership in the advanced-node foundry market,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “10LPP will be one of our key process offerings for high performance mobile, computing and network applications, and Samsung will continue to offer the most advanced logic process technology.”

In 2016, annual global semiconductor sales reached their highest-ever point, at $339 billion worldwide. In that same year, the semiconductor industry spent about $7.2 billion worldwide on wafers that serve as the substrates for microelectronics components, which can be turned into transistors, light-emitting diodes, and other electronic and photonic devices.

A new technique developed by MIT engineers may vastly reduce the overall cost of wafer technology and enable devices made from more exotic, higher-performing semiconductor materials than conventional silicon.

The new method, reported today in Nature, uses graphene — single-atom-thin sheets of graphite — as a sort of “copy machine” to transfer intricate crystalline patterns from an underlying semiconductor wafer to a top layer of identical material.

The engineers worked out carefully controlled procedures to place single sheets of graphene onto an expensive wafer. They then grew semiconducting material over the graphene layer. They found that graphene is thin enough to appear electrically invisible, allowing the top layer to see through the graphene to the underlying crystalline wafer, imprinting its patterns without being influenced by the graphene.

Graphene is also rather “slippery” and does not tend to stick to other materials easily, enabling the engineers to simply peel the top semiconducting layer from the wafer after its structures have been imprinted.

Jeehwan Kim, the Class of 1947 Career Development Assistant Professor in the departments of Mechanical Engineering and Materials Science and Engineering, says that in conventional semiconductor manufacturing, the wafer, once its crystalline pattern is transferred, is so strongly bonded to the semiconductor that it is almost impossible to separate without damaging both layers.

“You end up having to sacrifice the wafer — it becomes part of the device,” Kim says.

With the group’s new technique, Kim says manufacturers can now use graphene as an intermediate layer, allowing them to copy and paste the wafer, separate a copied film from the wafer, and reuse the wafer many times over. In addition to saving on the cost of wafers, Kim says this opens opportunities for exploring more exotic semiconductor materials.

“The industry has been stuck on silicon, and even though we’ve known about better performing semiconductors, we haven’t been able to use them, because of their cost,” Kim says. “This gives the industry freedom in choosing semiconductor materials by performance and not cost.”

Kim’s research team discovered this new technique at MIT’s Research Laboratory of Electronics. Kim’s MIT co-authors are first author and graduate student Yunjo Kim; graduate students Samuel Cruz, Babatunde Alawonde, Chris Heidelberger, Yi Song, and Kuan Qiao; postdocs Kyusang Lee, Shinhyun Choi, and Wei Kong; visiting research scholar Chanyeol Choi; Merton C. Flemings-SMA Professor of Materials Science and Engineering Eugene Fitzgerald; professor of electrical engineering and computer science Jing Kong; and assistant professor of mechanical engineering Alexie Kolpak; along with Jared Johnson and Jinwoo Hwang from Ohio State University, and Ibraheem Almansouri of Masdar Institute of Science and Technology.

Graphene shift

Since graphene’s discovery in 2004, researchers have been investigating its exceptional electrical properties in hopes of improving the performance and cost of electronic devices. Graphene is an extremely good conductor of electricity, as electrons flow through graphene with virtually no friction. Researchers, therefore, have been intent on finding ways to adapt graphene as a cheap, high-performance semiconducting material.

“People were so hopeful that we might make really fast electronic devices from graphene,” Kim says. “But it turns out it’s really hard to make a good graphene transistor.”

In order for a transistor to work, it must be able to turn a flow of electrons on and off, to generate a pattern of ones and zeros, instructing a device on how to carry out a set of computations. As it happens, it is very hard to stop the flow of electrons through graphene, making it an excellent conductor but a poor semiconductor.

Kim’s group took an entirely new approach to using graphene in semiconductors. Instead of focusing on graphene’s electrical properties, the researchers looked at the material’s mechanical features.

“We’ve had a strong belief in graphene, because it is a very robust, ultrathin, material and forms very strong covalent bonding between its atoms in the horizontal direction,” Kim says. “Interestingly, it has very weak Van der Waals forces, meaning it doesn’t react with anything vertically, which makes graphene’s surface very slippery.”

Copy and peel

The team now reports that graphene, with its ultrathin, Teflon-like properties, can be sandwiched between a wafer and its semiconducting layer, providing a barely perceptible, nonstick surface through which the semiconducting material’s atoms can still rearrange in the pattern of the wafer’s crystals. The material, once imprinted, can simply be peeled off from the graphene surface, allowing manufacturers to reuse the original wafer.

The team found that its technique, which they term “remote epitaxy,” was successful in copying and peeling off layers of semiconductors from the same semiconductor wafers. The researchers had success in applying their technique to exotic wafer and semiconducting materials, including indium phosphide, gallium arsenenide, and gallium phosphide — materials that are 50 to 100 times more expensive than silicon.

Kim says that this new technique makes it possible for manufacturers to reuse wafers — of silicon and higher-performing materials — “conceptually, ad infinitum.”

An exotic future

The group’s graphene-based peel-off technique may also advance the field of flexible electronics. In general, wafers are very rigid, making the devices they are fused to similarly inflexible. Kim says now, semiconductor devices such as LEDs and solar cells can be made to bend and twist. In fact, the group demonstrated this possibility by fabricating a flexible LED display, patterned in the MIT logo, using their technique.

“Let’s say you want to install solar cells on your car, which is not completely flat — the body has curves,” Kim says. “Can you coat your semiconductor on top of it? It’s impossible now, because it sticks to the thick wafer. Now, we can peel off, bend, and you can do conformal coating on cars, and even clothing.”

Going forward, the researchers plan to design a reusable “mother wafer” with regions made from different exotic materials. Using graphene as an intermediary, they hope to create multifunctional, high-performance devices. They are also investigating mixing and matching various semiconductors and stacking them up as a multimaterial structure.

“Now, exotic materials can be popular to use,” Kim says. “You don’t have to worry about the cost of the wafer. Let us give you the copy machine. You can grow your semiconductor device, peel it off, and reuse the wafer.”

3D-Micromac AG, a developer of laser micromachining and roll-to-roll laser systems for the photovoltaic, medical device and electronics markets, today announced that the total received order volume for its microCELL TLS high-throughput half-cell cutting tools tops 1.5 GW for tool deliveries in 2017 to date.

The microCELL TLS systems use Thermal Laser Separation for cleaving solar cells into half-cells. This process provides a multitude of mechanical and electrical benefits to customers. The separated cells show a significantly higher mechanical strength, better edge quality as well as lower power reduction compared to laser scribing and cleaving approaches. A module power gain of more than 1 W was seen with TLS compared to conventional scribe and break methods, in addition to the 5-7 W per module gain of half-cell module technology.

Further cementing its position as the market leader for laser systems in photovoltaics,
3D-Micromac also yesterday introduced its second-generation microCELL OTF system, the high-performance production solution for Laser Contact Opening (LCO) of Passivated Emitter Rear Contact (PERC) solar cells, which achieves a world-class throughput of 8,000 wafers per hour.

Scientists at the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) have developed a proof-of-principle photoelectrochemical cell capable of capturing excess photon energy normally lost to generating heat.

Using quantum dots (QD) and a process called Multiple Exciton Generation (MEG), the NREL researchers were able to push the peak external quantum efficiency for hydrogen generation to 114 percent. The advancement could significantly boost the production of hydrogen from sunlight by using the cell to split water at a higher efficiency and lower cost than current photoelectrochemical approaches.

Details of the research are outlined in the Nature Energy paper Multiple exciton generation for photoelectrochemical hydrogen evolution reactions with quantum yields exceeding 100%, co-authored by Matthew Beard, Yong Yan, Ryan Crisp, Jing Gu, Boris Chernomordik, Gregory Pach, Ashley Marshall, and John Turner. All are from NREL; Crisp also is affiliated with the Colorado School of Mines, and Pach and Marshall are affiliated with the University of Colorado, Boulder.

Beard and other NREL scientists in 2011 published a paper in Science that showed for the first time how MEG allowed a solar cell to exceed 100 percent quantum efficiency by producing more electrons in the electrical current than the amount of photons entering the solar cell.

“The major difference here is that we captured that MEG enhancement in a chemical bond rather than just in the electrical current,” Beard said. “We demonstrated that the same process that produces extra current in a solar cell can also be applied to produce extra chemical reactions or stored energy in chemical bonds.”

The maximum theoretical efficiency of a solar cell is limited by how much photon energy can be converted into usable electrical energy, with photon energy in excess of the semiconductor absorption bandedge lost to heat. The MEG process takes advantages of the additional photon energy to generate more electrons and thus additional chemical or electrical potential, rather than generating heat. QDs, which are spherical semiconductor nanocrystals (2-10 nm in diameter), enhance the MEG process.

In current report, the multiple electrons, or charge carriers, that are generated through the MEG process within the QDs are captured and stored within the chemical bonds of a H2 molecule.

NREL researchers devised a cell based upon a lead sulfide (PbS) QD photoanode. The photoanode involves a layer of PbS quantum dots deposited on top of a titanium dioxide/fluorine-doped tin oxide dielectric stack. The chemical reaction driven by the extra electrons demonstrated a new direction in exploring high-efficiency approaches for solar fuels.

At SEMICON Southeast Asia 2017, Dr. Chen Fusen, CEO of Kulicke & Soffa Pte Ltd, Singapore, will give a keynote on digital transformation in the manufacturing sector. Chen believes that Smart Manufacturing, or Industry 4.0, is no longer hype but real, and Asia needs to get on board sooner rather than later. SEMICON Southeast Asia (SEA) 2017, held at the SPICE arena in Penang on 25-27 April, is Asia’s premier showcase for electronics manufacturing innovation.

“Digital transformation has proven to provide solutions for addressing challenges in the manufacturing industry but there is still the issue of acceptance as well as lack of skills and knowledge that needs to be addressed,” said Chen. “With disruptive technology changing our world, I expect that more companies will see the value of their investments realised as this technology accelerates the creation of more individualised products and services.”

Dr. Hai Wang from NXP Semiconductors Singapore Pte Ltd agreed that more consumer-related innovations would stem from digital transformation as demand for solutions that provide efficiency and security increases. “At NXP, we look at developing advanced cyber security solutions for the automotive industry, such as tracking and analysing intelligence around connected and automated vehicles, which will help to counter any adverse threats in real time. These innovations are real and will soon mark a shift in the future of automation and manufacturing. It is vital that we embrace the change and adapt accordingly,” he said.

Other speakers at SEMICON SEA also feel strongly about the importance of Smart Manufacturing and digital transformation. David Chang of HTC Corporation, Taiwan, sees a dramatic shift in the value of being a “smart” manufacturer to address to the rising demand in consumer products and services innovation. “We have seen virtual reality technology offered by products such as HTC VIVE(TM) really shaping the future of the world. Transformative innovations such as this will pave the way for disruptive technology to be coupled into business models to benefit consumers in the long term,” he said.

These three speakers will join a long list of thought leaders from the electronics manufacturing sector – including Jamie Metcalfe from Mentor Graphics U.S., Chiang Gai Kit from Omron Asia Pacific Singapore, Ranjan Chatterjee from Cimetrix U.S. and Duncan Lee from Intel Products Malaysia – to speak at SEMICON SEA 2017. Topics discussed will cover issues relevant to the transformation of the manufacturing industry ranging from next-generation manufacturing to system-level integration, including exhibitions that will highlight the market and technology trends that are driving investment and growth in all sectors across the region.

The conference also aims to champion regional collaboration through new business opportunities for customers and foster stronger cross-regional engagement through reaching buyers, engineers and key decision-makers in the Southeast Asia microelectronics industry, including buyers from Malaysia, Singapore, Thailand, Indonesia, the Philippines, and Vietnam.

Learn more about SEMICON Southeast Asia 2017 in Penang, Malaysia on 25-27 April: http://www.semiconsea.org/.

Worldwide semiconductor revenue is forecast to total $386 billion in 2017, an increase of 12.3 percent from 2016, according to Gartner, Inc. Favorable market conditions that gained momentum in the second half of 2016, particularly for commodity memory, have accelerated and raised the outlook for the market in 2017 and 2018. However, the memory market is fickle, and additional capacity in both DRAM and NAND flash is expected to result in a correction in 2019.

“While price increases for both DRAM and NAND flash memory are raising the outlook for the overall semiconductor market, it will also put pressure on margins for system vendors of smartphones, PCs and servers,” said Jon Erensen, research director at Gartner. “Component shortages, a rising bill of materials, and the prospect of having to counter by raising average selling prices (ASPs) will create a volatile market in 2017 and 2018.”

PC DRAM pricing has doubled since the middle of 2016. A 4GB module that cost $12.50 has jumped to just under $25 today. NAND flash ASPs increased sequentially in the second half of 2016 and the first quarter of 2017. Pricing for both DRAM and NAND is expected to peak in the second quarter of 2017, but relief is not expected until later in the year as content increases in key applications, such as smartphones, have vendors scrambling for supply.

“With memory vendors expanding their margins though 2017, the temptation will be to add new capacity,” said Mr. Erensen. “We also expect to see China make a concerted effort to join the memory industry, setting the market up for a downturn in 2019.”

Unit production estimates for premium smartphones, graphics cards, video game consoles and automotive applications have improved and contributed to the stronger outlook in 2017. In addition, electronic equipment with heavy exposure to DRAM and NAND flash saw semiconductor revenue estimates increase. This includes PCs, ultramobiles, servers and solid-state drives.

“The outlook for emerging opportunities for semiconductors in the Internet of Things (IoT) and wearable electronics remains choppy with these markets still in the early stages of development and too small to have a significant impact on overall semiconductor revenue growth in 2017,” said Mr. Erensen.