Category Archives: Wafer Processing

Kulicke & Soffa Industries, Inc. (NASDAQ: KLIC) announced today the opening of its latest Process and Applications laboratory at the K&S Netherlands facility.

The 180 square meter laboratory adds to the Company’s existing base of global application facilities. The Netherlands site uniquely houses a complete prototype assembly line of K&S Advanced Packaging and Electronics Assembly equipment. The laboratory will facilitate stronger collaboration with global customers and industry partners to develop and refine next-generation of packaging solutions in direct response to the industry’s emerging challenges and opportunities. It also serves as a platform to accelerate internal development roadmaps and engineering competencies.

Bob Chylak, Kulicke & Soffa’s Vice President of Global Process Engineering, said, “This new lab marks another significant milestone for K&S and further enhances our capabilities to deploy the latest technology for component mounting, with a specific focus on applications requiring high-accuracy placement for passive components as well as active bare or packaged die. We are excited to further collaborate strategically with customers and industry partners to optimize and drive high-volume adoption of new advanced packaging processes.”

Kulicke & Soffa is proud to welcome the Guest-of-Honor, Mayor John Jorritsma, City of Eindhoven, for the Opening Ceremony. “We are very pleased with the presence of K&S in Brainport Eindhoven. The company contributes a lot to our added value chain, by creating new knowledge and employment. The opening of the new process lab proves that K&S also believes in our economic strength, which is great”, said Mayor John Jorritsma, City of Eindhoven.

In addition to the K&S Netherlands facility, Kulicke & Soffa also operates application laboratories in Taiwan, Korea, China, Singapore and the US.

The Department of Mechanical Engineering of The Hong Kong Polytechnic University (PolyU) has developed a novel technology of embedding highly conductive nanostructure into semiconductor nanofiber. The novel composite so produced has superb charge conductivity, and can therefore be widely applied, especially in environmental arena.

The innovation was awarded the Gold Medal with Congratulations of the Jury at the 45th International Exhibition of Inventions of Geneva, held on 29 March to 2 April this year.

A research team led by Prof. Wallace Leung develops novel semiconductor nanotubes with superb charge conductivity which can be widely used in different applications, especially in environmental arena. (PRNewsfoto/The Hong Kong Polytechnic Univer)

A research team led by Prof. Wallace Leung develops novel semiconductor nanotubes with superb charge conductivity which can be widely used in different applications, especially in environmental arena. (PRNewsfoto/The Hong Kong Polytechnic Univer)

Issues to address

Semiconductor made into nanofiber of diameter as small as 60nm (less than 1/1,000 of a human hair) have been widely used in modern daily life photonic devices (such as solar cells, photocatalyst for cleaning the environment), and non-photonic devices (such as chemical-biological sensor, lithium battery). However, electrons and holes generated by light or energy in semiconductor would readily recombine, thus reduce the current or device effectiveness. Such nature has limited the further development and applications of semiconductor nanofibers.

The novel technology developed by the research team led by Ir. Professor Wallace Leung, Chair Professor of Innovative Products and Technologies of the Department, have overcome such limitation. Applying electrospinning, the team succeeds in inserting highly conductive nano-structure (such as carbon nanotubes, graphene) into semiconductor nanofiber (such as Titanium Dioxide (TiO2 ). The novel nano-composite so produced thus provides a dedicated super-highway for electron transport, eliminating the problem of electron-hole recombination.

Amidst the potentially wide applications of the innovation in many spectrum, Professor Leung’s team has initially embarked on research of applying the novel nano-composite in two environmental aspects: solar cells, and photocatalysts for cleaning air.

Enhanced solar cell efficiency

The latest generation of solar cells (e.g. dye sensitized solar cell (DSSC), perovskite solar cell) are promising clean and renewable energy sources. Yet, for more wide applications, there are still much room for further enhancing their power conversion efficiency and producing in more cost-efficient ways.

By applying PolyU’s novel technology, carbon nanotube/graphene is embedded into the TiO2 component of DSSC and perovskite solar cell, boosting an increase of energy conversion from 40-66%. Compared to commercially available multi-crystalline silicon solar cell common in the market, with current price at US$0.25 (HK$1.94)/kWh, the cost of DSSC with carbon nanotube embedded is 12-32% higher (HK$2.18 – 2.56); while perovskite solar cell embedded with graphene is 28-40% lower (HK$1.17 – 1.40).

Given the superb charge conductivity of the novel semiconductor nanofiber, there is great potential for prompt development of more efficient solar cells, and at lower cost, than the silicon cells.

Enhanced photocatalyst performance in cleaning the air

TiO2 is the most commonly used photocatalyst material in commercially available air-purifying or disinfection devices in the market. However, TiO2 can only be activated by ultraviolet light (i.e. about 6% of solar energy), thus limiting its wider application as it is less effective in indoor environment. It is also relatively ineffective in converting nitric oxide (NO) into nitrogen dioxide (NO2), at a rate of less than 5%.

By applying PolyU’s novel technology, graphene roll is embedded into TZB composite (which mainly compose of TiO2). The novel semiconductor nanofiber so produced has superb conductivity, which provides a graphene superhighway for electrons to transport more quickly to oxide the absorbed pollutants. The technology also significantly increases the novel nano-fiber’s surface exposed for light absorption and trapping harmful molecules.

Such novel semiconductor nanofiber can convert about 90% of NO to NO2, a 35% increase compared to composite without graphene. If compared to high-standard TiO2 nano-particles commonly available in the market, the conversion rate is even 10 times more, yet 10 times more cost-efficient.

Readily available for wide applications

Given the wide uses of semiconductor nanofiber now and in the future, the PolyU groundbreaking technology that develops semiconductor nanofiber with superb charge conductivity has great potential for further development for different applications.

Besides in solar cells and photocatalysts, other obvious examples of making use of such novel technology include the development of biological-chemical sensors with enhanced sensitivity and sensing speed, and lithium batteries with lower impedance and increased storage.

Silicon Integration Initiative, Inc. (Si2), a integrated circuit research and development joint venture, has contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at creating a standardized means for modeling systems-on-chip (SoC) designed for lower power consumption.

Jerry Frenkil, Si2 director of OpenStandards, said that the Si2 Low Power Working Group developed the new technology to fill several holes in the flow for estimating and controlling SoC power consumption. “This new modeling technology provides accurate and efficient, early estimation of both static and dynamic power, including critical temperature dependencies, using a consistent model throughout the design flow. There’s currently no standard way to represent power data for use at the system level, especially across a range of process, voltage and temperature points in a single model.”

IEEE P2416 is an essential component of IEEE’s coordinated effort to improve system-level design. This effort also includes the IEEE 1801 standard, which expresses design intent. Its latest update, IEEE 1801-2015, includes support for power-state modeling. “P2416 provides power data representations to complement 1801 power-state modeling. Together, 1801 and 2416 will form a complete power model for hardware IP at any level of abstraction,” Frenkil added.

Organizations that contributed to the model development are: ANSYS, Cadence, Intel, IBM, Entasys, and North Carolina State University.

Nagu Dhanwada, senior technical staff member at IBM, chairs both the IEEE P2416 and Si2 Power Modeling Working Groups. According to Dhanwada, “This is a major contribution to the P2416 effort. As the first technology contribution to the P2416 Working Group, it’s expected to form a solid foundation for the resulting standard.”

“This new modeling technology is the first significant advance in power modeling in quite a long time,” said Paul Traynar, technical fellow at ANSYS and a contributor to the Si2 effort. “It will enable SoC designers to get consistent power estimates across design abstractions and especially early in the system design process.”

Julien Sebot, CPU architect at Intel and a member of the IEEE P2416 Working Group, added, “The Si2 contribution addresses the top priorities identified by the P2416 Working Group. The ability to create accurate, early estimates and to reuse and refine those estimates during the design process is essential in creating energy efficient systems-on-chip. Si2’s contribution is a major step toward addressing that need.”

The IEEE P2416 Working Group has already started reviewing the Si2 contribution. In parallel, Si2 will further develop, for its members, the technology with expanded model semantics, proof-of-concept demonstrations, and reference design implementations.

This model and its use will be described as part of a DAC 2017 tutorial, “How Power Modeling Standards Power Your Designs,” Monday, June 19, 3:30-5:00 p.m., Room 18AB, Austin Convention Center.

MagnaChip Semiconductor Corporation (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, announced today that it will host its Annual U.S. Foundry Technology Symposium at Hilton Santa Clara, California, on June 7th, 2017.

The primary purpose of the Foundry Technology Symposium is to showcase MagnaChip’s most up-to-date technology offerings and to provide an in-depth understanding of MagnaChip’s manufacturing capabilities, its specialty technology processes, target applications and end-markets. Furthermore, during the symposium, MagnaChip plans to discuss current and future semiconductor foundry business trends, and also cover presentations in key markets through guest speeches.

While providing an in-depth overview of its specialty processes, MagnaChip will also highlight its technology portfolio and its future roadmap, including technologies such as mixed-signal, which supports applications in the Internet of Things (IoT) and RF switch sector and Bipolar-CMOS-DMOS (BCD) for high-performance analog and power management applications. In addition, MagnaChip will also feature applications regarding Ultra-High Voltage (UHV), such as LED lighting and AC-DC chargers, and cover Non-Volatile Memory (NVM)-related technologies, such as Touch IC, Automotive MCUs and other customer specific applications. Furthermore, MagnaChip will present its technologies used in applications including smartphones, tablet PCs, automotive, industrial, LED lighting and the wearables segments. MagnaChip will also review its customer-friendly design environment and an on-line customer service tool known as “iFoundry.”

“We are very pleased to host MagnaChip’s Annual Foundry Technology Symposium in the US again this year,” said YJ Kim, Chief Executive Officer of MagnaChip. “We plan to offer participants an opportunity to better understand the foundry and the application market dynamics, and to provide insights into MagnaChip’s specialty process technologies.” MagnaChip has approximately 466 proprietary process flows it can utilize and offer to its foundry customers.

SEMI, the global industry association representing the electronics manufacturing supply chain, today announced that the worldwide semiconductor photomask market was $3.32 billion in 2016 and is forecasted to reach $3.57 billion in 2018. After increasing 1 percent in 2015, the photomask market increased 2 percent in 2016. The mask market is expected to grow 4 and 3 percent in 2017 and 2018, respectively, according to the SEMI report. Key drivers in this market continue to be advanced technology feature sizes (less than 45nm) and increased manufacturing in Asia-Pacific. Taiwan remains the largest photomask regional market for the sixth year in a row and is expected to be the largest market for the duration of the forecast.

Revenues of $3.32 billion place photomasks at 13 percent of the total wafer fabrication materials market, behind silicon and semiconductor gases. By comparison, SEMI reports that photomasks represented 18 percent of the total wafer fabrication materials market in 2003. Another trend highlighted in the report is the increasing importance of captive mask shops. Captive mask shops, aided by intense capital expenditures in 2011 and 2012 continue to gain market share at merchant suppliers’ expense. Captive mask suppliers accounted for 63 percent of the total photomask market last year, up from 56 percent in 2015. Captive mask shops represented 31 percent of the photomask market in 2003.

A recent published SEMI report, 2016 Photomask Characterization Summary, provides details on the 2016 Photomask Market for seven regions of world including North America, Japan, Europe, Taiwan, Korea, China, and Rest of World. The report also includes data for each of these regions from 2003 to 2018 and summarizes lithography developments over the past year.

Analogix Semiconductor, Inc. and Beijing Shanhai Capital Management Co, Ltd. (Shanhai Capital), today jointly announced the completion of the approximately $500 million acquisition of Analogix Semiconductor. China Integrated Circuit Industry Investment Fund Co., Ltd. (China IC Fund) joined Shanhai Capital’s fund as one of the limited partners.

“We are very pleased to have completed the transaction,” said Dr. Kewei Yang, Analogix Semiconductor’s chairman and CEO. “Enhanced by the strong financial support of our new investors, Analogix’s future is brighter than ever. We are excited to continue building and growing Analogix into a global leader in high-performance semiconductors.”

“As Analogix’s key financial partner and investor, we look forward to leveraging our resources to accelerate the company’s growth into new markets,” said Mr. Xianfeng Zhao, Chairman of Shanhai Capital. “We will build on the strength of the company’s core technology and customer relationships to create an exceptional semiconductor company that will be publicly listed in China.”

Sino-American International Investment Ltd, and Needham & Company, LLC served as financial advisors to Analogix Semiconductor. O’Melveny & Myers LLP served as legal counsel to Analogix Semiconductor.

Pillsbury Winthrop Shaw Pittman LLP and Jingtian & Gongcheng acted as legal counsel to Beijing Shanhai Capital Management Co.

IHS Markit (Nasdaq: INFO) announced that the worldwide semiconductor market showed signs of recovery in 2016 following a down year in 2015. In 2016, the market posted a year-end growth rate of 2 percent with chip growth seen across multiple market segments. Global revenue came in at $352.4 billion, up from $345.6 billion in 2015.

Key growth drivers

Key drivers of this growth were DRAM and NAND flash memory, which grew more than 30 percent collectively in the second half of 2016. Key to this turnaround was supply constraints and strong demand, coupled with an ASP increase. We expect these factors to drive memory revenue into record territory throughout 2017.

Semiconductors used for automotive applications were also a key driver of 2016 growth, with a 9.7 percent expansion by year-end. Chip content in cars continues to climb, with micro components and memory integrated circuits (IC) leading the pack, both experiencing over 10 percent growth in automotive applications.

“The strong component demand that drove record capital expenditures in 2016 also provided the industry with advanced technology platforms which will support further semiconductor revenue growth in 2017,” said Len Jelinek, Senior Director and Chief Analyst for Semiconductor Manufacturing at IHS Markit.

Continued consolidation

Continuing a recent trend, the semiconductor market saw another year of intense consolidation with no signs of slowing down. The year began with the close of the biggest-ever acquisition in the semiconductor industry. Avago Technologies finalized its $37 billion acquisition of Broadcom Corp. to form Broadcom Limited, which jumped to rank fourth in terms of market share (Avago previously ranked 11th). This acquisition resulted in the newly formed company increasing its market share in several market segments, including taking a large lead in the wired application market.

“After some selective divestiture, Broadcom Limited has focused on market segments where its customer base holds dominant market share positions. These also tend to be markets which have fairly stable and visible TAM growth,” said Senior Analyst Brad Shaffer. “These characteristics may help entrench the company’s market share positions in areas where it chooses to compete,” added Shaffer.

Among the top 20 semiconductor suppliers, ON Semiconductor and nVidia enjoyed the largest revenue growth, followed closely by MediaTek. ON and MediaTek achieved growth through multiple acquisitions, while nVidia saw an enormous demand for its GPU technology as it moves into new markets and applications.

Qualcomm remained the top fabless company in 2016 while MediaTek and nVidia moved into the number two and three spots, respectively. The fabless company with the largest market share gain was Cirrus Logic, a major supplier for Apple and Samsung mobile phones. They moved up five spots in 2016, to number 10.

Intel remains in the number one spot for semiconductor suppliers, followed by Samsung. Qualcomm comes in at number three, with plans to increase its market share in 2017 with its pending acquisition of NXP.

Find more information on this topic in the latest release of the Competitive Landscaping Tool from the Semiconductors & Components service at IHS Markit.

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced the release of the new Virtuoso Advanced-Node Platform supporting advanced 7nm designs. Through collaboration with early 7nm FinFET customers, Cadence has expanded the Virtuoso custom design platform with innovative new capabilities to manage design complexity and process effects introduced with this advanced-node process. The Virtuoso Advanced-Node Platform update supports all major advanced FinFET technologies with proven results, while improving designer productivity at 7nm.

To address the many technical challenges of 7nm design, the Virtuoso Advanced-Node Platform offers a variety of layout capabilities, including advanced editing with multi-pattern color awareness, FinFET grids, and module generator (ModGen) device arrays. Additionally, customers can take advantage of variation analysis in their circuit design flows utilizing Monte Carlo analysis across corners to address variability with the Spectre® Accelerated Parallel Simulator, the Virtuoso ADE Product Suite and the Virtuoso Schematic Editor.

“As a leader in mobile computing, we require the highest performance, lowest power and highest density possible to deliver innovative, advanced-node designs,” said Ching San Wu, general manager of Analog Design and Circuit Technology at MediaTek. “Through our strong collaboration and continued partnership with Cadence, we have been able to develop and deploy a custom design methodology based on the Virtuoso Advanced-Node Platform. With our recent successful tapeout, we took advantage of its many unique capabilities designed to manage the challenges presented at 7nm.”

Key features in the updated Virtuoso Advanded-Node Platform include:

  • Multi-patterning and color-aware layout: Provides essential new support of a variety of fully colored “multi-patterned” custom design flows, which are a baseline requirement for the 7nm process and enable users to be more productive in their designs.
  • ModGen device arrays: Offers designers a set of modules that have been co-developed in close collaboration with key partners to improve designer productivity and mitigate layout complexities at the 7nm process node.
  • Automated FinFET placement: Provides automatic FinFET grid placement that simplifies the overall FinFET-based coloring design methodologies needed at 7nm. By adhering to 7nm process constraints, the Virtuoso Advanced-Node Platform greatly simplifies layout creation and minimizes errors that can be pervasive when designing at 7nm, while decreasing layout design time by up to 50 percent on custom digital and analog blocks.
  • Variation analysis: Enables high-performance Monte Carlo analysis targeting FinFET technology and high-sigma analysis, which can reduce the overall time to run simulations by a factor of 10.

“Through constant innovation and strategic partnerships with industry leaders, Cadence has solidified its leading role in providing advanced-node custom design tools,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “Through our extensive work with customers such as MediaTek, we’ve been able to validate that our approaches greatly reduce the overhead inherent in designing at 7nm in order to help deliver the best possible silicon. We currently have many customers that have completed successful tapeouts and delivered production designs using the Virtuoso Advanced-Node Platform.”

Ultratech, Inc. (Nasdaq: UTEK), a supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HBLEDs), as well as atomic layer deposition (ALD) systems, today announced that it has received multiple commitments for its LM7 laser melt anneal system. After its recent introduction in Q416, two leading North American semiconductor manufacturers will target use of the LM7 melt system at 7nm and below nodes. Ultratech plans to ship both systems in the first half of 2017 to the customers’ facilities in the U.S.

As the industry faces the challenges of device manufacturing at 7nm and below, laser melt anneal technology has received attention as a solution not only for front-end-of-line, but also for middle- and back-end-of-line applications.  In particular, scaling at these nodes has resulted in scrutiny of the contact structure between the transistor and the first metal layer. The focus is not solely on the transistor device performance, but issues related to the resistance at the contact, which are becoming a limiting factor in the operation of the transistor, increasing drive current and limiting overall speed. A paper presented in December at the 2016 IEEE International Electron Devices Meeting (IEDM), which used Ultratech’s laser melt anneal system, provided data to support the system’s capability to enable contact scaling consistent with transistor performance targets for the 7-nm node and beyond.

“As we continue to scale to smaller nodes, contact resistance is widely acknowledged to be one of the gating issues that must be addressed,” said Yun Wang, Ph.D., Senior Vice President and Chief Technologist, Laser Processing at Ultratech. “Ultratech’s laser melt anneal technology addresses emerging annealing requirements for 7nm and beyond, with applications spanning the front end where the focus is on device performance and leakage improvement, the middle-of-line for contact resistance, and at the back-end-of-line where the focus is on material modifications and reduction of resistive capacitive (RC) delay. Over the last few years, Ultratech has been engaged with multiple customers on all of these applications, running wafers at our facility using our laser melt anneal technology. We look forward to working with these two customers and to providing our laser melt technology to meet their aggressive technology roadmaps.”

Ultratech LM7 Laser Melt Annealing System
The LM7 laser melt annealing system is based on the production-proven LSA201 laser spike anneal platform with ambient control. Built on this proven hardware/software platform, the LM7 provides a novel solution for melt annealing applications for 7nm and below nodes. The LM7 uses a unique dual-laser process that provides nanosecond-scale melt anneal with reduced pattern effects compared to conventional melt anneal approaches.  Ultratech’s LM7 laser melt anneal system provides the industry with a low cost-of-ownership solution for advanced annealing requirements for high-volume manufacturing at 7nm and beyond.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $30.4 billion for the month of February 2017, an increase of 16.5 percent compared to the February 2016 total of $26.1 billion. Global sales in February were 0.8 percent lower than the January 2017 total of $30.6 billion, exceeding normal seasonal market performance. February marked the global market’s largest year-to-year growth since October 2010. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry has posted strong sales early in 2017, with memory products like DRAM and NAND flash leading the way,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Year-to-year sales increased by double digits across most regional markets, with the China and Americas markets showing particularly strong growth. Global market trends are favorable for continuing sales growth in the months ahead.”

Year-to-year sales increased across all regions: China (25.0 percent), the Americas (19.1 percent), Japan (11.9 percent), Asia Pacific/All Other (11.2 percent), and Europe (5.9 percent). Month-to-month sales increased modestly in Asia Pacific/All Other (0.5 percent) but decreased slightly across all others: Europe (-0.6 percent), Japan (-0.9 percent), China (-1.0 percent), and the Americas (-2.3 percent).

Neuffer also noted the recent growth of foreign semiconductor markets is a reminder of the importance of expanding U.S. semiconductor companies’ access to global markets, which is one of SIA’s policy priorities for 2017. The U.S. industry accounts for nearly half of the world’s total semiconductor sales, and more than 80 percent of U.S. semiconductor company sales are to overseas markets, helping make semiconductors one of America’s top exports.

February 2017

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

6.13

5.99

-2.3%

Europe

2.84

2.82

-0.6%

Japan

2.79

2.77

-0.9%

China

10.15

10.05

-1.0%

Asia Pacific/All Other

8.72

8.76

0.5%

Total

30.64

30.39

-0.8%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.03

5.99

19.1%

Europe

2.66

2.82

5.9%

Japan

2.47

2.77

11.9%

China

8.04

10.05

25.0%

Asia Pacific/All Other

7.88

8.76

11.2%

Total

26.08

30.39

16.5%

Three-Month-Moving Average Sales

Market

Sept/Oct/Nov

Dec/Jan/Feb

% Change

Americas

6.25

5.99

-4.2%

Europe

2.88

2.82

-2.3%

Japan

2.90

2.77

-4.6%

China

10.04

10.05

0.1%

Asia Pacific/All Other

8.94

8.76

-2.0%

Total

31.02

30.39

-2.0%