Category Archives: Wafer Processing

It would be difficult to overestimate the importance of silicon when it comes to computing, solar energy, and other technological applications. (Not to mention the fact that it makes up an awful lot of the Earth’s crust.) Yet there is still so much to learn about how to harness the capabilities of element number fourteen.

The most-common form of silicon crystallizes in the same structure as diamond. But other forms can be created using different processing techniques. New work led by Carnegie’s Tim Strobel and published in Physical Review Letters shows that one form of silicon, called Si-III (or sometimes BC8), which is synthesized using a high-pressure process, is what’s called a narrow band gap semiconductor.

What does this mean and why does it matter?

Metals are compounds that are capable of conducting the flow of electrons that makes up an electric current, and insulators are compounds that conduct no current at all. Semiconductors, which are used extensively in electronic circuitry, can have their electrical conductivity turned on and off–an obviously useful capability. This ability to switch conductivity is possible because some of their electrons can move from lower-energy insulating states to higher-energy conducting states when subjected to an input of energy. The energy required to initiate this leap is called a band gap.

The diamond-like form of silicon is a semiconductor and other known forms are metals, but the true properties of Si-III remained unknown until now. Previous experimental and theoretical research suggested that Si-III was a poorly conducting metal without a band gap, but no research team had been able to produce a pure and large enough sample to be sure.

By synthesizing pure, bulk samples of Si-III, Strobel and his team were able to determine that Si-III is actually a semiconductor with an extremely narrow band gap, narrower than the band gap of diamond-like silicon crystals, which is the most-commonly utilized kind. This means that Si-III could have uses beyond the already full slate of applications for which silicon is currently used. With the availability of pure samples, the team was able to fully characterize the electronic, optical, and thermal transport properties of Si-III for the first time.

“Historically, the correct recognition of germanium as a semiconductor instead of the metal it was once widely believed to be truly helped to start the modern semiconductor era; similarly, the discovery of semiconducting properties of Si-III might lead to unpredictable technological advancement,” remarked lead author, Carnegie’s Haidong Zhang. “For example, the optical properties of Si-III in the infrared region are particularly interesting for future plasmonic applications.”

Telit, a global enabler of the Internet of Things (IoT), today announced that it is celebrating the 100th installation of its secureWISE software platform in a 300mm semiconductor fabrication plant.

As part of Telit’s IoT Factory Solutions, secureWISE has been providing over 12 years of secure remote IoT connectivity to tool manufacturers (OEMs) for the semiconductor industry. Telit’s IoT Factory Solutions focuses the company’s vision of connected factories, connected machines, and connected consumers and ties directly into its core IoT business. Building on 15 years of experience in industrial automation solutions deployed worldwide and connecting more than $300 billion in manufacturing assets, Telit is making it easy for customers to take advantage of the IIoT opportunity with multiple paths to deployment.

Telit’s secureWISE has been widely recognized as the de-facto solution for highly-secure remote access to semiconductor equipment. The software serves 18 of the top 20 OEMs and is used by every major integrated device manufacturer (IDM) and foundry to securely connect over 250 different tool types with their manufacturers. Connecting more fabs and OEMs than any other platform in the industry, secureWISE delivers secure, configurable end-to-end remote IoT connectivity across a closed, private network. It allows fabs and OEMs to remotely collaborate in ways that improve equipment performance at every stage of the process and lifecycle while protecting valuable intellectual property (IP).

Major semiconductor tool makers have introduced high availability service models that are tightly embedded into their machines installed at the fabs. OEMs are now able to use IoT and remotely collect data, to analyze, fix – as well as predict – any problem with their machines on the semiconductor production floor from any global location. They can offer immediate service and support from subject matter experts to the fabs. In turn, these new service models result in improved uptime and higher reliability of production tools.

The secureWISE eCentre server gives a fab full control of how, when, and what tools can be accessed, assuring that the OEM doesn’t have any unauthorized direct access to production tools. Furthermore, these built-in role-based access functions give fabs a detailed audit trail with comprehensive reporting and business analytics of all activities.

“We are proud of this milestone and the recognition that the semiconductor industry has made secureWISE their de-facto IoT software platform for secure remote monitoring and mediation of mission-critical manufacturing tools,” said Oozi Cats, CEO of Telit. “This is another testament to our fast-growing position around industrie 4.0 through our IoT Factory Solutions division, and it also illustrates how security is an integral part of our DNA, extending across all of Telit’s products and services.”

Spanning the globe, secureWISE is rapidly extending beyond 300mm fabs with new deployments across 200mm fabs, flat panel displays, solar and other manufacturing facilities.

This article was originally posted on SemiMD.com and was featured in the March 2017 issue of Solid State Technology.

By Ed Korczynski, Sr. Technical Editor

A new microwave electron cyclotron resonance (MECR) atomic layer deposition (ALD) process technology has been co-developed by Hitachi High-Technologies Corporation and Picosun Oy to provide commercial semiconductor IC fabs with the ability to form dielectric films at lower temperatures. Silicon oxide and silicon nitride, aluminum oxide and aluminum nitride films have been deposited in the temperature range of 150-200 degrees C in the new 300-mm single-wafer plasma-enhanced ALD (PEALD) processing chamber.

With the device features within both logic and memory chips having been scaled to atomic dimensions, ALD technology has been increasingly enabling cost-effective high volume manufacturing (HVM) of the most advanced ICs. While the deposition rate will always be an important process parameter for HVM, the quality of the material deposited is far more important in ALD. The MECR plasma source provides a means of tunable energy to alter the reactivity of ALD precursors, thereby allowing for new degrees of freedom in controlling final film properties.

The Figure shows the MECRALD chamber— Hitachi High-Tech’s ECR plasma generator is integrated with Picosun’s digitally controlled ALD system—from an online video (https://youtu.be/SBmZxph-EE0) describing the process sequence:

1.  first precursor gas/vapor flows from a circumferential ring near the wafer chuck,

2.  first vacuum purge,

3.  second precursor gas/vapor is ionized as it flows down through the ECR zone above the circumferential ring, and

4.  second vacuum purge to complete one ALD cycle (which may be repeated).

The development team claims that MECRALD films are superior to other PEALD films in terms of higher density, lower contamination of carbon and oxygen (in non-oxides), and also show excellent step-coverage as would be expected from a surface-driven ALD process. The relatively density of these films has been confirmed by lower wet etch rates. The single-wafer process non-uniformity on 300mm wafers is claimed at ~1% (1 sigma). The team is now exploring processes and precursors to be able to deposit additional films such as titanium nitride (TiN), tantalum nitride (TaN), and hafnium oxide (HfO). In an interview with Solid State Technology, a spokesperson from Hitachi High-Technologies explained that, “We are now at the development stage, and the final specifications mainly depend on future achievements.”

The MECR source has been used in Hitachi High-Tech’s plasma chamber for IC conductor etch for many years, and is able to generate a stable high-density plasma at very low pressure (< 0.1 Pa). MECR plasmas provide wide process windows through accurate plasma parameter management, such as plasma distribution or plasma position control. The same plasma technology is also used to control ions and radicals in the company’s dry cleaning chambers.

“I’m really impressed by the continuous development of ALD technology, after more than 40 years since the invention,” commented Dr. Tuomo Suntola, and the famous inventor and patentor of the Atomic Layer Deposition method in Finland in 1974, and member of the Picosun board of directors. “Now combining Hitachi and Picosun technologies means (there is) again a major breakthrough in advanced semiconductor manufacturing.”

MECRALD chambers can be clustered on a Picosun platform that features a Brooks robot handler. This technology is still under development, so it’s too soon to discuss manufacturing parameters such as tool cost and wafer throughput.

—E.K.

BY ED KORCZYNSKI, Senior Technical Editor

With rapidly increasing use of “cloud” client:server computing there is motivation to find cost-savings in the cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300-mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

GlobalFoundries has found a way to automatically align twelve optical fibers to a silicon chip while the fibers are dark. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expen- sively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommu- nications application. Silicon photonics may find first appli- cations for very high bandwidth, mid- to long-distance trans- mission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithog- raphy tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.

IEEE, the world’s largest technical professional organization dedicated to advancing technology for humanity, this week announced the next milestone phase in the development of the International Roadmap for Devices and Systems (IRDS)—an IEEE Standards Association (IEEE-SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative—with the launch of a series of nine white papers that reinforce the initiative’s core mission and vision for the future of the computing industry. The white papers also identify industry challenges and solutions that guide and support future roadmaps created by IRDS.

IEEE is taking a lead role in building a comprehensive, end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software. In May 2016, IEEE announced the formation of the IRDS under the sponsorship of IEEE RC. The historical integration of IEEE RC and the International Technology Roadmap for Semiconductors (ITRS) 2.0 addresses mapping the ecosystem of the new reborn electronics industry. The new beginning of the evolved roadmap—with the migration from ITRS to IRDS—is proceeding seamlessly as all the reports produced by the ITRS 2.0 represent the starting point of IRDS.

While engaging other segments of IEEE in complementary activities to assure alignment and consensus across a range of stakeholders, the IRDS team is developing a 15-year roadmap with a vision to identify key trends related to devices, systems, and other related technologies.

“Representing the foundational development stage in IRDS is the publishing of nine white papers that outline the vital and technical components required to create a roadmap,” said Paolo A. Gargini, IEEE Fellow and Chairman of IRDS. “As a team, we are laying the foundation to identify challenges and recommendations on possible solutions to the industry’s current limitations defined by Moore’s Law. With the launch of the nine white papers on our new website, the IRDS roadmap sets the path for the industry benefiting from all fresh levels of processing power, energy efficiency, and technologies yet to be discovered.”

“The IRDS has taken a significant step in creating the industry roadmap by publishing nine technical white papers,” said IEEE Fellow Elie Track, 2011-2014 President, IEEE Council on Superconductivity; Co-chair, IEEE RC; and CEO of nVizix. “Through the public availability of these white papers, we’re inviting computing professionals to participate in creating an innovative ecosystem that will set a new direction for the greater good of the industry. Today, I open an invitation to get involved with IEEE RC and the IRDS.”

The series of white papers delivers the starting framework of the IRDS roadmap—and through the sponsorship of IEEE RC—will inform the various roadmap teams in the broader task of mapping the devices’ and systems’ ecosystem:

“IEEE is the perfect place to foster the IRDS roadmap and fulfill what the computing industry has been searching for over the past decades,” said IEEE Fellow Thomas M. Conte, 2015 President, IEEE Computer Society; Co-chair, IEEE RC; and Professor, Schools of Computer Science, and Electrical and Computer Engineering, Georgia Institute of Technology. “In essence, we’re creating a new Moore’s Law. And we have so many next-generation computing solutions that could easily help us reach uncharted performance heights, including cryogenic computing, reversible computing, quantum computing, neuromorphic computing, superconducting computing, and others. And that’s why the IEEE RC Initiative exists: creating and maintaining a forum for the experts who will usher the industry beyond the Moore’s Law we know today.”

The IRDS leadership team hosted a winter workshop and kick-off meeting at the Georgia Institute of Technology on 1-2 December 2016. Key discoveries from the workshop included the international focus teams’ plans and focus topics for the 2017 roadmap, top-level needs and challenges, and linkages among the teams. Additionally, the IRDS leadership invited presentations from the European and Japanese roadmap initiatives. This resulted in the 2017 IRDS global membership expanding to include team members from the “NanoElectronics Roadmap for Europe: Identification and Dissemination” (NEREID) sponsored by the European Semiconductor Industry Association (ESIA), and the “Systems and Design Roadmap of Japan” (SDRJ) sponsored by the Japan Society of Applied Physics (JSAP).

The IRDS team and its supporters will convene 1-3 April 2017 in Monterey, California, for the Spring IRDS Workshop, which is part of the 2017 IEEE International Reliability Physics Symposium (IRPS). The team will meet again for the Fall IRDS Conference—in partnership with the 2017 IEEE International Conference on Rebooting Computing (ICRC)—scheduled for 6-7 November 2017 in Washington, D.C. More information on both events can be found here: http://irds.ieee.org/events.

IEEE RC is a program of IEEE Future Directions, designed to develop and share educational tools, events, and content for emerging technologies.

IEEE-SA’s IC Program helps incubate new standards and related products and services, by facilitating collaboration among organizations and individuals as they hone and refine their thinking on rapidly changing technologies.

A new way to grow narrow ribbons of graphene, a lightweight and strong structure of single-atom-thick carbon atoms linked into hexagons, may address a shortcoming that has prevented the material from achieving its full potential in electronic applications. Graphene nanoribbons, mere billionths of a meter wide, exhibit different electronic properties than two-dimensional sheets of the material.

This graphene nanoribbon was made bottom-up from a molecular precursor. Nanoribbon width and edge effects influence electronic behavior. Credit: Oak Ridge National Laboratory, U.S. Dept. of Energy; scanning tunneling microscopy by Chuanxu Ma and An-Ping Li

This graphene nanoribbon was made bottom-up from a molecular precursor. Nanoribbon width and edge effects influence electronic behavior. Credit: Oak Ridge National Laboratory, U.S. Dept. of Energy; scanning tunneling microscopy by Chuanxu Ma and An-Ping Li

“Confinement changes graphene’s behavior,” said An-Ping Li, a physicist at the Department of Energy’s Oak Ridge National Laboratory. Graphene in sheets is an excellent electrical conductor, but narrowing graphene can turn the material into a semiconductor if the ribbons are made with a specific edge shape.

Previous efforts to make graphene nanoribbons employed a metal substrate that hindered the ribbons’ useful electronic properties.

Now, scientists at ORNL and North Carolina State University report in the journal Nature Communications that they are the first to grow graphene nanoribbons without a metal substrate. Instead, they injected charge carriers that promote a chemical reaction that converts a polymer precursor into a graphene nanoribbon. At selected sites, this new technique can create interfaces between materials with different electronic properties. Such interfaces are the basis of semiconductor electronic devices from integrated circuits and transistors to light-emitting diodes and solar cells.

“Graphene is wonderful, but it has limits,” said Li. “In wide sheets, it doesn’t have an energy gap–an energy range in a solid where no electronic states can exist. That means you cannot turn it on or off.”

When a voltage is applied to a sheet of graphene in a device, electrons flow freely as they do in metals, severely limiting graphene’s application in digital electronics.

“When graphene becomes very narrow, it creates an energy gap,” Li said. “The narrower the ribbon is, the wider is the energy gap.”

In very narrow graphene nanoribbons, with a width of a nanometer or even less, how structures terminate at the edge of the ribbon is important too. For example, cutting graphene along the side of a hexagon creates an edge that resembles an armchair; this material can act like a semiconductor. Excising triangles from graphene creates a zigzag edge–and a material with metallic behavior.

To grow graphene nanoribbons with controlled width and edge structure from polymer precursors, previous researchers had used a metal substrate to catalyze a chemical reaction. However, the metal substrate suppresses useful edge states and shrinks the desired band gap.

Li and colleagues set out to get rid of this troublesome metal substrate. At the Center for Nanophase Materials Sciences, a DOE Office of Science User Facility at ORNL, they used the tip of a scanning tunneling microscope to inject either negative charge carriers (electrons) or positive charge carriers (“holes”) to try to trigger the key chemical reaction. They discovered that only holes triggered it. They were subsequently able to make a ribbon that was only seven carbon atoms wide–less than one nanometer wide–with edges in the armchair conformation.

“We figured out the fundamental mechanism, that is, how charge injection can lower the reaction barrier to promote this chemical reaction,” Li said. Moving the tip along the polymer chain, the researchers could select where they triggered this reaction and convert one hexagon of the graphene lattice at a time.

Next, the researchers will make heterojunctions with different precursor molecules and explore functionalities. They are also eager to see how long electrons can travel in these ribbons before scattering, and will compare it with a graphene nanoribbon made another way and known to conduct electrons extremely well. Using electrons like photons could provide the basis for a new electronic device that could carry current with virtually no resistance, even at room temperature.

“It’s a way to tailor physical properties for energy applications,” Li said. “This is an excellent example of direct writing. You can direct the transformation process at the molecular or atomic level.” Plus, the process could be scaled up and automated.

A coalition of leaders from the global tech, defense, and aerospace industries, led by the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC), today released a report identifying the key areas of scientific research needed to advance innovation in semiconductor technology and fulfill the promise of emerging technologies such as artificial intelligence (AI), the Internet of Things (IoT), and supercomputing. The report, titled Semiconductor Research Opportunities: An Industry Vision and Guide, also calls for robust government and industry investments in research to unlock new technologies beyond conventional, silicon-based semiconductors and to advance next-generation semiconductor manufacturing methods.

“Semiconductor technology is foundational to America’s innovation infrastructure and global technology leadership,” said John Neuffer, president and CEO of SIA, which represents U.S. leadership in semiconductor manufacturing, design, and research. “Our industry has pushed Moore’s Law to levels once unfathomable, enabling technologies that have driven economic growth and transformed society. Now, as it becomes increasingly challenging and costly to maintain the breakneck pace of putting more transistors on the same size of silicon real estate, industry, academia, and government must intensify research partnerships to explore new frontiers of semiconductor innovation and to foster the continued growth of emerging technologies. Taking swift action to implement the recommendations from the Vision report will help usher in a new era of semiconductor technology and keep America at the head of the class in technological advancement.”

Neuffer also noted concern in the tech, research, and academic communities about proposed cuts to basic scientific research outlined in the Trump Administration’s fiscal year 2018 budget blueprint. Basic scientific research funded through agencies such as the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), the Defense Advanced Research Projects Agency (DARPA), and the Department of Energy (DOE) Office of Science has yielded tremendous dividends, helping launch technologies that underpin America’s economic strength and global competiveness. The U.S. semiconductor industry invests about one-fifth of revenue each year in R&D – the highest share of any industry. Neuffer expressed the semiconductor industry’s readiness to work with the Administration and Congress to enact a budget that embraces the strategic importance of research investments to America’s continued economic and technological strength.

“Continued and predictable advancements in semiconductor technology have fueled the growth of many industries, including those historically based on mechanics such as automotive,” said Ken Hansen, president & CEO of SRC. “As the rate of dimensional scaling has slowed, the need to reinvigorate the investment in semiconductor research has become increasingly clear. Now is the time for industry, government, and academia to double down their resources and efforts to ensure the pace of renewal continues. Alternative strategies and techniques to the traditional scaling for performance are now being explored by SRC. Furthermore, with the support of SIA, SRC is building research programs that align with the Vision report, including complimentary technologies such as advanced packaging and communications. An infusion of funding is vital to expand the research breadth beyond the historical focus areas, enabling the industry to keep its promise of a continuous stream of products with improved performance at reduced cost. As industries look to future areas of growth and innovation, SIA and SRC are laying the groundwork for new discoveries through fundamental research.”

The Vision report is the culmination of work by a diverse group of industry experts and leaders, including chief technology officers at numerous leading semiconductor companies, who came together over a nine-month period in 2016-2017 to identify areas in which research is essential to progress. The report, which will be updated periodically moving forward, has active participation from the industry’s leading chip makers, fabless companies, IP providers, equipment and material suppliers, and research organizations. It will serve as a foundational guide for defining the semiconductor industry’s future research paths in 14 distinct but complimentary research areas. These areas, outlined in the Vision report, are as follows:

1. Advanced Devices, Materials, and Packaging2. Interconnect Technology and Architecture

3. Intelligent Memory and Storage

4. Power Management

5. Sensor and Communication Systems

6. Distributed Computing and Networking

7. Cognitive Computing

 8. Bio-Influenced Computing and Storage9. Advanced Architectures and Algorithms

10. Security and Privacy

11. Design Tools, Methodologies, and Test

12. Next-Generation Manufacturing Paradigm

13. Environmental Health and Safety: Materials and Processes

14. Innovative Metrology and Characterization

 

IC Insights has raised its worldwide IC market growth forecast for 2017 to 11%—more than twice its original 5% outlook—based on data shown in the March Update to the 20th anniversary 2017 edition of The McClean Report. The revision was necessary due to a substantial upgrade to the 2017 growth rates forecast for the DRAM and NAND flash memory markets.

IC Insights currently expects DRAM sales to grow 39% and NAND flash sales to increase 25% this year, with upside potential from those forecasts.  DRAM market growth is expected to be driven almost entirely by a huge 37% increase in the DRAM average selling price (ASP), as compared to 2016, when the DRAM ASP dropped by 12%. Moreover, NAND flash ASPs are forecast to rebound and jump 22% this year after falling by 1% last year.

The DRAM market started 2017 the way it ended 2016—with strong gains in DRAM ASP.  In April 2016, the DRAM ASP was $2.41 but rapidly increased to $3.60 in January 2017, a 49% jump.  A pickup in DRAM demand from PC suppliers during the second half of 2016 caused a significant spike in the ASP of PC DRAM.  Currently, strengthening ASPs are also evident in the mobile DRAM market segment.

With total DRAM bit volume demand expected to increase by 30% this year and DRAM bit volume production capacity forecast to increase by 20%, IC Insights believes that quarterly DRAM ASPs could still surprise on the upside in 2017. Furthermore, DRAM output is also being slowed, at least temporarily, by the ongoing transition of DRAM production to ≤20nm feature sizes by the major DRAM producers this year.

At $57.3 billion, the DRAM market is forecast to be by far the largest IC product category in 2017, exceeding the expected MPU market for standard PCs and servers ($47.1 billion) by $10.2 billion this year.  Figure 1 shows that the DRAM market has been both a significant tailwind (i.e., positive influence) and headwind (i.e., negative influence) on total worldwide IC market growth in three out of the past four years.

Figure 1

Figure 1

Spurred by a 12% decline in the DRAM ASP in 2016, the DRAM market slumped 8% last year.  The DRAM segment became a headwind to worldwide IC market growth in 2016 instead of the tailwind it had been in 2013 and 2014. As shown, the DRAM market shaved two percentage points off of total IC industry growth last year.  In contrast, the DRAM segment is forecast to have a positive impact of four percentage points on total IC market growth this year. It is interesting to note that the total IC market growth rate forecast for 2017, when excluding the DRAM and NAND flash markets, would be only 4%, about one-third of the current worldwide IC market growth rate forecast including these memory devices.

The March Update to the 2017 edition of The McClean Report further describes IC Insights’ IC market forecast revision, updates its 2017-2021 semiconductor capital spending forecast, and shows the final 2016 top 10 OSAT company ranking.

Micron Technology, Inc. (NASDAQ:MU), a developer of advanced semiconductor systems, today announced that on March 14 it successfully won the auction for Cando Corporation assets, which will be utilized in establishing a back-end site for Micron Taiwan. Micron has now completed the title acquisition process for the new site.

The acquisition includes the cleanroom and tools that are adjacent to Micron’s existing Taichung fab, bringing the company’s fabrication and back-end together in one location. The new site will be focused on establishing a centralized back-end operation.

“This marks a significant step in our plan to create a center of excellence for leading-edge DRAM in Taiwan,” said Wayne Allan, VP, Global Manufacturing. “Bringing fabrication and back end together, all in one location, builds an efficient support structure for end-to-end manufacturing with quicker cycle times that benefit our business and customers.”

The new back-end site is expected to begin production in August, and the new integrated center of excellence is expected to bring greater operational cost efficiency that will benefit Micron’s DRAM business on a global scale. These cost efficiencies are part of the overall US$500 million of ongoing operational enhancement opportunities cited at the company’s 2017 analyst conference.

The strategic acquisition, with a winning bid of US$89.2 million, also highlights Micron’s goal to grow its presence in Taiwan – where it is the largest foreign employer and investor – from its current wafer manufacturing function to a broader center of expertise in the global memory industry. The back-end site will further enhance the company’s strong presence on the island, which already includes 300mm wafer fabrication facilities in Taichung and Taoyuan, as well as sales and technical support offices in Taipei.

The back-end operation will be led by site director Mike Liang, who joined Micron in November 2016 with more than 35 years of experience in the semiconductor industry. Having previously served in leadership roles at Ti-Acer, KYEC and Amkor Taiwan, Liang brings significant expertise in both front-end wafer fabrication and back-end assembly and test manufacturing.

Intel Corporation today announced that Omar Ishrak and Greg Smith have been elected to Intel’s board of directors.

“We are very pleased to welcome two new, independent directors with the depth of leadership experience at innovative, global companies that both Mr. Ishrak and Mr. Smith bring,” said Intel Chairman Andy Bryant. “We look forward to their valuable contributions as Intel continues to transform itself for growth in emerging, adjacent market segments.”

Omar-IshrakIshrak, 61, is the chairman and chief executive officer of Medtronic, a global leader in medical technology. He has served in that role since 2011. Prior to joining Medtronic, he spent 16 years in various roles with General Electric Company, most recently as president and chief executive officer of GE Healthcare Systems, a division of GE Healthcare. He is a member of the board of trustees of the Asia Society, which promotes mutual understanding and strengthening partnerships among peoples, leaders and institutions of Asia and the United States in a global context, and a member of the board of directors for Minnesota Public Radio.

Smith, 50, is the chief financial officer and executive vice president of corporate development and strategy at Boeing, the world’s largest aerospace and defense company. He has served as Boeing’s finance leader since 2012 and its strategy leader since 2015. Previously, Smith held various leadership roles across Boeing’s finance function and operations. He rejoined Boeing in 2008 after serving for four years as vice president of global investor relations at Raytheon. Smith serves on the board of trustees for the Chicago Museum of Science and Industry, and the board of directors of the Economic Club of Chicago, the Chicago Botanic Garden and the Northwestern Medicine Community Physicians Group.