Category Archives: Wafer Processing

Worldwide silicon wafer area shipments increased during the third quarter 2016 when compared to second quarter 2016 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,730 million square inches during the most recent quarter, a 0.9 percent increase from the 2,706 million square inches shipped during the previous quarter. New quarterly total area shipments are 5.4 percent higher than third quarter 2015 shipments and are at their highest recorded quarterly level.

“Global silicon wafer demand continued to grow during this quarter,” said Dr. Volker Braetsch, chairman SEMI SMG and senior vice president of Siltronic AG. “Year-to-date shipments are trending slightly above the same period as last year.”

Silicon* Area Shipment Trends

Millions of Square Inches

3Q 

2015

2Q 

2016

3Q 

2016

Q1 + Q2 + Q3 

2016

Q1 + Q2 + Q3 

2015
Total

 

2,591

2,706

2,730

7,973

7,930

 

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

Researchers at the Fraunhofer Institute for Solar Energy Systems ISE together with the Austrian company EV Group (EVG) have successfully manufactured a silicon-based multi-junction solar cell with two contacts and an efficiency exceeding the theoretical limit of silicon solar cells. For this achievement, the researchers used a “direct wafer bonding” process to transfer a few micrometers of III-V semiconductor material to silicon, a well-known process in the microelectronics industry. After plasma activation, the subcell surfaces are bonded together in vacuum by applying pressure. The atoms on the surface of the III-V subcell form bonds with the silicon atoms, creating a monolithic device. The efficiency achieved by the researchers presents a first-time result for this type of fully integrated silicon-based multi-junction solar cell. The complexity of its inner structure is not evident from its outer appearance: the cell has a simple front and rear contact just as a conventional silicon solar cell and therefore can be integrated into photovoltaic modules in the same manner.

Wafer-bonded III-V / Si multi-junction solar cell with 30.2 percent efficiency ©Fraunhofer ISE/A. Wekkeli

Wafer-bonded III-V / Si multi-junction solar cell with 30.2 percent efficiency ©Fraunhofer ISE/A. Wekkeli

“We are working on methods to surpass the theoretical limits of silicon solar cells,” says Dr. Frank Dimroth, department head at Fraunhofer ISE. “It is our long-standing experience with silicon and III-V technologies that has enabled us to reach this milestone today.” A conversion efficiency of 30.2 percent for the III-V / Si multi-junction solar cell of 4 cm² was measured at Fraunhofer ISE’s calibration laboratory. In comparison, the highest efficiency measured to date for a pure silicon solar cell is 26.3 percent, and the theoretical efficiency limit is 29.4 percent.

The III-V / Si multi-junction solar cell consists of a sequence of subcells stacked on top of each other. So-called “tunnel diodes” internally connect the three subcells made of gallium-indium-phosphide (GaInP), gallium-arsenide (GaAs) and silicon (Si), which span the absorption range of the sun’s spectrum. The GaInP top cell absorbs radiation between 300 and 670 nm. The middle GaAs subcell absorbs radiation between 500 and 890 nm and the bottom Si subcell between 650 and 1180 nm, respectively. The III-V layers are first epitaxially deposited on a GaAs substrate and then bonded to a silicon solar cell structure. Subsequently the GaAs substrate is removed, and a front and rear contact as well as an antireflection coating are applied.

“Key to the success was to find a manufacturing process for silicon solar cells that produces a smooth and highly doped surface which is suitable for wafer bonding as well as accounts for the different needs of silicon and the applied III-V semiconductors,” explains Dr. Jan Benick, team leader at Fraunhofer ISE.

“In developing the process, we relied on our decades of research experience in the development of highest efficiency silicon solar cells.” Institute Director Prof. Eicke Weber expresses his delight: “I am pleased that Fraunhofer ISE has so convincingly succeeded in breaking through the glass ceiling of 30 percent efficiency with its fully integrated silicon-based solar cell with two contacts. With this achievement, we have opened the door for further efficiency improvements for cells based on the long-proven silicon material.”

“The III-V / Si multi-junction solar cell is an impressive demonstration of the possibilities of our ComBond® cluster for resistance-free bonding of different semiconductors without the use of adhesives,” says Markus Wimplinger, Corporate Technology Development and IP Director at EV Group. “Since 2012, we have been working closely with Fraunhofer ISE on this development and today are proud of our team’s excellent achievements.” The direct wafer-bonding process is already used in the microelectronics industry to manufacture computer chips.

On the way to the industrial manufacturing of III-V / Si multi-junction solar cells, the costs of the III-V epitaxy and the connecting technology with silicon must be reduced. There are still great challenges to overcome in this area, which the Fraunhofer ISE researchers intend to solve through future investigations. Fraunhofer ISE’s new Center for High Efficiency Solar Cells, presently being constructed in Freiburg, will provide them with the perfect setting for developing next-generation III-V and silicon solar cell technologies. The ultimate objective is to make high efficiency solar PV modules with efficiencies of over 30 percent possible in the future.

The young researcher Dr. Romain Cariou carried out research on this project at Fraunhofer ISE with the support of a Marie Curie Postdoctoral Fellowship. Funding was provided by the EU project HISTORIC. The work at EVG was supported by the Austrian Ministry for Technology.

Datacenters with few other emerging applications will become a multibillion dollar market for silicon photonics by 2025. Transporting high level of data with existing technologies will soon reach its limit and photons will continue replacing step by step electrons throughout networks. Growing investments made by VCs have been identified by Yole Développements’ analysts and few startups have been created in this sector. All these indicators confirm the trend: silicon photonic technologies have reached the tipping point that precedes massive growth.

silicon photonics illustration

Yole Développement (Yole), the “More than Moore” market research and strategy consulting company releases this month the technology & market analysis titled Silicon Photonics for datacenters and other applications. Both experts Dr Eric Mounier, Sr Technnology & Market Analyst at Yole and Jean-Louis Malinge, former CEO of Kotura, now at ARCH Venture Partners combined their knowledge of the silicon photonic industry to perform a deep added-value analysis. Under this report, they examine the current status and future challenges for silicon photonics and data centers application. They detail for all applications, silicon photonic benefits as well as a comprehensive analysis of the industrial supply chain with player’s status.

What is the status of silicon photonic technologies? Could we already speak about commercial solutions? What is the market size today? What about tomorrow? How high are the current investments? Yole’s analysts offer you a snapshot of the story.

The silicon photonics market is still modest with estimated sales below US$40 million in 2015 and very few companies actually shipping products in the open market: Mellanox, Cisco, Luxtera, Intel, STMicroelectronics, Acacia and Molex are part of these leading players.

Silicon photonics has been under development for years. However now, this technology is being pushed hard by large webcom companies like Facebook and Microsoft. “Silicon photonics has reached the tipping point that precedes massive growth,” comments Dr Eric Mounier from Yole. “Indeed we estimate, the packaged silicon photonics transceiver market will be worth US$6 billion in 10 years.”

Silicon photonics is an exciting technology mixing optics, CMOS technology and advanced packaging. This combination benefits from semiconductor wafer manufacturing scalability to reduce costs.

“Silicon photonics offers silicon technology advantages including higher integration, more functionalities embedded with lower power consumption and better reliability compared to legacy optics”, analyzes Jean-Louis Malinge.

In 2020 and more, silicon photonic chips will far exceed copper cabling capabilities. Such solutions will be so deployed in high-speed signal transmission systems. In 2025 and more, the technology will be more and more used in processing such as interconnecting multiple cores with processor chips. Indeed, according to Yole’s analysts, the chip market value should score US$1,5 billion in 2025 at chip level (Estimated to be less than US$40 million in 2015). Step by step photons get closer to the chips!

Data centers are clearly the best opportunity for silicon photonics technology today. And there are also many other applications that silicon photonics can enable. These include high performance computers, telecommunications, sensors, life science, quantum computers and other high-end applications.

Two applications are particularly interesting as silicon photonics can push the integration of optical functions and miniaturization further to achieve successful products. Those applications are lidars for autonomous cars and biochemical and chemical sensors.

Lidars are costly and bulky instruments which make their integration in a car challenging. Within a promising ADAS market expected to reach US$3,9 billion in 2017 silicon photonic-based lidar will play a key role. Indeed silicon photonics allow lidar without moving elements, which can experience issues in a harsh car environment. Last august, MIT’s Photonic Microsystems Group announced a successful DARPA project using silicon photonics for lidar-on-a-chip with steerable transmitting and receiving phased arrays and on-chip Ge photodetectors.

Biochemical and gas sensors are not new, and several applications have existed for a while. Day by day, the interest in gas sensing is gaining importance due to the emergence of promising new large volume portable applications. Integration of biochemical or gas sensors into smartphones or wearables is currently on the roadmap of many companies but size, cost and sensitivity are still issues. To push optical gas sensor miniaturization further, some companies are already considering silicon photonics as an integration platform for their devices.

These non-data center applications will be about US$300 million in 2025, detail Yole’s analysts in the silicon photonics report.

Since President Obama took office in 2009, the Administration has focused on promoting innovation for the purposes of strengthening the economy, improving quality of life, and protecting the safety and security of our country.

Last week, the President’s Council of Advisors on Science and Technology (PCAST) announced the formation of a new working group focused on strengthening the U.S. semiconductor industry in ways that benefit the nation’s economic and security interests.

Semiconductors are essential to many aspects of modern life, from cellphones and automobiles to medical diagnostics to reconnaissance satellites and weapon systems. The semiconductor industry directly employs 250,000 workers, is the third largest source of U.S. manufactured exports, and has the highest level of investment in research and development (R&D) as a percentage of sales of any major industry. In addition, the semiconductor industry creates foundational technologies that enable innovation in virtually every sector of the U.S. economy. A loss of leadership in semiconductor innovation and manufacturing could have significant adverse impacts on the U.S. economy and even on national security.

In a world where the supply chains are global, policies being pursued by other countries are posing new challenges to the U.S. semiconductor industry. Specifically, some countries that are important in this domain are subsidizing their domestic semiconductor industry or requiring implicit transfer of technology and intellectual property in exchange for market access. Such policies could lead to overcapacity and dumping, reduce incentives for private-sector R&D in the United States, and thereby slow the pace of semiconductor innovation and realization of the economic and security benefits that such innovation could bring.

The industry may also be approaching technological and economic inflection points. Based on the currently commercialized approach to semiconductor technology, the industry may soon be unable to continue the pace of advance described by “Moore’s Law”—doubling the processing power of chips every 18–24 months—a pace that has brought with it rapid advances in the capabilities of systems that use semiconductors, opened up new applications, and thus fueled economic growth while increasing quality of life and strengthening national security. Indeed, the exponentially growing cost of designing and fabricating higher-performance chips in the conventional mold is already stifling innovation, making it more difficult for startups and new ideas from university research to create new markets—a key source of competitive advantage for America’s entrepreneurial economy.

Additional public and private investments in R&D are almost certain to be required if the past remarkable pace of improvements in price and performance of semiconductors and the benefits deriving therefrom are to continue—R&D that looks to create new technologies that can leapfrog beyond the limits of today’s technology and explore entirely new computer architectures and their integration into systems well beyond the traditional computing sphere, including automotive and other mobile applications.

The time is therefore right for a fresh look at the policy issues shaping innovation and global competition in the semiconductor industry. The new PCAST working group will identify the core challenges facing the semiconductor industry at home and abroad and identify major opportunities for sustaining U.S. leadership. Based on its findings, the working group will deliver a set of recommendations on initial actions the Federal government, industry, and academia could pursue to maintain U.S. leadership in this crucial domain.

The full working group includes the following members:

  • John Holdren (Director, OSTP; PCAST Co-Chair); Working Group Co-Chair
  • Paul Otellini (Former President and CEO, Intel); Working Group Co-Chair
  • Richard Beyer (Former Chairman and CEO, Freescale Semiconductor)
  • Wes Bush (Chairman, CEO, and President, Northrop Grumman)
  • Diana Farrell (President and CEO, JP Morgan Chase Institute)
  • John Hennessy (President Emeritus, Stanford University)
  • Paul Jacobs (Executive Chairman, Qualcomm)
  • Ajit Manocha (Former CEO, GlobalFoundries)
  • Jami Miscik (Co-CEO and Vice Chairman, Kissinger Associates; Co- Chair, President’s Intelligence Advisory Board)
  • Craig Mundie (President, Mundie and Associates; Former Senior Advisor, Microsoft; Member of PCAST)
  • Mike Splinter (Former CEO and Chairman, Applied Materials)
  • Laura Tyson (Distinguished Professor of the Graduate School, UC Berkeley; Former CEA Chair and NEC Director)

SunEdison Semiconductor Limited (NASDAQ:SEMI) (“SunEdison Semiconductor”) announced today that it has received notice that the Investment Committee of the Ministry of the Economic Affairs of the Republic of China has approved the proposed acquisition of SunEdison Semiconductor by GlobalWafers Co., Ltd. (“GlobalWafers”), and that the Austrian antitrust authority has concluded its review.  As a result, all pre-closing antitrust requirements have been completed.

As previously announced on August 17, 2016, GlobalWafers and SunEdison Semiconductor entered into a definitive agreement for the acquisition by GlobalWafers, through a wholly owned subsidiary, of all of the outstanding ordinary shares of SunEdison Semiconductor in an all-cash transaction valued at US$683 million, including SunEdison Semiconductor outstanding net indebtedness, pursuant to a scheme of arrangement under Singapore law.  Under the terms of the agreement, SunEdison Semiconductor shareholders will receive, upon consummation of the scheme of arrangement, US$12.00 per share in cash for each ordinary share.

Astronics Corporation (NASDAQ:ATRO), through its wholly-owned subsidiary Astronics Test Systems, introduced its new breakthrough System-Level Test (SLT) platform that is expected to revolutionize the testing of high volume integrated semiconductor devices.  The new ATS 5034 System-Level Test (SLT) Platform improves production efficiency and greatly reduces the cost of test by processing up to 396 devices simultaneously.

This new platform is ideal for testing the latest semiconductor devices for mobile, automotive, wearable and industrial applications.  The ATS 5034 SLT Platform can be tailored to meet precise production test requirements.  Customers will benefit from the dramatically reduced footprint of the ATS 5034 SLT Platform and the ability to test up to 5,000 units per hour (UPH).

“For the past 20 years, we’ve provided system-level and burn-in testers that have tested more than 9 billion semiconductor devices globally,” explained Jon Sinskie, Executive Vice President of Astronics Test Systems.  “The ATS 5034 SLT Platform is our newest tester, which for the first time offers an affordable method for semiconductor manufacturers to improve yields by implementing a 100% SLT test insertion in production.”

Affordable 100% SLT through a Massively Parallel Platform

The new ATS 5034 SLT Platform tests integrated semiconductors in “mission mode” to verify performance of the semiconductor at the operating level.  Traditionally a difficult, expensive test insertion, the new ATS 5034 makes it simple for manufacturers to now transition to 100% SLT affordably.  An engineer can design a test sequence for a single site, and the ATS 5034 SLT Platform easily scales that sequence to hundreds of sites.

“With the increasing complexity of today’s semiconductor devices and pressures to cost effectively hit aggressive time to market schedules, customers are looking for new ways to find defects that are missed during traditional ATE functional testing,” explained Anil Bhalla, Senior Marketing Manager for Astronics Test Systems.  “We’ve built a platform that enables customers to find these defects with SLT in a way that previously was not cost effective.”

Customizable and adaptable, this versatile modular platform satisfies a variety of manufacturing test functions including system characterization, validation, and qualification, system-level test and RMA/failure debug.

Key features include:

  • Testing of integrated semiconductor devices, such as microprocessors, microcontrollers, and embedded systems
  • Test up to 396 devices simultaneously, at a rate of up to 5,000 UPH
  • Support for popular package types: system on chip (SoC), module, and heterogeneous system in package (SiP)
  • Turnkey automation with JEDEC trays input and outputs, including lot cascading
  • Astronics’ ActivATE™ software, an easy-to-use test executive
  • Extremely accurate thermal stress testing capability (+/- 1° C)
  • Small factory footprint

Astronics can further customize this platform for various low, medium or high volume system-level test scenarios.  This platform also includes support from the Astronics program management organization, which oversees installation and maintenance at any global location.  Units are in production and shipping in the first quarter of 2017.

Semiconductor Manufacturing International Corporation (“SMIC”; NYSE:  SMI; SEHK: 981), the largest and most advanced foundry in Mainland China, announces the official launch of a 12-inch integrated circuit (IC) production line at SMIC’s Shenzhen facility. It will be the very first 12-inch fab in South China.

In order to meet the large demand for IC chips in the IoT era, SMIC Shenzhen is building the new 12-inch IC production line in an existing building. The new line will manufacture mainstream mature technology. Construction is planned to start by the end of 2016. Some second-hand equipment for the new line has already been secured. The early production is expected to begin by the end of 2017.The total designed capacity is 40,000 12-inch wafers per month; capacity ramp will be based on customer needs.

Located in Pingshan New District, Shenzhen, SMIC Shenzhen opened the first 8-inch IC production line in South China in December 2014. Its capacity is currently 30,000 wafers per month, and it will continue to expand based on market demand.

The Chairman of SMIC, Dr. Zixue Zhou, said, “Shenzhen has the largest electronic information industrial base in China, comprising hundreds of IC design, system and equipment companies. Thanks to the attention given to the IC industry from the Shenzhen Municipal Government, SMIC Shenzhen steadily operates an 8-inch production line. By launching the new 12-inch production line, SMIC will further improve our capacity, better serve our customers, and facilitate the development of Shenzhen’s IC ecosystem.”

Samsung Electronics Co. Ltd. announced today that it is expanding its advanced foundry process technology offerings with the fourth-generation 14-nanometer (nm) process (14LPU) and the third-generation 10nm process (10LPU) to meet the requirements of next generation products ranging from mobile and consumer electronics to data centers and automotives.

Samsung presented these new technology offerings at the Samsung Foundry Forum to foundry customers and partners. The event was held at its Device Solutions America headquarters today, where the company elaborated on the details of new technology offerings including 14LPU and 10LPU.

Samsung’s fourth-generation 14nm process technology, 14LPU, delivers higher performance at the same power and design rules compared to its third-generation 14nm process (14LPC). 14LPU will be optimally suited for high-performance and compute-intensive applications.

Samsung’s third-generation 10nm process, 10LPU, will provide area reduction compared to its previous generations (10LPE and 10LPP). Due to limitations of current lithography technologies, 10LPU is expected to be the most cost-effective cutting-edge process technology in the industry. Together with the second-generation 10nm process (10LPP) that offers an extra performance boost from 10LPE, 10LPU is positioned to meet the needs of an extended range of applications that can benefit from the advanced 10nm process.

On top of the new process offerings, Samsung also updated its 7nm EUV process development status and showcased its 7nm EUV wafer.

“After we announced the industry’s first 10nm mass production in mid-October, we have now also expanded our lineup with new foundry offerings, 14LPU and 10LPU,” said Ben Suh, Senior Vice President of foundry marketing at Samsung Electronics. “Samsung is very confident with our technology definitions that provide design advantages on an aggressive process with manufacturability considerations. We have received tremendous positive market feedback and are looking forward to expanding our leadership in the advanced process technology space.”

Process design kits (PDK) for 14LPU and 10LPU process technologies will be available during the second quarter of 2017.

The Global Semiconductor Alliance (GSA) announced the 2016 award nominees for the GSA Awards Dinner Celebration. Featuring a keynote by Dan Schulman, President and CEO of PayPal, the celebration will take place on Thursday, December 8, 2016, at the Santa Clara Convention Center in Santa Clara, California. The program will recognize companies that have demonstrated excellence through their vision, strategy, execution and future opportunity. These companies will be honored for their achievements in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry.

The 2016 Dr. Morris Chang Exemplary Leadership Award winner is Lip-Bu Tan, President and CEO of Cadence Design Systems, Inc.and Founder and Chairman of Walden International.

The evening’s program will recognize leading semiconductor companies that have exhibited market growth through technological innovation and exceptional business management strategies. The award categories and nominees (in alphabetical order) are as follows:

Start-Up to Watch Award
Credo Semiconductor
Innovium, Inc.
Transphorm, Inc.

Most Respected Private Semiconductor Company Award
Aquantia Corporation
Movidius
Quantenna Communications, Inc.

Most Respected Public Semiconductor Company Award (Achieving $100 to $500 Million in Annual Sales):
Nordic Semiconductor
Power Integrations, Inc.
Rambus, Inc.

Most Respected Public Semiconductor Company Award (Achieving $500 Million to $1 Billion in Annual Sales):
MACOM Technology Solutions Holdings, Inc.
Mellanox Technologies
Silicon Labs

Most Respected Public Semiconductor Company Award (Achieving $1 Billion to $5 Billion in Annual Sales)
Analog Devices, Inc.
Microchip Technology, Inc.
Skyworks Solutions, Inc.

Most Respected Public Semiconductor Company Award (Achieving Greater than $5 Billion in Annual Sales)
MediaTek Inc.
NVIDIA Corporation
NXP Semiconductors N.V.

Best Financially Managed Semiconductor Company Award (Achieving Up to $1 Billion in Annual Sales):
Power Integrations, Inc.
Silicon Motion Technology Corporation (Silicon Motion, Inc.)
Sitronix Technology Corporation

Best Financially Managed Semiconductor Company Award (Achieving Greater than $1 Billion in Annual Sales)
NVIDIA Corporation
Realtek Semiconductor Corporation
Skyworks Solutions, Inc.

Analyst Favorite Semiconductor Company Award (chosen by analyst Quinn Bolton of Needham & Company, LLC)
Integrated Device Technology, Inc.
MACOM Technology Solutions Holdings, Inc.
Microsemi Corporation

Outstanding Asia Pacific Semiconductor Company Award
MediaTek Inc.
Realtek Semiconductor Corporation
Samsung Electronics Co., Ltd.
Spreadtrum Communications, Inc.

Outstanding EMEA Semiconductor Company Award
Fingerprint Cards AB (FPC)
Movidius
Sckipio Technologies

Qualcomm’s proposed acquisition of NXP Semiconductors marks the latest deal in a wave of industry consolidation that includes increasingly expensive transactions with greater focus on expanding scope rather than economies of scale, according to Fitch Ratings. Fitch believes consolidation in the chip industry will continue through the intermediate term within the context of cheap financing and tepid demand in more mature semiconductor markets.

While the NXP deal is expensive (and the largest ever) at $47 billion, including nearly $8 billion of net debt at NXP, Qualcomm will be able to tax-efficiently use offshore cash to fund a material amount of the all-cash transaction, given NXP’s Dutch incorporation. Fitch estimates Qualcomm will use approximately $28 billion of its $31 billion of total available cash at June 26, 2016 (more than $28 billion is located outside the U.S.) of offshore cash as of June 26, 2016 (versus $31 billion of total cash) and $11 billion of new debt, resulting in a Fitch estimated total leverage (total debt to operating EBITDA) of roughly 3.2x at closing. Despite the high price tag, Fitch believes the 4.6x revenue purchase multiples is in line with averages paid in large transactions completed over the last year, which Fitch estimates was roughly 5x revenues.

The Qualcomm deal with NXP is the latest example of chip companies acquiring capabilities within growth markets, particularly automotive and internet of things (IoT), as traditional semiconductor PC and smartphone markets mature. Qualcomm expects the acquisition will increase its addressable market by 40%, driven by increasing semiconductor content per car in automotive markets, exponential growth of connected devices in IoT markets and growing adoption of credit card security technologies.

Avago Technologies’ Feb. 2, 2016 acquisition of Broadcom for $37 billion focused on leveraging Broadcom’s leading wi-fi technology for the IoT market. Qualcomm’s August 2016 $2.4 billion acquisition of CSR plc strengthened Qualcomm’s nascent automotive and IoT offerings with significant semiconductor and software capabilities. Intel’s December 2015 acquisition of Altera Inc. for $16.7 billion acquisition of Altera diversified Intel away from personal computers by combining Altera’s field-programmable gate arrays with Intel’s low power processors for IoT applications. Even NXP’s December 2015 $12 billion acquisition of Freescale Semiconductor focused on expanding already strong capabilities and share in automotive and IoT markets.

Qualcomm has been in strategic review mode over the past few years amid growth concerns reflecting intensifying competition in the maturing smart phone market from the likes of Intel and a less robust long-term outlook for licensing revenue in China, where most smartphone unit growth is expected. The acquisition of NXP meaningfully diversifies Qualcomm’s end market exposure, reducing wireless handset exposure to below 50% of mobile products sales from 61% currently, and provides a top line growth catalyst, as well as earnings growth beyond significant share repurchases.

Fitch believes deal integration may be complicated by NXP’s ongoing integration of Freescale, which was structured largely as a merger of equals, and lack of technology overlap, given Qualcomm’s system-on-a-chip for mobile devices and telecom equipment focus and NXP’s focus on mixed-signal semiconductors and microprocessors and microcontrollers.