Category Archives: Wafer Processing

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics’ Process Design Kit (PDK) and Foundation Library on Samsung’s second-generation of 10nm LPP (Low Power Plus) process. Samsung also validated the Cadence reference flow using a quad-core design with the ARM Cortex-A53 processor on the 10LPP process, which was implemented with the low-power design methodology covering power-gating and memory retention, IEEE 1801 UPF2.1 power intent, and statistical on-chip variation (SOCV)-based timing closure using the Liberty Variation Format (LVF) library.

The Cadence digital and signoff tools met all of Samsung’s accuracy requirements, enabling foundry customers to quickly achieve design closure and deliver large, complex FinFET designs faster with the 10LPP process. In addition, the Cadence signoff tools have been certified for tapeout using Samsung’s certification criteria for baseline accuracy. The tools in the design flow include:

  • Innovus Implementation System: Based on a massively parallel architecture, it enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirements, such as floorplanning, placement and routing with integrated color-/pin-access /variability-aware timing closure, and clock tree and power optimization
  • Genus Synthesis Solution: Delivers improved productivity during register-transfer level (RTL) design and highly correlated, optimal quality of results (QoR) in final implementation
  • Quantus QRC Extraction Solution: Offers best-in-class accuracy versus foundry baseline; faster, scalable cell-level and transistor-level extraction; multi-patterning; multi-coloring; and a built-in 3D extraction capability, Quantus Field Solver (FS)
  • Conformal Logic Equivalence Checking (LEC): Ensures the correctness of logic changes and engineering change orders (ECOs) as well as the implementation flow, while enabling the comparison of different views/abstraction levels
  • Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs
  • Tempus Timing Signoff Solution: Provides integrated, advanced process delay calculation and static timing analysis (STA) that achieves Samsung’s accuracy requirements, including those at low voltage operation
  • Voltus IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy
  • Physical Verification System: Includes advanced technologies and rule decks to support design rule checking (DRC), layout versus schematic (LVS), smart metal fill, yield scoring, voltage-dependent checks, and in-design signoff
  • Litho Physical Analyzer: Enables designers to detect and automatically repair process hotspots to improve design manufacturability and yield of digital, custom and mixed-signal designs, libraries and IP. This is part of Samsung’s foundry DFM offering.
  • Cadence CMP Predictor: Predicts the 3D topology variation and hotspots caused by chemical mechanical polishing (CMP) to improve design manufacturability and reduce topology variation. This is part of Samsung’s foundry DFM offering.
  • LDE Electrical Analyzer: Allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate analog design convergence
  • Modus Test Solution: Provides scan and logic/memory built-in self test (BIST) insertion, combined with a new physically aware 2D Elastic Compression architecture, enabling design engineers to achieve reductions in test time to minimize production test cost

“Samsung and Cadence collaborated closely on this new 10LPP process reference flow to provide our mutual customers with a fast path to design closure,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “Cadence’s digital and signoff tools have implemented methodology innovations that enable designers to access and reap the benefits of our 10LPP process.”

“Samsung’s certification of the Cadence digital tools enables customers to manage and overcome complexity and deliver advanced 10LPP designs faster,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Customers using the Cadence flow on Samsung’s latest 10LPP process can also achieve optimal power, performance and area (PPA) to meet their aggressive time-to-market requirements.”

SEMICON Europa will open its doors tomorrow, showcasing the latest product, tools, and technologies for advanced microelectronics manufacturing. Co-located with the IoT Planet exhibition at the Alpexpo in Grenoble, France, SEMICON Europa features more than 400 international exhibitors representing all segments and sectors of the semiconductor supply chain. SEMICON Europa 2016 will run from 25-27 October.

Presenting and attending companies include Intel, STMicroelectronics, CEA-Leti, imec, GLOBALFOUNDRIES, INFINEON, EVG, Sony, among others.  The market data and technological developments and strategies presented will keep attendees informed about current industry practices and achievements and help propel them into the future of the electronics industry.

SEMICON Europa sessions and conferences, including the Fab Management Forum, Advanced Packaging Conference, Imaging Conference, Power Electronics Conference, and the new 2016FLEX Europe Conference offer attendees a real connection to the complete electronics supply chain, from silicon to system, with a strong emphasis on application-driven markets, including imaging, power electronics, automotive, MedTech, and flexible hybrid electronics (FHE).

More than 6,000 industry professionals are expected to attend this year’s event. In addition to the exhibition and conferences, dozens of start-up and early-stage companies and more than 60 speakers will participate in the Innovation Village program. Located on the SEMICON show floor, Innovation Village showcases start-up talent, incubators, and investment opportunities within Europe and abroad.

For more information visit www.semiconeuropa.org.

ams AG (SIX: AMS), a provider of high performance sensors and analog ICs, a provider of high performance sensors and analog ICs, has announced its fast and cost-efficient IC prototyping service, known as Multi-Project Wafer (MPW) or shuttle run, with an updated schedule for 2017. The prototyping service, which combines several IC designs from different customers onto a single wafer, offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among all shuttle participants.

ams’ best in class MPW service offers the whole range of 180nm and 0.35μm specialty processes including the recently introduced 180nm CMOS technology (“aC18”). The aC18 process supports a large number of 1.8V and 5.0V NMOS and PMOS devices (substrate based, floating, low leakage and high threshold voltage options) and fully characterised passives including various capacitors. Area-optimised high-density and low-power digital libraries with gate densities up to 152kGates/mm², updated digital and analog I/O libraries with up to 6 metal layers as well as ESD protection cells with up to 8kV HBM level complete the offering. ams’ aC18 process is ideally suited for sensor and sensor interface devices in a wide variety of applications. All 2017 MPW runs in aC18 technology will be manufactured in ams’ state of the art 200mm fabrication facility in Austria ensuring very low defect densities and high yields.

In addition to the four aC18 MPW runs, ams will also offer four MPW runs in its advanced 180nm High-Voltage CMOS (aH18) technology supporting 1.8V, 5V, 20V and 50V devices. For its 0.35μm specialty processes a total of 14 runs are offered in 2017. ams’ 0.35μm High-Voltage CMOS process family, optimised for high-voltage designs in automotive and industrial applications, supports 20V, 50V and 120V devices as well as truly voltage scalable transistors. The advanced High-Voltage CMOS process with embedded EEPROM functionality as well as the 0.35μm SiGe-BiCMOS technology S35 are fully compatible with the base CMOS process and complete ams’ MPW service portfolio.

Overall, ams will offer almost 150 MPW start dates in 2017, enabled by co-operations with worldwide partner organisations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies.

The complete schedule for 2017 has now been released and detailed start dates per process are available on the web atwww.ams.com/MPW.

To take advantage of the MPW service, ams’ foundry customers deliver their completed GDSII-data on specific dates and receive untested packaged samples or dies within a short lead-time of typically 8 weeks for CMOS and 12 weeks for High-Voltage CMOS, SiGe-BiCMOS and Embedded Flash processes.

All process technologies are supported by the well-known hitkit, ams’ industry benchmark process design kit based on Cadence, Mentor Graphics or Keysight ADS design environments. The hitkit comes complete with fully silicon-qualified standard cells, periphery cells and general purpose analog cells such as comparators, operational amplifiers, low power A/D and D/A converters. Custom analog and RF devices, physical verification rule sets for Assura and Calibre, as well as precisely characterised circuit simulation models enable rapid design starts of complex high performance mixed-signal ICs. In addition to standard prototype services, ams also offers advanced analog IP blocks, a memory (RAM/ROM) generation service and packaging services in ceramic or plastic.

Learn more about the comprehensive service and technology portfolio of Full Service Foundry at www.ams.com/foundry.

SEMI and Messe München today announced that SEMICON Europa will co-locate with productronica and electronica (alternating years) in Munich, Germany. For the first time, the co-located events (productronica and SEMICON Europa) will be held next year (14-17 November 2017), creating the strongest single event for electronics manufacturing in Europe, and broadening the range of attendees across the electronics supply chain.

productronica, the world’s leading trade fair for electronics development and production, and electronica, the world’s leading trade fair for electronic components, systems and applications, will now offer attendees an extended platform. With the inclusion of SEMICON Europa, which is focused on the electronics manufacturing supply chain and largely the semiconductor manufacturing, the co-located events will expand attendee opportunities to exchange ideas and promote technological progress.

Falk Senger, managing director of Messe München, says: “The co-location of these events strengthens the global orientation of electronica and productronica, in addition to reinforcing the importance of Munich as one of the epicenters of the international electronics industry.”

SEMICON Europa features the most advanced and innovative electronics manufacturing platform in Europe. Key segments include: semiconductor front-end and back-end manufacturing, MEMS/sensors, secondary equipment, advanced packaging, and applications such as the Internet of Things (IoT).

“The co-location of SEMICON Europa with productronica and electronica is an excellent fit with SEMI’s global trade association strategy to connect the breadth of the global electronics manufacturing supply chain. SEMICON Europa brings a wide range of focused programs that address Europe’s electronics manufacturing issues and opportunities,” says Denny McGuirk, president and CEO of SEMI.

Munich is a convenient central location in Europe with easy access for international visitors. The co-located events will brings tens of thousands of visitors together to connect for electronics business.

To learn more about SEMI (and SEMICON Europa) and Messe München  (and electronica and productronica), please visit the websites.

A new design for solar cells that uses inexpensive, commonly available materials could rival and even outperform conventional cells made of silicon.

A tandem perovskite solar cell boosts efficiency by absorbing high- and low-energy photons from the sun. Credit: Rongrong Cheacharoen/Stanford University

A tandem perovskite solar cell boosts efficiency by absorbing high- and low-energy photons from the sun. Credit: Rongrong Cheacharoen/Stanford University

Writing in the Oct. 21 edition of Science, researchers from Stanford and Oxford describe using tin and other abundant elements to create novel forms of perovskite – a photovoltaic crystalline material that’s thinner, more flexible and easier to manufacture than silicon crystals.

“Perovskite semiconductors have shown great promise for making high-efficiency solar cells at low cost,” said study co-author Michael McGehee, a professor of materials science and engineering at Stanford. “We have designed a robust, all-perovskite device that converts sunlight into electricity with an efficiency of 20.3 percent, a rate comparable to silicon solar cells on the market today.”

The new device consists of two perovskite solar cells stacked in tandem. Each cell is printed on glass, but the same technology could be used to print the cells on plastic, McGehee added.

“The all-perovskite tandem cells we have demonstrated clearly outline a roadmap for thin-film solar cells to deliver over 30 percent efficiency,” said co-author Henry Snaith, a professor of physics at Oxford. “This is just the beginning.”

Tandem technology

Previous studies showed that adding a layer of perovskite can improve the efficiency of silicon solar cells. But a tandem device consisting of two all-perovskite cells would be cheaper and less energy-intensive to build, the authors said.

“A silicon solar panel begins by converting silica rock into silicon crystals through a process that involves temperatures above 3,000 degrees Fahrenheit (1,600 degrees Celsius),” said co-lead author Tomas Leijtens, a postdoctoral scholar at Stanford. “Perovskite cells can be processed in a laboratory from common materials like lead, tin and bromine, then printed on glass at room temperature.”

But building an all-perovskite tandem device has been a difficult challenge. The main problem is creating stable perovskite materials capable of capturing enough energy from the sun to produce a decent voltage.

A typical perovskite cell harvests photons from the visible part of the solar spectrum. Higher-energy photons can cause electrons in the perovskite crystal to jump across an “energy gap” and create an electric current.

A solar cell with a small energy gap can absorb most photons but produces a very low voltage. A cell with a larger energy gap generates a higher voltage, but lower-energy photons pass right through it.

An efficient tandem device would consist of two ideally matched cells, said co-lead author Giles Eperon, an Oxford postdoctoral scholar currently at the University of Washington.

“The cell with the larger energy gap would absorb higher-energy photons and generate an additional voltage,” Eperon said. “The cell with the smaller energy gap can harvest photons that aren’t collected by the first cell and still produce a voltage.”

The smaller gap has proven to be the bigger challenge for scientists. Working together, Eperon and Leijtens used a unique combination of tin, lead, cesium, iodine and organic materials to create an efficient cell with a small energy gap.

“We developed a novel perovskite that absorbs lower-energy infrared light and delivers a 14.8 percent conversion efficiency,” Eperon said. “We then combined it with a perovskite cell composed of similar materials but with a larger energy gap.”

The result: A tandem device consisting of two perovskite cells with a combined efficiency of 20.3 percent.

“There are thousands of possible compounds for perovskites,” Leijtens added, “but this one works very well, quite a bit better than anything before it.”

Seeking stability

One concern with perovskites is stability. Rooftop solar panels made of silicon typically last 25 years or more. But some perovskites degrade quickly when exposed to moisture or light. In previous experiments, perovskites made with tin were found to be particularly unstable.

To assess stability, the research team subjected both experimental cells to temperatures of 212 degrees Fahrenheit (100 degrees Celsius) for four days.

“Crucially, we found that our cells exhibit excellent thermal and atmospheric stability, unprecedented for tin-based perovskites,” the authors wrote.

“The efficiency of our tandem device is already far in excess of the best tandem solar cells made with other low-cost semiconductors, such as organic small molecules and microcrystalline silicon,” McGehee said. “Those who see the potential realize that these results are amazing.”

The next step is to optimize the composition of the materials to absorb more light and generate an even higher current, Snaith said.

“The versatility of perovskites, the low cost of materials and manufacturing, now coupled with the potential to achieve very high efficiencies, will be transformative to the photovoltaic industry once manufacturability and acceptable stability are also proven,” he said.

Researchers have found an unexpected way to control the thermal conductivity of two-dimensional (2-D) materials, which will allow electronics designers to dissipate heat in electronic devices that use these materials.

2-D materials have a layered structure, with each layer having strong bonds horizontally, or “in plane,” and weak bonds between the layers, or “out of plane.” These materials have unique electronic and chemical properties, and hold promise for use in creating flexible, thin, lightweight electronic devices.

For many of these potential applications, it’s important to be able to dissipate heat efficiently. And this can be tricky. In 2-D materials, heat is conducted differently in plane than it is out of plane.

For example, in one class of 2-D materials, called TMDs, heat is conducted at 100 watts per meter per Kelvin (W/mK) in plane, but at only 2 W/mK out of plane. That gives it a “thermal anisotropy ratio” of about 50.

To better understand the thermal conduction properties of 2-D materials, a team of researchers from North Carolina State University, the University of Illinois at Urbana-Champaign (UI) and the Toyota Research Institute of North America (TRINA) began experimenting with molybdenum disulfide (MoS2), which is a TMD.

The researchers found that, by introducing disorder to the MoS2, they could significantly alter the thermal anisotropy ratio.

The researchers created this disorder by introducing lithium ions between the layers of MoS2. The presence of the lithium ions does two things simultaneously: it puts the layers of the 2-D material out of alignment with each other, and it forces the MoS2 to rearrange the structure of its component atoms.

When the ratio of lithium ions to MoS2 reached 0.34, the in-plane thermal conductivity was 45 W/mK, and the out-of-plane thermal conductivity dropped to 0.4 W/mK- increasing the material’s thermal anisotropy ratio from 50 to more than 100. In other words, heat became more than twice as likely to travel in plane — along the layer, rather than between the layers.

And that was as good as it got. Adding fewer lithium ions made the thermal anisotropy ratio lower. Adding more ions also made it lower. But in both cases, the ratio was affected in a predictable way, meaning that the researchers could tune the material’s thermal conductivity and thermal anisotropy ratio.

“This finding was very counter-intuitive,” says Jun Liu, an assistant professor of mechanical and aerospace engineering at NC State and co-corresponding author of a paper describing the work. “The conventional wisdom has been that introducing disorder to any material would decrease the thermal anisotropy ratio.

“But based on our observations, we feel that this approach to controlling thermal conductivity would apply not only to other TMDs, but to 2-D materials more broadly,” Liu says.

“We set out to advance our fundamental understanding of 2-D materials, and we have,” Liu adds. “But we also learned something that is likely to be of practical use for the development of technologies that make use of 2-D materials.”

North America-based manufacturers of semiconductor equipment posted $1.60 billion in orders worldwide in September 2016 (three-month average basis) and a book-to-bill ratio of 1.05, according to the September Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.05 means that $105 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in September 2016 was $1.60 billion. The bookings figure is 8.5 percent lower than the final August 2016 level of $1.75 billion, and is 3.2 percent higher than the September 2015 order level of $1.55 billion.

The three-month average of worldwide billings in September 2016 was $1.53 billion. The billings figure is 10.2 percent lower than the final August 2016 level of $1.71 billion, and is 2.6 percent higher than the September 2015 billings level of $1.50 billion.

“Semiconductor equipment bookings continue to outpace equipment billings,” said Denny McGuirk, president and CEO of SEMI.  “Year-to-date bookings and billings data are on trend to surpass last year’s levels.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
April 2016

$1,460.2

$1,595.4

1.09
May 2016

$1,601.5

$1,750.5

1.09
June 2016

$1,715.2

$1,714.3

1.00
July 2016

$1,707.9

$1,795.4

1.05
August 2016 (final)

$1,709.0

$1,753.4

1.03
September 2016 (prelim)

$1,534.4

$1,604.1

1.05

Source: SEMI (www.semi.org), October 2016

Avalanche Technology, Inc., has entered into a manufacturing agreement with Sony Semiconductor Manufacturing Corporation to begin production of it’s Spin Transfer Torque Magnetic RAM (STT-MRAM) on 300mm wafers at various advanced geometry nodes.  Volume production is expected in early 2017 at Sony Semiconductor Manufacturing Corporation in Japan to address a wide range of applications for this disruptive non-volatile memory technology.

This partnership with Sony Semiconductor Manufacturing Corporation will help the adoption of perpendicular Magnetic Tunnel Junction (pMTJ)-based STT-MRAM and further validate the widely accepted industry belief that STT-MRAM is the memory technology of choice for a broad spectrum of applications.

“Avalanche is working on breakthrough memory products.  As a result, we are able to address a very large non-volatile memory market with a wide range of requirements.  STT-MRAM is an ideal solution for markets such as Storage, Automotive, IoT and embedded applications,” said Petro Estakhri, founder and CEO of Avalanche Technology.

“We are pleased to partner with Avalanche Technology on the production of pMTJ based STT-MRAM,” said Toshiyuki Yanase, Representative of Yamagata Technology Center of Sony Semiconductor Manufacturing Corporation.  “Working with Avalanche Technology, we look forward to manufacturing MRAM products that meet current and future demands in the memory market.”

The U.S. Air Force Research Laboratory and the Office of the Secretary of Defense have awarded Raytheon Company [NYSE: RTN] a $14.9M contract to further enhance its process for producing gallium nitride-based semiconductors. The new agreement follows a previous GaN Title III contract, completed in 2013, and aims to increase the performance, yield and reliability of Raytheon GaN-based, wideband, monolithic, microwave-integrated circuits and circulator components.

GaN is a semiconductor material that can efficiently amplify high power radio frequency signals at microwave frequencies thereby enhancing a system’s range and raid handling, while reducing size, weight, power and cost. It is used in a broad spectrum of military radars and defense systems, including the U.S. Navy’s Air and Missile Defense Radar and Next Generation Jammer.

“We have only scratched the surface when it comes to harnessing the game-changing power that gallium nitride technology can bring to military applications,” said Colin Whelan, vice president of Advanced Technology in Raytheon’s Integrated Defense Systems business unit. “This contract will build on the 17-year, two-hundred-plus million-dollar investment Raytheon has made in maturing GaN. Over the next two years, we will further refine our GaN process to push the limits of radio frequency performance while maintaining or increasing yield and reliability.”

The first demonstrator of this technology will be incorporated into Raytheon Space and Airborne Systems’ Next Generation Jammer program, which is scheduled for low-rate initial production in 2018.

Researchers at the Nanoscale Transport Physics Laboratory from the School of Physics at the University of the Witwatersrand have found a technique to improve carbon superlattices for quantum electronic device applications. Superlattices are made up of alternating layers of very thin semiconductors, just a few nanometers thick. These layers are so thin that the physics of these devices is governed by quantum mechanics, where electrons behave like waves. In a paradigm shift from conventional electronic devices, exploiting the quantum properties of superlattices holds the promise of developing new technologies.

A schematic atomic diagram of a quantum well made from amorphous carbon layers. The blue atoms represent amorphous carbon with a high percentage of diamond-like carbon. The maroon atoms represent amorphous carbon which is graphite-like. The diamond-like regions have a high potential (diamond is insulating) while the graphite-like regions are more metallic. This creates a quantum well as electrons are confined within the graphite-like region due to the relatively high potential in the diamond-like regions. Superlattices are made up of a series of quantum wells. Credit: Wits University

A schematic atomic diagram of a quantum well made from amorphous carbon layers. The blue atoms represent amorphous carbon with a high percentage of diamond-like carbon. The maroon atoms represent amorphous carbon which is graphite-like. The diamond-like regions have a high potential (diamond is insulating) while the graphite-like regions are more metallic. This creates a quantum well as electrons are confined within the graphite-like region due to the relatively high potential in the diamond-like regions. Superlattices are made up of a series of quantum wells. Credit: Wits University

The group, headed by Professor Somnath Bhattacharyya has been working for the past 10 years on developing carbon-based nano-electronic devices.

“Carbon is the future in the electronics field and it soon will be challenging many other semiconductors, including silicon,” says Bhattacharyya.

The physics of carbon superlattices is more complex than that of crystalline superlattices (such as gallium arsenide), since the material is amorphous and carbon atoms tend to form chains and networks. The Wits group, in association with researchers at the University of Surrey in the UK, has developed a detailed theoretical approach to understand the experimental data obtained from carbon devices. The paper has been published in Scientific Reports (Nature Publishing Group) on 19 October.

“This work provides an understanding of the fundamental quantum properties of carbon superlattices, which we can now use to design quantum devices for specific applications,” says lead author, Wits PhD student, Ross McIntosh. “Our work provides strong impetus for future studies of the high-frequency electronic and optoelectronic properties of carbon superlattices”.

Through their work, the group reported one of the first theoretical models that can explain the fundamental electronic transport properties in disordered carbon superlattices.

Bhattacharyya started looking at the use of carbon for semiconductor applications almost 10 years ago, before he joined Wits University, when he and co-authors from the University of Surrey developed and demonstrated negative differential resistance and excellent high-frequency properties of a quantum device made up of amorphous carbon layers. This work was published in Nature Materials in 2006.

McIntosh undertook the opportunity at honours level to measure the electrical properties of carbon superlattice devices. Now, as a PhD student and having worked extensively with theoretician Dr. Mikhail V. Katkov, he has extended the theoretical framework and developed a technique to calculate the transport properties of these devices.

Bhattacharyya believes this work will have immense importance in developing Carbon-based high-frequency devices.

“It will open not only fundamental studies in Carbon materials, but it will also have industrial applications in the electronic and optoelectronic device sector,” he says.

Superlattices are currently used as state of the art high frequency oscillators and amplifiers and are beginning to find use in optoelectronics as detectors and emitters in the terahertz regime. While the high frequency electrical and optoelectronic properties of conventional semiconductors are limited by the dopants used to modify their electronic properties, the properties of superlattices can be tuned over a much wider range to create devices which operate in regimes where conventional devices cannot.

Superlattice electronic devices can operate at higher frequencies and optoelectronic devices can operate at lower frequencies than their conventional counterparts. The lack of terahertz emitters and detectors has resulted in a gap in that region of the electromagnetic spectrum (known as the “terahertz gap”), which is a significant limitation, as many biological molecules are active in this regime. This also limits terahertz radio astronomy.

Amorphous Carbon devices are extremely strong, can operate at high voltages and can be developed in most laboratories in the world, without sophisticated nano-fabrication facilities. New Carbon-based devices could find application in biology, space technology, science infrastructure such as the Square Kilometre Array (SKA) telescope in South Africa, and new microwave detectors.

“What was lacking earlier was an understanding of device modelling. If we have a model, we can improve the device quality, and that is what we now have,” says Bhattacharyya.