Category Archives: Wafer Processing

MagnaChip Semiconductor Corporation (“MagnaChip”) (NYSE:  MX), a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, announced today the availability of a new 0.13 micron Slim Flash process technology, based on 0.13 micron EEPROM.  While maintaining the same performance characteristics of the existing EEPROM process, Slim Flash process technology is highly cost competitive because it reduces the number of layers to be embedded by 20 percent and cuts the manufacturing turnaround time by 15 percent.

The embedded NVM (Non-Volatile Memory) EEPROM process, integrates logic, analog, and memory into one chip, and has been adopted in a wide range of applications such as automotive, MCU, touch IC and Auto Focus IC.

Qualification test for 0.13 micron Slim Flash process technology was completed in both device performance and yield categories.  All devices passed the WLR (Wafer Level Reliability) test, SRAM, and reliability test of standard cell library.  In particular, high density EEPROM IP satisfied all categories related to endurance and data retention test.

In addition to the existing 0.13 micron EEPROM, MagnaChip plans to build a Slim Flash portfolio by merging Slim Flash into various technologies, including BCD and High Voltage.  MagnaChip is currently engaging with customers using the new technology, with several products currently in development. Volume production of the Slim Flash process technology is expected to begin as early as the fourth quarter of 2016.

“With the introduction of our 0.13 micron Slim Flash process technology, customers now have access to a cost-saving and time-saving manufacturing process that will improve their overall time to market,” said YJ Kim, Chief Executive Officer of MagnaChip.

Brewer Science was honored by the Missouri Association of Manufacturers with a Made in Missouri Leadership Award (MMLA) for Sustainability Leadership. The award honors innovative Missouri manufacturers and leaders that are shaping the future of global manufacturing.

Brewer Science received recognition for the development and implementation of a robust and strategic environmental program, which led to a program that was certified Zero Waste to Landfill The impact of this certification reinforces Brewer Science’s commitment to the environment, both internally and externally.

“Environmental responsibility does not require an ROI – it is a simple truth and it adds value to our company, but more importantly to the global community,” said Tom Brown, Executive Director, Corporate Production and Sustainability. “Reducing the environmental footprint at Brewer Science has also had a positive impact on the region and in our approach to business by allowing us to contain costs through improved efficiencies.”

“In addition to monitoring and managing our waste, Brewer Science has continued a partnership with the community by helping stakeholders properly dispose of their waste,” said Matt Beard, Director of Integrated Management Systems. “By working with the City of Rolla, the Ozark Rivers Solid Waste Management District, the Missouri Department of Natural Resources, the Meramec Regional Planning Commission, and the Phelps County Commission, Brewer Science provides area residents with community collections that have enabled them to properly dispose of almost 811,000 pounds of waste over the past 11 years.”

Brewer Science is a developer and manufacturer of materials, processes, and equipment for the fabrication of semiconductors and microelectronic devices. With its headquarters in Rolla, Missouri, Brewer Science supports customers throughout the world with a service and distribution network in North America, Europe, and Asia. Brewer Science has earned the Zero Waste to Landfill certification from GreenCircle Certification LLC.

By Paula Doe, SEMI

As the rate of traditional scaling slows, the chip sector looks increasingly to materials and design to move forward on multiple paths for multiple applications. Figuring out more effective ways to collaborate across silos will be crucial.

Source: IBM [IBM slide 6 in Strategic Materials Conference deck]

Source: IBM [IBM slide 6 in Strategic Materials Conference deck]

  1. Paradigm shift requires co-optimization

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“Scaling has hit a wall, and there is no longer any single path forward,” noted Larry Clevenger, BEOL Architect and Technology Definition, IBM Research, at the SEMI Strategic Materials Conference 2016 (September 20-21). “The materials set we use in the middle and back end of line is running out of steam. We need new materials and design co-optimization.”  He noted EUV would much improve the critical tight pitch areas for the memory and BEOL for 7nm-5nm logic. But reducing the parasitics in the metal interconnect in middle of the line and BEOL will also be critical, with good results demonstrated from new materials like Si:P and Ge:Ga meta-stable alloys, cobalt instead of tungsten, self-forming encapsulation of copper by cobalt, and airgaps, all of which would require optimization of an ecosystem of appropriate cleaning, deposition and wet process technologies for integration. Changing the design to route the critical paths directly up to higher wiring levels where the wires are larger would also help reduce resistance.

“It’s a paradigm shift that what was once a process deviation is now an excursion,” said Archita Sengupta, Intel senior technologist, noting the need for new specialized tools to measure, monitor and control the process to detect ever tinier defects sooner. “We need more proactive cooperation across the supply chain for bottom up control of quality from suppliers.”

Showing impressive examples of imaging and computation enabling doctors to reduce errors in breast cancer detection by 85 percent, and even to operate on a beating heart, using Nvidia GPUs and artificial intelligence, Nvidia’s director of Advanced Technology John Hu noted, “We are at a real inflection point for demand for more compute power, and we can’t get there by just process scaling any more. We are going to have to rely on new architectures to rescue us from the increasingly imperfect reality of materials and processes.”

While almost every speaker stressed the increasing need for the different segments of the supply chain from materials to design to work more closely together to move technology forward along many new paths, the materials suppliers in the audience felt that progress could be better to make this happen. Some audience members talked among themselves of now being invited more often into the fabs to discuss material development, but still not being told much detail about the key target parameters. Material suppliers in the audience raised the issues of the time and expense needed to qualify their second sources for raw materials and precursors, to get the needed environmental certifications, and to find access to the expensive exotic multi-technology metrology tools capable of finding contaminates too small to see with conventional methods, before they could even bring in any potential material to be evaluated for use several years in the future.

Although speakers kept referring to the past Golden Age of Moore’s Law of regular two-year dimensional scaling, before the proliferation of alternatives, Tim Hendry, retiring Intel VP, Fab Materials, pointed out that it hadn’t really seemed like a Golden Age at the time. “As I remember, we thought it was pretty hard back then too.”

  1. Look to self-aligned and selective processes as scaling boosters

As lithography scaling slows down, new approaches will make creative use of deposition and etch to keep improving pattern resolution. “14nm is a real sweet spot technically for lithography that will be with us for a long time,” noted Anton DeVilliers, Tokyo Electron America director of Patterning Technology, suggesting a toolkit of assorted self-alignment and selective deposition and etch processes likely to see increasing use as resolution boosters as an alternative to pushing the lithography, such as collars at key points to protect the pattern, or self aligned patterning by selective etching.

Adding a protective ALD collar holds a key region open during etch to widen the process window and prevent shorts from process variation in tight pattern areas.

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ALD snap collar holds the critical part of M1 pattern open to widen window in LELELE process…

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So that overlay variation that would typically create a short…

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Instead creates the desired pattern. Source: TEL

Using materials with different etch selectivity for different parts of a pattern, such as for alternate lines, enables the creation of a self aligned pattern at higher resolution than the lithography.  Different etch selectivity in alternate metal tracks could also reduce the number of exposure passes and improve overlay tolerance. “For 5nm nanowires, we’ll have to use selective ALD and ALE, controlled by self assembling monolayers,” noted DeVilliers. “We’ve done each of these steps on a tool, but now the challenge is to put them all together.”

  1. Progress on 3D alternatives

“To maintain the pace of progress we’ll have to change everything—we can’t do it with Moore’s Law,” said Bill Bottoms, chairman and CEO, Third Millennium Test Solutions, updating on the international effort to create a Heterogeneous Integration Roadmap. “Future progress will come from bringing active elements closer together through integration at the system level, with interconnect with photonics and plasmonics.” The aim is to map future needs to better enable precompetitive collaboration. The first edition of the roadmap is now slated to come out in March.

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CEA-Leti researchers meanwhile are reporting good progress on lowering the temperatures of the various processes needed to build a second chip directly on top of a first, for monolithic 3D CMOS-on-CMOS integration.  Performance of the bottom chip degrades if the process temperatures for the top chip are >500°C, mainly because the NiPt silicide deteriorates, but replacing the NiPt with a more stable NiCo and adding an Si cap looks promising to increase stability. The 8nm active active layer for the top device is bonded atop the bottom device at room temperature and annealed 300C. Nanosecond laser thermal annealing and low temperature solid phase epitaxy regrowth help bring down temperatures for dopant activation. Cycles of deposition and etch replace selective epitaxy for the source and drain, while different precursors reduce process temperatures to 500-550C. “Later this year at IEDM we’ll demonstrate top CMOS made at 500°C with these developments,” said Philippe Rodriguez, CEA-Leti research engineer.

  1. Get used to the slow growth world 

The semiconductor industry will see silicon demand (MSI) pick up from this year’s 0.6 percent increase to  ~3.8 percent growth in 2017, and ~6.3 percent in 2018, as some uncertainty about interest rates and government policy in major countries resolves, according to the econometric semiconductor forecast from Hilltop Economics and LINX Consulting. “We got comfortable with 3 percent GDP growth in the world that we sell chips into, but since the 2009 recession we are only seeing about 2.4 percent growth,” said Duncan Meldrum, chief economist, Hilltop Economics. He noted that economists keep saying the world will get back to its regular 3 percent growth next quarter or year, but it hasn’t happened, probably because high government debt levels in most major economies tends to reduce growth by about reduces it. Silicon demand grows a little faster than GDP, but its trends generally track that global growth number more than in the past as the electronics industry matures.

  1. Wafer level fan out will shake up package materials sector

Now that it appears the 40 to 50 percent improvement in performance in the newest Apple A10 processor is largely from its wafer-level fan out packaging from TSMC, demand for the packaging approach is ramping fast. “This is one of the fastest ramps we’ve seem for a package in a long time,” said TechSearch International president Jan Vardaman. “It’s a very disruptive technology that will have a big impact on the industry.” The thinner, lower-cost packaging approach is also showing up in RF and audio codec chips in mobile phones, with  ~2 billion units just in Samsung and Apple phones, potentially bringing big changes to the packaging materials market. Laminate substrate suppliers will see demand plunge, copper post suppliers will see little change, and makers of wafer-level dielectrics could potentially see 3X growth in volume. “But don’t think you’ll see that in revenue, since customers will really beat the prices down.”

And in a final note, the gathered materials sector paused in a moment of silence for Dan Rose, who passed away on September 19.  Dan was a well-known market researcher and founder of Rose Associates with a focus on materials market data.

Originally published on the SEMI blog.

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry business. An excerpt from the September Update, describing foundry sales by feature size, is shown below.

Figure 1

Figure 1

TSMC has long been the technology leader among the major pure-play foundries. As shown in Figure 1, 54% of TSMC’s 2016 revenue is expected to come from <40nm processing. GlobalFoundries, which has dedicated a large portion of its capacity to making advanced processors over the past few years, also generates a large portion of its sales based on leading-edge process technology and feature sizes. In 2016, 52% of GlobalFoundries’ sales are forecast to come from <40nm production.

Although GlobalFoundries and TSMC are forecast to have a similar share of their sales dedicated to <40nm technology this year, TSMC is expected to have almost 6x the sales volume at <40nm as compared to GlobalFoundries in 2016 ($15.6 billion for TSMC and $2.6 billion for GlobalFoundries). In contrast, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.

Because TSMC has a very large percentage of its sales targeting <40nm production, its revenue per wafer is forecast to increase at a CAGR of 3% from 2011 through 2016 as compared to a -1% CAGR expected for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC over this same timeperiod. Only 2% of SMIC’s 2016 sales are expected to come from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so low as compared to TSMC and GlobalFoundries.

It is interesting to note that the increase in pure-play foundry sales this year is forecast to be almost entirely due to <40nm feature size device sales (Figure 2). Although it is expected to represent 60% of total pure-play foundry sales in 2016, the ≥40nm pure-play IC foundry market is forecast to be flat this year. In contrast, the leading-edge <40nm pure-play foundry market in 2016 is expected to surge by 23%, increasing by a hefty $3.6 billion.

Figure 2

Figure 2

North America-based manufacturers of semiconductor equipment posted $1.75 billion in orders worldwide in August 2016 (three-month average basis) and a book-to-bill ratio of 1.03, according to the August Equipment Market Data Subscription (EMDS) Book-to-Bill Report published by SEMI.  A book-to-bill of 1.03 means that $103 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in August 2016 was $1.75 billion. The bookings figure is 2.3 percent lower than the final July 2016 level of $1.80 billion, and is 5.0 percent higher than the August 2015 order level of $1.67 billion.

The three-month average of worldwide billings in August 2016 was $1.71 billion. The billings figure is approximately the same as the final July 2016 level of $1.71 billion, and is 8.4 percent higher than the August 2015 billings level of $1.58 billion.

“The book-to-bill ratio has been at or above parity since December of last year with current monthly bookings and billings levels at $1.7 billion,” said Denny McGuirk, president and CEO of SEMI.  “Given the current data trends, North American equipment suppliers are clearly benefiting from strong investments by device manufacturers in the second half of the year.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

  Billings
(3-mo. avg)		 Bookings
(3-mo. avg)		 Book-to-Bill
March 2016  $1,197.6 $1,379.2 1.15
April 2016  $1,460.2 $1,595.4 1.09
May 2016  $1,601.5 $1,750.5 1.09
June 2016  $1,715.2 $1,714.3 1.00
July 2016 (final) $1,707.9 $1,795.4 1.05
August 2016 (prelim) $1,708.1 $1,753.9 1.03

Source: SEMI (www.semi.org), September 2016

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the SEMI Equipment Market Data Subscription (EMDS).

By David W. Price and Douglas G. Sutherland

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing. 

Introduction

In a previous Process Watch article [1], we showed that big excursions are usually easy to detect but finding small excursions requires a combination of high capture rate and low noise. We also made the point that, in our experience, it’s usually the smaller excursions which end up costing the fab more in lost product. Catastrophic excursions have a large initial impact but are almost always detected quickly. By contrast, smaller “micro-excursions” sometimes last for weeks, exposing hundreds or thousands of lots to suppressed yield.

Figure 1 shows an example of a micro-excursion. For reference, the top chart depicts what is actually happening in the fab with an excursion occurring at lot number 300. The middle chart shows the same excursion through the eyes of an effective inspection strategy; while there is some noise due to sampling and imperfect capture rate, it is generally possible to identify the excursion within a few lots. The bottom chart shows how this excursion would look if the fab employed a compromised inspection strategy—low capture rate, high capture rate variability, or a large number of defects that are not of interest; in this case, dozens of lots are exposed before the fab engineer can identify the excursion with enough confidence to take corrective action.

Figure 1. Illustration of a micro-excursion. Top: what is actually happening in the fab. Middle: the excursion through the lens of an effective control strategy (average 2.5 exposed lots). Bottom: the excursion from the perspective of a compromised inspection strategy (~40 exposed lots).

Figure 1. Illustration of a micro-excursion. Top: what is actually happening in the fab. Middle: the excursion through the lens of an effective control strategy (average 2.5 exposed lots). Bottom: the excursion from the perspective of a compromised inspection strategy (~40 exposed lots).

Unfortunately, the scenario depicted in the bottom of Figure 1 is all too common. Seemingly innocuous cost-saving tactics such as reduced sampling or using a less sensitive inspector can quickly render a control strategy to be ineffective [2]. Moreover, the fab may gain a false sense of security that the layer is being effectively monitored by virtue of its ability to find the larger excursions. 

Micro-Excursions 

Table 1 illustrates the difference between catastrophic and micro-excursions. As the name implies, micro-excursions are subtle shifts away from the baseline. Of course, excursions may also take the form of anything in between these two.

Table 1: Catastrophic vs. Micro-Excursions

Table 1: Catastrophic vs. Micro-Excursions

Such baseline shifts happen to most, if not all, process tools—after all, that’s why fabs employ rigorous preventative maintenance (PM) schedules. But PM’s are expensive (parts, labor, lost production time), therefore fabs tend to put them off as long as possible.

Because the individual micro-excursions are so small, they are difficult observe from end-of-line (EOL) yield data. They are frequently only seen in EOL yield data through the cumulative impact of dozens of micro-excursions occurring simultaneously; even then it more often appears to be baseline yield loss. As a result, fab engineers sometimes use the terms “salami slicing” or “penny shaving” since these phrases describe how a series of many small actions can, as an accumulated whole, produce a large result [3].

Micro-excursions are typically brought to an end because: (a) a fab detects them and puts the tool responsible for the excursion down; or, (b) the fab gets lucky and a regular PM resolves the problem and restores the tool to its baseline. In the latter case, the fab may never know there was a problem.

The Superposition of Multiple Simultaneous Micro-Excursions

To understand the combined impact of these multiple micro-excursions, it is important to recognize:

  1. Micro-excursions on different layers (different process tools) will come and go at different times
  2. Micro-excursions have different magnitudes in defectivity or baseline shift
  3. Micro-excursions have different durations

In other words, each micro-excursion has a characteristic phase, amplitude and wavelength. Indeed, it is helpful to imagine individual micro-excursions as wave forms which combine to create a cumulative wave form. Mathematically, we can apply the Principle of Superposition [4] to model the resulting impact on yield from the contributing micro-excursions.

Figure 2 illustrates the cumulative effect of one, five, and 10 micro-excursions happening simultaneously in a 1,000 step semiconductor process. In this case, we are assuming a baseline yield of 90 percent, that each micro-excursion has a magnitude of 2 percent baseline yield loss, and that they are detected on the 10th lot after it starts. As expected, the impact of a single micro-excursion is negligible but the combined impact is large.

Figure 2. The cumulative impact of one, five, and 10 simultaneous micro-excursions happening in a 1,000 step process: increased yield loss and yield variation.

Figure 2. The cumulative impact of one, five, and 10 simultaneous micro-excursions happening in a 1,000 step process: increased yield loss and yield variation.

It is interesting to note that the bottom curve in Figure 2 would seem to suggest that the fab is suffering from a baseline yield problem. However, what appears to be 80 percent baseline yield is actually 90 percent baseline yield with multiple simultaneous micro-excursions, which brings the average yield down to 80 percent. This distinction is important since it points to different approaches in how the fab might go about improving the average yield. A true baseline yield problem would suggest that the fab devote resources to run experiments to evaluate potential process improvements (design of experiments (DOEs), split lot experiments, failure analysis, etc.). These activities would ultimately prove frustrating as the engineers would be trying to pinpoint a dozen constantly-changing sources of yield loss.

The fab engineer who correctly surmises that this yield loss is, in fact, driven by micro-excursions would instead focus on implementing tighter process tool monitoring strategies. Specifically, they would examine the sensitivity and frequency of process tool monitor inspections; depending on the process tool, these monitors could be bare wafer inspectors on blanket wafers and/or laser scanning inspectors on product wafers. The goal is to ensure these inspections provide timely detection of small micro-excursions, not just the big excursions.

The impact of an improved process tool monitoring strategy can be seen in Figure 3. By improving the capture rate (sensitivity), reducing the number of non-critical defects (by doing pre/post inspections or using an effective binning routine), and reducing other sources of noise, the fab can bring the exposed product down from 40 lots to 2.5 lots. This, in turn, significantly reduces the yield loss and yield variation.

Figure 3. The impact of 10 simultaneous micro-excursions for the fab with a compromised inspection strategy (brown curve, ~40 lots at risk), and a fab with an effective process tool monitoring strategy (blue curve, ~2.5 lots at risk).

Figure 3. The impact of 10 simultaneous micro-excursions for the fab with a compromised inspection strategy (brown curve, ~40 lots at risk), and a fab with an effective process tool monitoring strategy (blue curve, ~2.5 lots at risk).

Summary

Most fabs do a good job of finding the catastrophic defect excursions. Micro-excursions are much more common and much harder to detect. There are usually very small excursions happening simultaneously at many different layers that go completely undetected. The superposition of these micro-excursions leads to unexplained yield loss and unexplained yield variation.

As a yield engineer, you must be wary of this. An inspection strategy that guards only against catastrophic excursions can create the false sense of security that the layer is being effectively monitored—when in reality you are missing many of these smaller events that chip away or “salami slice” your yield.

References:

About the Author: 

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Analogix Semiconductor, Inc. and Beijing Shanhai Capital Management Co, Ltd. (Shanhai Capital), today jointly announced that they have entered into a definitive merger agreement under which a consortium led by Shanhai Capital will acquire all of the outstanding shares of Analogix for over $500 million. China Integrated Circuit Industry Investment Fund Co., Ltd. (China IC Fund) also joined Shanhai Capital’s fund as one of the limited partners. The transaction is subject to regulatory approvals and is expected to close in late 2016.

Analogix’s high-speed, mixed-signal semiconductor integrated circuits (ICs) for high-performance display applications are used in mobile devices, virtual/augmented reality (VR/AR), and other high-performance electronic products from leading electronics brands including Apple, Samsung, LG, Microsoft, Google, Lenovo, Dell, HP, Asus, and HTC. The company is headquartered in Santa Clara, California, and the majority of its engineering operations are located in Beijing, China. Current investors include leading venture capital firms: DCM Ventures, Globespan Capital Partners, Keytone Ventures, and the Woodside Fund.

“We are very happy to have reached this agreement, which provides significant value to our shareholders,” said Dr. Kewei Yang, Analogix Semiconductor’s chairman and CEO. “The financial support of Shanhai Capital propels our growth while maintaining the direction, organization, and determination to serve our customers. I am especially excited that we all share the same vision of building Analogix into a much broader and more capable global semiconductor leader.”

“We are pleased to establish our relationship with Analogix, a company whose technology leadership is recognized by the world’s leading OEMs, and we look forward to facilitating Analogix’s continued growth,” said Mr. Xianfeng Zhao, Chairman of Beijing Shanhai Capital Management Co, Ltd. “With the added investment, we can leverage the strength of the company’s core technology and business expertise, extend our business into adjacent high-growth markets, and build a world-leading semiconductor company. We expect an IPO in China in the near future.”

The Semiconductor Industry Association (SIA), in consultation with Semiconductor Research Corporation (SRC), today presented its University Research Award to professors from the University of Chicago and the University of Michigan in recognition of their outstanding contributions to semiconductor research.

Dr. Paul Nealey, professor of molecular engineering at the University of Chicago, received the honor for excellence in technology research, while Dr. David T. Blaauw, professor of electrical engineering and computer science at the University of Michigan, was recognized for excellence in design research.

“Research brings to life the tremendous innovations that underpin the U.S. semiconductor industry, the broader tech sector, and our economy,” said John Neuffer, president and CEO of the Semiconductor Industry Association, which represents U.S. leadership in semiconductor manufacturing, design, and research.

“Professors Nealey and Blaauw have led research efforts that have advanced semiconductor technology and strengthened America’s global technology leadership. It is an honor to recognize Dr. Nealey and Dr. Blaauw for their landmark accomplishments.”

“SRC’s mission is to drive focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry,” said Ken Hansen, SRC President and CEO. “Dr. Nealey and Dr. Blaauw exemplify that spirit of innovation, and we’re pleased to honor them for their achievements.”

Dr. Nealey is a pioneer of directed self-assembly, which is becoming very important in microelectronics processing to create patterns for integrated circuits. He is one of the world’s leading experts on patterning organic materials. This entails creating physical patterns of structure and composition in organic materials at the nanometer length scale, where the patterns affect the function of the materials. Dr. Nealey holds 14 patents and is the author of more than 180 publications.

Dr. Blaauw worked for Motorola, Inc. from 1993-2001, where he was the manager of the High Performance Design Technology group. Since August 2001, he has been on the faculty at the University of Michigan where he is currently a full professor. His work has focused on VLSI design with particular emphasis on adaptive and low-power design. Dr. Blaauw received his B.S. from Duke University in 1986 and his Ph.D. from the University of Illinois, Urbana, in 1991.

The University Research Award was established in 1995 to recognize lifetime research contributions to the U.S. semiconductor industry by university faculty.

BY MIKE CZERNIAK, Environmental Solutions Business Development Manager, Edwards

The World Semiconductor Council (WSC) is comprised of the semiconductor industry associations (SIAs) of the United States, Korea, Japan, Europe, China and Chinese Taipei. Its goal is to promote international cooperation in the semiconductor sector in order to facilitate the healthy growth of the industry from a long-term, global perspective. Formed in 1996, the WSC early on recog- nized the industry’s obligation to respon- sibly manage its impact on the environment.

One of the council’s first acts was the issuing of a voluntary industry target to reduce the emission of perfluorinated compounds (PFC) to 10 percent below their 1995 levels by 2010. PFCs are significant greenhouse gases (GHG) and many can persist for extended periods in the atmosphere. Given the significant growth of the semiconductor industry over this 15 year period, this was a very aggressive goal. By the end of the period, all member SIAs were able to report that they had met, and in many cases, significantly exceed the stated goal. This rather impressive achievement was accomplished by two key efforts. The first was the replacement of traditional CF4 and C2F6 CVD cleaning gases with NF3, which readily dissociates in a plasma to provide fluorine, an effective cleaning gas, which, though toxic, is not a greenhouse gas. The second was the widespread adoption exhaust gas abatement.

In 2011 the industry set new targets for 2020, which it summarizes as:

• The implementation of best practices for new semicon- ductor fabs. The industry expects that the implementation of best practices will result in a normalized emission rate (NER) in 2020 of 0.22 kgCO2e/cm2, which is a 30 percent NER reduction from the 2010 aggregated baseline.

• The addition of “Rest of World” fabs (fabs located outside the WSC regions that are operated by a company from a WSC association) in reporting of emissions and the imple- mentation of best practices for new fabs.

• NER based measurement in kilograms of carbon equiva- lents per area of silicon wafers processed (kgCO2e/cm2), which will be the single WSC goal at the global level.

The original 2010 target focused primarily (and success- fully) on emissions from chemical vapour deposition (CVD) processes. The main area for potential improvement now, as illustrated by the figure, is etch, especially in older 200mm fabs where etch processes may not have been fitted with PFC abatement devices. This is particularly true for etch processes making extensive use of CF4, which has a very high global warming potential over a 100-year timescale (GWP100) of 7350, due largely to its atmospheric half-life of 50,000 years. It is extremely stable.

Some are predicting a prolonging of the productive lifetimes of 200mm fabs in conjunction with projected growth as a result of the growing market for internet of things (IoT). Many IoT devices do not require cutting-edge production technology and can be economically produced in older fabs. In any case, the onus is on our industry to continue our efforts to reduce any adverse effects on the environment we all share.

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry industry and a look at the current state of the merger and acquisition surge in the semiconductor industry. An excerpt from the M&A portion of this Update is shown below.

After an historic surge in semiconductor merger and acquisition agreements in 2015, the torrid pace of transactions has eased (until recently), but 2016 is already the second-largest year ever for chip industry M&A announcements, thanks to three major deals struck in 3Q16 that have a combined total value of $51.0 billion. As of the middle of September, announced semiconductor acquisition agreements this year have a combined value of $55.3 billion compared to the all-time high of $103.8 billion reached in all of 2015 (Figure 1). Through the first three quarters of 2015, semiconductor acquisition pacts had a combined value of about $79.1 billion, which is 43% higher than the total of the purchasing agreements reached in the same period of 2016, based on M&A data compiled by IC Insights.

In many ways, 2016 has become a sequel to the M&A mania that erupted in 2015, when semiconductor acquisitions accelerated because a growing number of suppliers turned to purchase agreements to offset slower growth in major existing end-use equipment applications (such as smartphones, PCs, and tablets) and to broaden their businesses to serve huge new market potentials, including the Internet of Things (IoT), wearable electronics, and strong segments in embedded electronics, like highly-automated automotive systems. China’s goal of boosting its domestic IC industry is also driving M&A. In the first half of 2016, it appeared the enormous wave of semiconductor acquisitions in 2015 had subsided substantially, with the value of transactions announced between January and June being just $4.3 billion compared to $72.6 billion in the same six-month period in 1H15. However, three large acquisition agreements announced in 3Q16, including SoftBank’s purchase of ARM, Analog Devices’ intended purchase of Linear Technology, and Renesas’ potential acquisition of Intersil) have insured that 2016 will be second only to 2015 in terms of the total value of announced semiconductor M&A transactions.

Figure 1

Figure 1

A major difference between the huge wave of semiconductor acquisitions in 2015 and the nearly 20 deals being struck in 2016 is that a significant number of transactions this year are for parts of businesses, divisions, product lines, technologies, or certain assets of companies.  This year has seen a surge in the agreements in which semiconductor companies are divesting or filling out product lines and technologies for newly honed strategies in the second half of this decade.