Category Archives: Wafer Processing

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, presented its highest honors Sept. 12 to professors from University of California, Berkeley and University of Minnesota at SRC’s annual TECHCON conference in Austin, Texas.

Dr. Tsu-Jae King Liu, TSMC Distinguished Professor in Microelectronics in the Department of Electrical Engineering and Computer Sciences(EECS) at UC Berkeley, received this year’s SRC Aristotle Award for outstanding teaching and a deep commitment to the educational experience of his students. With SRC support, Liu’s team at UC Berkeley has made numerous research contributions to the industry in areas including nanometer-scale semiconductor devices and technology, novel non-volatile memory devices and technology and M/NEMS technology for ultra-low-power integrated circuits.

Additionally, Dr. Chris Kim, a Professor in the Department of Electrical and Computer Engineering at Minnesota, was awarded the SRC Technical Excellence Award for his respective SRC-supported research and contributions to the industry in VLSI circuit design.

Selected by SRC member companies and SRC staff, the award-winning faculty and research teams are being recognized for their exemplary impact on semiconductor productivity through cultivation of technology and talent.

“Advanced research has been instrumental in propelling the semiconductor industry forward, and we are recognizing these valuable researchers and their teams for the critical work they have performed in helping the industry achieve technological triumphs,” said Ken Hansen, SRC CEO and President.

UC Berkeley and Minnesota research helps drive technology innovation

Dr. Liu, a member of the Kavli Energy NanoSciences Institute and Associate Dean of the College of Engineering at UC Berkeley, earned B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. Prior to joining UC Berkeley, she worked as a researcher at the Xerox Palo Alto Research Center. Dr. Liu’s current research activities include nanometer-scale logic and memory devices for energy-efficient electronics, and she currently leads research on millivolt nanomechanical switches under the NSF Center for Energy Efficient Electronics Science.

“I am very fortunate to have been able to work with many outstanding students during my career at UC Berkeley, and am humbled to receive this prominent recognition for our joint achievements,” said Dr. Liu. “SRC’s support has made it possible for us to make impactful contributions to society, for which I am very grateful.”

Dr. Kim, a recipient of the National Science Foundation’s CAREER award, received his B.S and M.S. degrees from Seoul National University and a Ph.D. from Purdue University. Prior to joining the University of Minnesota, he worked at Intel Corporation that also recognized him with an Intel Ph.D. Fellowship. His current research focuses on digital, mixed-signal and memory circuit design in advanced-CMOS and beyond-CMOS technologies.

“This award recognizes our group’s invention of a new class of compact on-chip sensors called “silicon odometers” that can accurately and efficiently measure circuit aging effects,” said Dr. Kim. “Over the span of several SRC projects, our team has experimentally demonstrated more than a dozen different odometer designs in technologies ranging from 130 to 32 nanometers.”

TECHCON showcases academia’s brightest

TECHCON brings together the brightest minds in microelectronics research to exchange news about the progress of research ranging from materials to architectures created by SRC’s network of more than 100 of the top engineering universities. Students and industry leaders discuss basic research that is intended to accelerate advancements for both private and public entities.

The presentation of the Aristotle and Technical Excellence awards reflects the purpose of TECHCON, which is to enable future generations of chip technology. The Aristotle Award is given to SRC-funded university faculty that have profoundly and continuously impacted their students’ professional performances in a way that provides long-term benefit to the SRC member companies. The Technical Excellence Awards recognize researchers who have made key contributions to technologies that significantly enhance the productivity of the semiconductor industry.

More than 12,000 students have been prepared by SRC programs, professors and mentors for entry into the semiconductor business. These students provide a path for technology transfer and a source of relevantly educated technical talent for the industry.

Lomonosov MSU physicists found a way to “force” silicon nanoparticles to glow in response to radiation strongly enough to replace expensive semiconductors used in display business. According to Maxim Shcherbakov, researcher at the Department of Quantum Electronics of the Moscow State University and one of the authors of the study, the developed method considerably enhances the efficiency of nanoparticle photoluminescence.

The key term in the problem is photoluminescence — the process, when materials irradiated by visible or ultraviolet radiation start to respond with their own light, but in a different spectral range. In the study, the material glows red.

In some of the modern displays, semiconductor nanoparticles, or the so-called quantum dots, are used. In quantum dots, electrons behave completely unlike those in the bulk semiconductor, and it has long been known that quantum dots possess excellent luminescent properties. Today, for the purposes of quantum-dot based displays various semiconductors are used, i.e. CdSe, etc. These materials are toxic and expensive, and, therefore, researchers have long been scrutinizing the far cheaper and much more studied silicon. It is also suitable for such use in all respects except one — silicon nanoparticles vaguely respond to radiation, which is not appealing for optoelectronic industry.

Scientists all over the world were seeking to solve this problem since the beginning of the 1990’s, but until now no significant success has been achieved in this direction. The breakthrough idea about how to “tame” silicon originated in Sweden, at the Royal Institute of Technology, Kista. A post-doctoral researcher Sergey Dyakov (a graduate of the MSU Faculty of Physics and the first author of the paper) suggested placing an array of silicon nanoparticles in a matrix with a non-homogeneous dielectric medium and cover it with golden nanostripes.

‘The heterogeneity of the environment, as has been previously shown in other experiments, allows to increase the photoluminescence of silicon by several orders of magnitude due to the so-called quantum confinement,’ says Maxim Shcherbakov. ‘However, the efficiency of the light interaction with nanocrystals still remains insufficient. It has been proposed to enhance the efficiency by using plasmons (quasiparticle appearing from fluctuations of the electron gas in metals — ed). Plasmon lattice formed by golden nanostripes allow to “hold” light on the nanoscale, and allow a more effective interaction with nanoparticles located nearby, bringing its luminescence to an increase.’

The MSU experiments with samples of “gold-plated” matrix with silicon nanoparticles made in Sweden brilliantly confirmed the theoretical predictions – the UV irradiated silicon for the first time shone bright enough to be used it in practice.

The first author of the paper Sergey Dyakov will present the findings on The 10th International Congress on Advanced Electromagnetic Materials in Microwaves and Optics (September 17-22, Crete). The work was also published in the Physical Review B (“Optical properties of silicon nanocrystals covered by periodic array of gold nanowires”).

Qualcomm Incorporated (NASDAQ:  QCOM) today announced the opening of Qualcomm Communication Technologies (Shanghai) Co. Ltd., a semiconductor test facility in the Waigaoqiao (WGQ) free-trade zone in Shanghai, and its first foray into providing manufacturing services for semiconductors. By working with Amkor Technology, Inc., one of the world’s leading providers of contract semiconductor assembly and test services, the new company will combine Amkor’s extensive test services experience and cleanroom facilities with Qualcomm Technologies’ industry leadership in cutting-edge product engineering and development.

The new manufacturing facility demonstrates Qualcomm Technologies’ commitment to continue to invest and help develop semiconductor expertise in China, and is indicative of growth in semiconductor market leadership in the country. Through the ownership and operation of a semiconductor test center, Qualcomm Technologies will enhance its focus on customer service, continue to develop its expertise in operational excellence, and increase its business presence in China.

“The test facility is part of our continued mission to streamline supply chain operations and improve operational efficiency,” said Roawen Chen, senior vice president, QCT global operations, Qualcomm Technologies, Inc.

“Qualcomm Technologies continually strives to improve our manufacturing footprint in China and the formation of Qualcomm Communication Technologies in Shanghai is another example of this dedication,” said Frank Meng, chairman, Qualcomm China.

“We are excited to work with Qualcomm Technologies in their new test operation in China,” said Steve Kelley, Amkor’s president and chief executive officer. “Amkor offers the most advanced outsourced assembly and test technologies in China, and this expanded relationship is a natural extension of the long history of close collaboration between our two companies.”

The Shanghai-based facility is set to begin operations on October 18, 2016.

An overview of liquid-to-liquid cooling systems and their operating principles

BY MARKO NIEMANN, Regional Sales Director, Laird Engineered Thermal Systems, Cologne, Germany

Cooling and temperature control systems are used throughout semiconductor fabrication facilities. In fabrication facilities both large and small, hundreds to thousands of cooling systems are installed and operate continuously. The processes employed are usually setup as copy-exact, which means the process systems are developed and transferred from the OEM of the process tool. These crtitical production tools used in a semiconductor fabrication facilities are required to be reliable and easy to service to deliver minimum downtime. The same is required of the cooling systems that support them. Usually the cooling systems employed have a water- cooled evaporator instead of an air-cooled evaporator. A liquid-liquid unit is quieter than a liquid to air unit because a fan is not required. Even more important, the heat can be rejected by available general facility cooling water and the heat is not rejected into the air temperature conditioned environment. These cooling systems can be placed near the tool, hidden in a false floor or on the lower level in a sub-floor. Cooling systems are built to meet SEMI S2 or F47 standards. OEM customers vary in their demand according to their unique requirements, but compliance is mandatory and sometimes OEM customers ask to get certifications for SEMI S2 or F47, which includes for example seismic “protections.” In these fabrication facilities a variety of liquid cooling systems are used including: compressor and thermoelectric based recirculating chillers.

Cooling systems

Liquid cooling systems are required to:

  • Protect the tool process against chemical reaction by avoiding an unknown Wetted-Parts-Material-Mix
  • Achieve a stable temperature, independent from facility water temperatures that can change
  • Achieve a temperature below or above the facility water temperature
  • Solve different temperature or fluid requirements at one tool with a multi-loop liquid cooling system

In semiconductor fabrication facilities, the required temperature control range varies from -80°C to +150°C. For the majority of applications, only one stable temperature set point is required. In the final chip test environment however, temperatures are required to vary in order to stress the chip. Here different temperature set points need to be reached with a single thermal management system. Due to the high-precision processes, tool manufacturers demand a very stable temperature environment. Typical of these requirements are +/-0.1K stability (e.g. for etching) to ±0.001K (e.g. for lithography) while cooling capacities can be up to several kilowatts.

In semiconductor fabrication facilities, custom multi- stage compressor based chillers are used to support cooling for very low temperature requirements. Most standard chillers utilized need some form of modification to meet semiconductor process facility requirements and may even require a water-cooled condenser. Some of the installation base also uses thermoelectric (19” rack) cooling systems, i.e. for etch applications, instead of compressor-based systems.

The cooling capacity demands and the range over which the system operates varies from a couple of hundred Watts (thermoelectric chiller and compressor based systems) to hundreds of Kilowatts (liquid-to-liquid cooling systems). The majority of the installed base uses liquid-to-liquid cooling systems that operate close to ambient and are based on a fluid-to-fluid heat-exchange principle.

The cooling systems utilize facility water to prevent heat dissipation of the cooling unit from warming the cleanroom and destabilizing the process tool’s thermal management system. These liquid-to-liquid systems keep the air quality level high by avoiding dust up introduced from the airflow of an air-to-air thermal management system. This consideration is independent of the location of the thermal management system. Due to the cyclic nature of the market, product requirements change and time to market is crucial. The cooling system solution developed is usually a custom product with a unique approach and design specific to the OEM.

Technical requirements

Cooling systems are often placed in the sub-fab, which means they are located one or two floors below the tool they are connected to. For cooling systems that use water as coolant, the height between the tool and the cooling system cannot exceed 10 meters, otherwise the height difference can cause the water to boil as the pressure is lower than the vapor pressure of water.
If the cooling system is placed at a lower level, the coolant circuit can function as a closed loop to the atmosphere. In this case, the cooling unit needs to incorporate a closed pressurized reservoir (7 PSI pressure cap) to minimize over flow conditions. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap (FIGURE 1).

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

A standpipe reservoir introduces additional fluid to the liquid circuit as required, whereas a flow-through reservoir continuously exchange fluid. It is important to know that the pump simply needs to overcome the height and pressure difference one-time during start-up in a closed loop system, as the supply and return lines will equilibrate given that they have the same length and diameter.

Material compatibility

In the semiconductor process environment, copper and brass are materials with limited compatibility due to their susceptibility to galvanic corrosion. Wetted parts, which come in direct contact with the medium (liquid), are typically made of stainless steel. These parts range from the complete plumbing circuit of the cooling unit to the process loop. Stainless steel is usually used in the process loop due its resistance to galvanic corrosion or because a special fluid is used that is not compatible with PVC, copper, and brass etc. When stainless steel is required, the heat exchanger, valves and the pumps will require special consideration. Occasionally, stainless steel may require additional passivation or a limited subset of stainless steel materials may be used.

If copper or brass is used to accomodate cost considerations, the material needs to be insulated to minimize the thermal impact on the system from outside thermal sources. Special particle free insulation may be required in this instance.

Special fluids used in the semiconductor environment include: di-electric fluids (Galden, 3M Novec), which are non-conductive. Special hoses and sealings need to be used for these fluids and special attention to handling is also required. These coolants run in a closed loop as the fluid vapor pressure is relatively low compared to water.

The use of de-ionized water is common. Copper or brass can be run up to 3 MOhm-cm resistivity if the set point temperature does not exceed 30°C for extended periods of time. However to ensure long lifetimes and for higher resistivity demands, the cooling system should be equipped with a nickel brazed or complete passivated stainless steel evaporator/heat-exchanger. The pumps should be stainless steel and all component parts in contact with the fluid should be made of passivated stainless steel to prevent corrosion. This is referred to as high-purity plumbing. In addition, a DI cartridge can be equipped with an indicator light or regulated through the cooling system and the DI level will be constantly measured and monitored keeping to a preset resistivity. The DI cartridge filters the ions out of the fluid and needs to be replaced to ensure its effectiveness.

Valves

If the unit is placed below the fabrication floor, an anti- siphoning package can be used to avoid backflow of the fluid and prevent overflowing the unit in event the pump stops. The anti-siphoning package consists of a one-way check valve in the supply line and normally open solenoid valves triggered by the unit in the return line. The solenoid valve would close in case the pump stops and the one-way check valve allows for the flow in only one direction. Instead of a one-way check valve, another solenoid valve can be used, though this depends on the flow rate and size (FIGURE 2).

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

For a process facility, constant monitoring and control of the facility process water is required and modulating solenoid valves from Siemens or Bellimo need to be used. The valve diameter and actuating motor have to be sized correctly to achieve stable temperatures and trigger the correct switching cycles. Assuring this means the inclusion of a long- lasting actuator and facility water flowing through an acceptable pressure drop from the facility water supply and return. Sometimes three-way mixing valves are used. This allows for continuous flow into the facility water loop and adds cooling for the heat exchanger of the thermal management system when required. The constant flow back to the facility water loop avoids a water hammer in cases where it would close and reopen when cooling is required. Flow requirements can go be as high as hundreds of liters per minute.

Space consideration

Cleanroom costs can be up to $60,000 /m2, therefore the chiller footprint is important and can have a costly impact. Semiconductor cooling systems should be stackable (stacked high) and preferable narrow to maximize space and minimize their impact on costs. Therefore the design of a cooling system’s footprint needs to be closely examined. The system should also be located where it is easy to access from two sides. Routine maintenance on cooling systems is required to exchange components such as pumps, motors, valves and fans to maximize system uptime.

SEMI requirements

For a completed tool, OEMs require a SEMI S2 certification and sometimes a Semi F-47 certification in areas with high earthquake probability. As the SEMI S2 certification requires a high amount of documentation, subsystems like a cooling unit will finally be integrated into the tool. Most of the time it is sufficient to meet the intent of SEMI S2 and the OEM will do a full certification of the final tool with all sincorporated subsystems in their NRTL laboratory. Below are some items to consider when designing a cooling unit to meet SEMI S2 and F-47 standards.

SEMI S2:

  • Drip tray must be large enough to hold 110% of the volume of the largest container in the cooling product
  • EMO button and/or EMO connection
  • Seismic brackets, seismic tie downs for standalone units
  • A specific power connection setup depending on the power consumption

F-47:

  • Continue to run during a power drop for a given time and fixed reduction of power

These requirements vary from customer to customer, but to some extent the certification is known to the manufacturer of the system.

If the unit is not placed below the fabrication facility flooring, the cooling system will instead be placed in the cleanroom or a grey room. Again, requirements here can vary drastically from customer to customer. If the cooling system, sub-assembly or any component is required to be in the cleanroom, then the entire assembly including each component must be as clean as possible. This requires the entire manufacturing process to have a high level of attention to cleanliness. Debris, dust, burrs or chips occurring at every process step need to be examined and removed ideally after every fabrication step. The industry is quite sensitive to this.

After the final assembly, the cooling unit needs to go through a manual check with UV-light and wipe down for final cleaning with gloves. The unit is then double bagged and each bag needs to be labeled appropriately. There are suppliers who specialize in cleaning, to semicon- ductor standards, and this can be subcontracted. Since it contributes to the cost and lead-time, the level of detail used requires scrutiny.

Service

Selling a cooling unit into the semiconductor market requires long-term servicing agreements in the contract. If a product is qualified in one facility other facilities can take over the setup as a copy exact requirement and use the existing cooling solution. For this after-market service and support, full understanding of the end users demands is critical. Service and support needs to responsive. In the event a tool unexpectedly goes down, immediate support is required or the OEM can lose millions of dollars in revenue.

Once the tool is installed service needs to be done on-site on the same day of failure, as large cooling systems cannot be replaced easily or shipped back to manufacturer for repair. OEMs have moved away from purchasing redundant cooling systems as their processes are getting leaner and expenses are reviewed more closely. This puts the contractual emphasis on service and a global service infrastructure.

Ideally the manufacturer is aware of the service demands and support strategy of their customers. Systems today are designed to minimize the downtime and make use of hot swappable parts, such as pumps on rails or modular exchange of complete assemblies, including electrical control boxes.

Conclusion

A semiconductor fabrication facility’s unique environment makes designing and building a liquid based cooling system one of the most challenging environments. Careful consideration is required not only for component selection, but also on the overall liquid cooling system unit and its integration with a semiconductor tool. Challenges designers face include the type of heat transfer mechanism utilized on the control and heat dissipation sides, material compat- ibility, valve control, cleanliness, space optimization, semi compliance and serviceability. These are all areas in need of attention to detail to properly ensure an optimized total cost of ownership.

The global high-tech engineering and construction company M+W Group has presented current and future trends, as well as state of the art solutions, for an integrated approach to waste reduction in order to improve the sustainability of semiconductor fabs. The presentation was held at the High-Tech Facility International Forum 2016 in Taipei on 8th September in conjunction with the Semicon Taiwan trade show.

Having successfully contributed to the forum’s widely recognized meetings over the past two years M+W Group was also invited to this year’s expert meeting on high- tech facilities. There, M+W Group leading experts presented the company’s solutions for an Integrated Waste Reduction Program for Semiconductor Facilities. It was emphasized that minimization of waste produced in semiconductor wafer fabs and other high-tech facilities begins during the buildings’ design and must focus on both the construction as well as the operational phases.

Drawing on its globally recognized experience, M+W Group outlined how sustainability in a semiconductor wafer fab can best be evaluated, monitored and optimized through the application of a holistic Life Cycle Assessment (LCA) tool that provides systematic evaluation of all environmental aspects of a wafer fab during their construction, operational lifetime and decommissioning.
Herbert Blaschitz, CEO of M+W Group’s Global Business Unit Advanced Technology Facilities, said “There is an ever-increasing interest in the industry to implement fully sustainable semiconductor wafer fab solutions. We at M+W Group have broad and successful experience in this field and are proud to be at the forefront of this development.”

About the High-Tech Facility International Forum: As part of SEMICON Taiwan the High- Tech Facility International Forum 2016 focuses on cost-efficient waste reduction for sustainable facilities. The forum builds a platform for major players in the high tech facility community to discuss latest trends, challenges and outstanding solutions for the Taiwanese high-tech industry. Other members besides M+W Group include TSMC, UMC (wafer fab foundries for Integrated Circuits (IC)), Macronix, Inotera (IC memory manufacturers), AUO, Chimei Innolux (flat panel display manufacturers), ASE, SPIL (IC assembly), Epistar (LED Manufacturer) and Motech (PV module manufacturer).

Lam Research Corp. (Nasdaq: LRCX), an advanced manufacturer of semiconductor equipment, today announced that it is expanding its atomic layer etching (ALE) portfolio with the addition of ALE capability on its Flex dielectric etch systems. Enabled by Lam’s Advanced Mixed Mode Pulsing (AMMP) technology, the new ALE process has demonstrated the atomic-level control needed to address key challenges in scaling logic devices to 10nm and below. First in the industry to use plasma-enhanced ALE in production for dielectric films, the latest Flex system has been adopted as tool of record for high-volume manufacturing of logic devices.

“From transistor and contact creation to interconnect patterning, a new level of precision is needed by logic manufacturers to continue scaling beyond the 10nm technology node,” said Vahid Vahedi, group vice president, Etch Product Group. “For device-enabling applications like self-aligned contacts, where etch helps create critical structures, conventional technologies do not provide sufficient control for the stringent specifications now demanded. Our latest Flex product with dielectric ALE delivers atomic-scale control with proven productivity to meet customers’ key requirements.”

To continue logic device scaling, chipmakers are adopting new integration schemes such as those using self-aligned contacts (SACs) in order to address issues like RC delay. As a result, contact etch has become one of the most crucial processes, directly impacting both wafer yield and transistor performance. In order to define critical device structures with high fidelity, the etch process requires directional (anisotropic) capability with ultra-high selectivity, while also delivering the productivity needed for manufacturing.

For next-generation logic and foundry applications, Lam’s Flex dielectric etch systems offer the industry’s most advanced capacitively coupled plasma (CCP) reactor, featuring a unique, small-volume design to deliver repeatable results. The latest system uses proprietary AMMP technology to enable ALE of dielectric films such as silicon dioxide (SiO2). This capability results in a 2x improvement in selectivity over previous dielectric etch technologies while delivering atomic-level control.

SPTS Technologies, an Orbotech company and a supplier of advanced wafer-processing solutions for the global semiconductor and related industries, today announced its collaboration with Novati Technologies, a global nanotechnology development center, to establish Novati’s new plasma dicing line at their fab in Austin, Texas. Novati has selected SPTS’s Rapier-300S plasma dicing solution over competing options to provide next-generation plasma dicing capabilities and services for customers.

“Plasma dicing has many advantages over conventional singulation methods and offers designers and manufacturers greater flexibility with regards to die shape, size and position,” stated Kevin Crofton, President of SPTS Technologies and Corporate Vice President at Orbotech. “The Rapier-300S is the latest addition to our Mosaic™ plasma dicing platform which includes wafer handling solutions for 150mm, 200mm and 300mm wafers, both full thickness and taped to dicing frames. Novati selected the Rapier-300S to provide their customers with the latest dicing technology to complement their advanced semiconductor fabrication solutions and services.”

“Novati provides customers with technology building blocks, engineering expertise, professional program management and a broad complement of flexible processing equipment that enable the accelerated development of 200mm and 300mm production-worthy solutions,” stated John Behnke, President of Novati Technologies. “In order to remain at the forefront of novel process development, we must provide our foundry customers with the latest process solutions capable of manufacturing next generation devices.”

SPTS’s Mosaic plasma dicing system with the Rapier-300S overcomes many of the design limitations of conventional dicing methods, particularly for smaller, thinner, more fragile die, as well as offering the potential for significant increases in yield and throughput. By leveraging SPTS’s extensive expertise and experience in deep silicon etch which serves as the basis of Rapier-300S plasma dicing technology, customers are able to support the development of innovative More-than-Moore solutions.

To learn more about SPTS’s Rapier-300S and Mosaic plasma dicing platform and the benefits of Plasma Dicing for Next Generation Ultra Small and Ultra Thin Die, register now for a free webinar on Wed 14th Sept, 2016, with presentations from Amandine Pizzagalli, Analyst at Yole Developpment, and Richard Barnett from SPTS Technologies.

SEMI today presented its industry leadership award for sustainable manufacturing to Po Wen Yen, CEO of United Microelectronics Corporation (UMC). Yen received theSEMI Sustainable Manufacturing Leadership Award – Inspired by Akira Inoue, at the Leadership Gala Dinner at SEMICON Taiwan 2016, the largest annual electronics manufacturing industry event in Taiwan.

“Yen exemplifies outstanding leadership and commitment to sustainable manufacturing issues. He approaches environmental protection in a holistic way, thinking broadly and then setting up the infrastructure to institutionalize the change while staying involved each step of the way,” said Denny McGuirk, president and CEO of SEMI. “This SEMI award for significant sustainable manufacturing achievement recognizes his status among a distinguished group of electronics industry executives.”

As CEO of UMC, Yen drove UMC to become a global leader in sustainable semiconductor manufacturing, emphasizing to his staff, customers, and suppliers, that “sustainable development is not only UMC’s vision but is also our core philosophy.” Yen also created a corporate structure where all sustainability-related goals and activities are overseen by a committee that he chairs, and then he reports these developments directly to the UMC Board of Directors.  Yen’s commitment has led to significant positive impacts on sustainable manufacturing at UMC. Yen’s specific accomplishments noted by the SEMI Award committee include:

Environmental Protection

  • Global Warming –To reduce energy use at UMC, Yen created and chairs an Energy Saving Committee, which reduced electrical power usage by 29,469 Mwh in 2014, which is the equivalent of removing 15,353 tons of CO2 from the atmosphere, and reduced natural gas usage by 11,979 Mwh, the equivalent to reducing 2,159 tons of CO2 emissions from being released into the atmosphere.
  • Water Resources – UMC maximizes water efficiency and promotes the importance of water resources and conservation. Total water recovery and reuse reached more than 180 percent of water intake for the calendar year 2015.
  • Green Manufacturing – UMC innovated corporate programs to manage hazardous substances and reduce pollution and waste during semiconductor manufacturing. UMC has a robust Hazardous Substance Process Management (HSPM) system in place that is certified by the International Electro-Technical Commission Quality Assessment System.
  • Green Buildings – UMC’s Fab 12A in the Tainan Science Park obtained both Taiwan’s Gold Certification for Green Buildings and LEED Gold Certification.
  • Green Products –To better evaluate the environmental impacts of products, UMC collaborated with the Industrial Technology Research Institute (ITRI) to implement a Life Cycle Assessment for each fab, improving its management processes and reducing resource consumption.


Community Service

  • Social Welfare – UMC encourages a culture of community volunteering with many programs. One example, “Spreading the Seeds of Hope,” has assisted over 6,000 children from disadvantaged families.
  • UMC Fire Brigade – Still the only corporation in Taiwan’s electronics industry to have its own fire department, UMC established its high-tech fire brigade more than 20 years ago. The fire brigade consists of 106 members, including 13 full-time employees and 93 voluntary firefighters.

The Sustainable Manufacturing Leadership Awardis sponsored by SEMI. The award is named after the late Akira Inoue, past president of Tokyo Electron Limited and a strong advocate of sustainable manufacturing in the semiconductor industry. Inoue also served on the SEMI Board of Directors. The award recognizes individuals in industry who have made significant leadership contributions to reduce the environmental and social impacts of semiconductor manufacturing. Past Award recipients include: Mark Durcan (CEO, Micron), TY Chiu (CEO, SMIC), Ajit Manocha (CEO, GLOBALFOUNDRIES), and Morris Chang (CEO, TSMC).

SEMICON Taiwan will be held from September 7 to 9 at Taipei Nangang Exhibition Center, Hall 1. Upbeat about the growth prospects of Taiwan’s semiconductor sector, SEMICON Taiwan 2016 features 600 exhibitors covering over 1,600 booths,and is expected to attract more than 43,000 visitors in three days.

For the sixth consecutive year, Taiwan has been the largest consumer of semiconductor equipment due to its large foundry and advanced packaging capacity, totaling $9 billion in 2016 and expecting to grow to $10 billion in 2017, accounting for a quarter of the global market. According to the latest report from IEK, the total production value of Taiwan semiconductor industry is expected to reach $2.4 trillion, performing better than the global market with a growth rate of 7.2 percent.

SEMICON Taiwan 2016 adds new pavilions including Okinawa (Japan), Philippines, Singapore, and World of IoT, in addition to pavilions on Cross-Strait, Kyushu (Japan), German, Holland High Tech and Korea, plus theme pavilions of AOI, CMP, High-Tech Facility, Materials, Precision Machinery, Secondary Market, Smart Manufacturing and Taiwan Localization. The total of nine theme pavilions and the eight country/region pavilions will offer visitors the most up-to-date options of greatest diversity.

The ascending trends of the Internet of Things and the need for smaller and more powerful mobile devices and wearables have created limitless new opportunities for semiconductor industry. In response to these trends, SEMICON Taiwan 2016 features the World of IoT pavilion showing off the latest application products, but also includes 21 forums, inviting speakers from the industry and academia, including TSMC, UMC, ASE, SPIL, Amkor, Lam Research, TEL and more, to share their exclusive perspectives on topics including memory, advanced packaging, semiconductor materials, high-tech facility, IC design, MEMS, 2.5D/3D IC technology, embedded and wafer level technology, and sustainable supply chain management. The three-day program is expected to attract over 4,000 attendances, providing an ideal platform for information exchange.

Covering the hottest topics like smart manufacturing, high-tech facility, and materials, more than 50 presentations will be given on TechXPOT stages, providing not only the latest technology updates but also great opportunities to meet potential partners.  To connect the right people and facilitate collaboration, SEMICON Taiwan organizes a series of networking events, like the Materials, High-Tech Facility, and Smart Manufacturing Get Togethers and the Supplier Search Program, creating business opportunities.

Diverse show activities and services include:

  • Live Broadcasting: HD live streaming provides first-hand highlights of forums and events from each corner on big screen and Facebook.
  • SEMICON Taiwan App: Providing the most updated exhibition information along with personal assistance functions, the SEMICON Taiwan App allows a smarter and more convenient visiting experience.
  • Jing Jing Lucky Draw: One of the most anticipated show activities will give away Ninebot One E+, Kodak Pixpro SP360, HTC Vive, Irobot Roomba, and new-years-eve hotel coupon.

Terry Tsao, SEMI Taiwan president states, “For years, SEMICON Taiwan not only has successfully connected Taiwan with the global markets, but also has bridged healthy communication between the government and the industry. Through increasing diversity, we expect to see SEMICON Taiwan continue to play an important role in facilitating collaboration and integration, helping the Taiwan semiconductor industry remain in a leading position.”

For more information, visit www.semicontaiwan.org/en

ZEISS introduces the new ZEISS ForTune system for photomask tuning. With its latest optical design, it takes two main mask tuning processes to the next level in terms of efficiency, accuracy and throughput. The first tool has already been delivered to the first customer.

The new ZEISS ForTune mask tuning system combines the capabilities from ZEISS CDC and RegC in a new advanced system. This means mask registration and Critical Dimension Uniformity (CDU) can be completed in one process. It helps to:

  1. Expand the Lithography Process Window and reduce the wafer intrafield hot spots (using the CDC technology)
  2. Improve wafer intra-field On-Product Overlay and enhance Mask Image Placement (using the RegC technology)

ZEISS ForTune is a technology with advanced system and optics design, allowing for high process efficiency and prediction accuracy, as well as for significantly improved output.

The mask tuning system has been first introduced to Wafer Fab customers at the SEMICON West in San Francisco, USA in July 2016.

“In order to produce IC devices at sub-16nm design nodes, semiconductor manufacturers are integrating many novel technologies, including multiple patterning, spacer pitch splitting, 3D logic and memory structures, new materials and complex reticles. Using these new technologies requires tight specifications for On-Product Overlay, Mask Registration, and Lithography Process Window. ForTune is a powerful new technology that enables Mask Makers and Wafer Fabs to tackle these challenges in a fast and cost-effective way,” states Ofir Sharoni, Product Manager of ZEISS ForTune in Karmiel, Israel. Another presentation of the new system will take place at the SPIE Photomask Conference in September 2016 in San Jose, USA.

Besides the official product launch, the next generation Wafer and Mask Tuning System has already been successfully delivered to an US based chip manufacturer, who ordered the new ZEISS ForTune system earlier this year.