Category Archives: Wafer Processing

Driven by rising demand for thinner wafers and stronger die, dicing technology is evolving.

“Reaching more than US$100 million in 2015, the dicing equipment market will double by 2020-2021,” announced Yole Développement (Yole) (Source: Thin Wafer Processing & Dicing Equipment Market report, Yole Développement, May 2016). Yet at the same time thin wafers are creating new challenges of significant interest in the dicing equipment industry such as die breakage, chipping, low die strength, handling issues and dicing damage.

Yole’s Technology & Market Analyst, Amandine Pizzagalli, is pleased to give her vision of the dicing technologies, market forecast and competitive landscape during the webcast “Plasma Dicing for Next Generation Ultra Small and Ultra Thin Die” organized by SPTS Technologies, an Orbotech company. This webcast will take place on September 14. To register click PLASMA DICING.

Today, the most common dicing technology applied across memory, logic, MEMS, RFID and power devices is mechanical dicing, also known as blade dicing. 

“Blade dicing represents more than 80% of the dicing brand equipment business in terms of dicing tools and stealth dicing 20%,” explained Amandine Pizzagalli from Yole.

However, companies are showing a growing need for thinner wafers and smaller devices in general and Yole sees a trend towards adopting alternative dicing technologies. These include stealth dicing and plasma dicing based on deep reactive ion etching technology. Yole’s analysts details the plasma dicing market per application:

  • Memory specifically has predominantly relied on a combination of blade and laser dicing applied together to singulate complex stacks. Using only blade dicing on top layers leads to delamination issues because of the high metal density. However, it’s difficult to safely singulate 50 µm thin wafers even with laser dicing and this could allow plasma dicing to enter this area. “Even if the philosophy of the designers is changing, memories manufacturers are still the most conservative”, details Amandine from Yole.
  • In MEMS devices blade dicing is largely applied for singulating the ASIC, capping and MEMS sensors. However, exposure to water from the process can contaminate some sensors and destroy sensitive MEMS structures, example in MEMS microphones. In such cases, stealth dicing has been already adopted in large volume production. Plasma dicing has also been adopted in low volume production today for MEMS devices.
  • In parallel, the RFID is a growing market segment: plasma dicing is already in production but the adoption rate is still small. According to Yole’s analysts, a fast growth for plasma dicing especially for RFID devices is expected. Indeed plasma dicing has the ability to reduce die fragility, boost die strength, increase the number of chips per wafer and thus reduce Cost Of Ownership of equipment overall.

“As die sizes continue to shrink, singulation by plasma etching offers considerable benefits for die quality and strength as compared to traditional dicing solutions,” stated Richard Barnett, Etch Product Manager at SPTS Technologies, an Orbotech company. And he adds: “Ultra-small and ultra-thin devices like RFID chips or fragile devices like MEMS are more susceptible to damage from the vibration and chipping caused by mechanical saws, or from the heat caused by lasers.”

Under its new thin wafer & dicing equipment market report, the “More than Moore” market research and strategy consulting company is analyzing the competitive landscape: the current market is today controlled by DISCO and Accretech, which today claim market shares of almost 80% focused on blade dicing and stealth dicing, respectively:

  • DISCO leads the blade dicing market and offers a large product portfolio including stealth dicing and laser ablation. They have also a partnership with Plasma-Therm which gives them access to the complete range of dicing technologies: Yole’s analysts had the opportunity to discuss the market, its evolution and challenges with Abdul Lateef, CEO, and Thierry Lazerand, Business Development Director, of Plasma-Therm. To discover this interview, click Plasma-Therm solution.
  • Accretech leads the stealth dicing market offering.
  • ASM Pacific is a strong player in laser ablation, especially because their process does not lead to contamination issues compared to standard laser ablation technology.

During SPTS Technologies webcast, Amandine Pizzagalli will describe the today’s competitive landscape of the key dicing technologies across MEMS devices, power devices, CMOS image sensors, and RFID devices, highlighting her major findings on the evolution and trends of the dicing technologies.

These results are part of Yole’s report entitled Thin Wafer Processing & Dicing Equipment Market. Under this analysis, Yole presents a comprehensive overview of the key dicing technologies benchmarks in terms of feature requirements. This report includes insights into the number of tools, broken down by wafer size, by application and by dicing technology… A full description of the report is available on i-micronews.com, manufacturing reports section.

In parallel, SPTS Technologies speaker, Richard Barnett also proposes an overview of the latest advances in plasma dicing. During his talk, Richard will highlight the latest data illustrating how processing routes affect die strength, share experiences with different types of tapes and other die features such as solder balls. SPTS Technologies will share details of the latest equipment which is now available for plasma dicing wafers up to 300mm (on 400mm tape frames) for full production applications.

Cabot Microelectronics Corporation (Nasdaq: CCMP), a supplier of chemical mechanical planarization (CMP) polishing slurries and a growing CMP pad supplier to the semiconductor industry, announced the appointment of Thomas F. Kelly, Vice President, Corporate Development, which is effective as of September 6, 2016. Mr. Kelly rejoins Cabot Microelectronics after serving as the Director of Global Raw Materials Procurement for Celanese Corporation from 2012 through 2016, and prior to that as the Vice President of New Business Development and the Program Management Organization of Chemtura Corporation, where he was employed from 2008 until 2012. He was employed by Cabot Microelectronics from 1999 through 2008, serving in various senior business operations, product management, and supply chain assurance roles.

“I am delighted to welcome Tom Kelly back to Cabot Microelectronics, and am confident his executive expertise from various global companies in the larger engineered materials and chemicals industries will benefit our company greatly in a number of important areas,” said David H. Li, Cabot Microelectronics’ President and Chief Executive Officer. “Tom knows our business, industry, customers and supply chain well, along with having developed important experience in mergers and acquisitions, business development, and corporate strategy from his more recent roles in helping to lead multi-billion dollar global businesses.”

In addition to this, the Company announced that as of September 1, 2016, Daniel J. Pike has resigned from his position as Vice President, Corporate Development, and will continue to serve the Company in a non-executive transition role until March 1, 2017. Mr. Li stated, “I would like to thank Dan for his significant contribution to the founding and growth of Cabot Microelectronics during his many years of service. All of us wish him well in his future endeavors.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced more than a dozen semiconductor industry icons, leaders, and founders will come together at the annual SIA Award Dinner on Thursday, Nov. 10 in San Jose to celebrate the 25th anniversary of the Robert N. Noyce Award, the industry’s highest honor. Former Noyce Award recipients who will attend the event include Dr. Craig Barrett, Dr. Morris Chang, John Daane, Federico Faggin, Ted Hoff, Dr. John E. Kelly III, Stanley Mazor, Jim Morgan, Jerry Sanders, George Scalise, Mike Splinter, Ray Stata, Rich Templeton, and Pat Weber. The evening’s program will include a conversation with former Noyce recipients about the industry’s storied past and its tremendous promise for the future.

SIA previously announced Martin van den Brink, president and chief technology officer at ASML Holding and renowned pioneer in semiconductor manufacturing technology, will receive the 2016 Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the semiconductor industry in technology or public policy.

“Recipients of the Noyce Award represent the finest our industry has to offer, individuals who have shaped the trajectory of semiconductor technology and spurred groundbreaking innovations,” said John Neuffer, president and CEO, Semiconductor Industry Association. “This year we are privileged to present the 2016 Noyce Award to Martin van den Brink, a man whose career accomplishments have fundamentally transformed semiconductor manufacturing, and to do so with many former Noyce winners on hand. We look forward to this unique opportunity to celebrate the semiconductor industry alongside these legends in our industry and true trailblazers of modern technology.”

For information about the SIA Award Dinner, including tickets and sponsorship opportunities, please visit www.semiconductors.org.

By Paul Trio, SEMI

Growing Demands, Constraints Continue

For many years, the ATE industry has been challenged with controlling the cost of both production and development test by implementing innovative approaches and employing clever strategies (e.g., multi-site test implementation, DFT, etc.) to make “ends” meet, so to speak.  This predicament has been a perpetual struggle, but the industry manages to soldier on. However, the demands for next-generation technology continues to introduce new challenges to the ATE realm. For example, shorter production ramp-up and higher yields result in the increasing demand for test data and information in real-time. Not only is there a need for more data quickly, but also for better test data quality. Adding to the complexity is that existing formats are typically slow/limited or even proprietary. As a result, the equipment manufacturers are burdened with supporting multiple proprietary data transport and communications systems.  This requires the use of valuable engineering resources to develop and maintain these multiple proprietary systems, whereas a single standard system would open up resources to develop new ATE features and products.

ATE Industry Alliance

These ATE industry problems are being addressed by CAST – Collaborative Alliance for Semiconductor Test – a SEMI Special Interest Group (SIG). SEMI SIGs provide a forum that fosters discussion and aligns stakeholders on industry-critical issues. CAST was formed in 2008 by semiconductor device makers and test industry suppliers to engage in and resolve common industry issues related to higher test equipment utilization, lower costs, and greater return on investment. In 2009, CAST became a SEMI Special Interest Group. Its charter includes fostering pre-competitive collaboration as well as developing and promoting standards that enable industry productivity improvements.

Figure 1 CAST Industry Stakeholders

Figure 1 CAST Industry Stakeholders

CAST members include a range of semiconductor industry leaders, ranging from automated test equipment (ATE) companies to integrated device manufacturers (IDMs) to fabless manufacturers to outsourced semiconductor assembly and test (OSAT) companies. Companies participating in CAST include: Advantest, ASE, Galaxy Semiconductor, GLOBALFOUNDRIES, Infineon, Maxim, Nvidia, Optimal+, PDF Solutions, Qualcomm, Roos Instruments, STMicroelectronics, Teradyne, Tesec, Texas Instruments, Xcerra.

CAST Structure

The CAST organization is primarily comprised of a steering committee and two working groups. The CAST Steering Committee meets quarterly to review progress on programs and identify new solutions needed by the industry. The Steering Committee is comprised of decision-makers and strategic thinkers of the participating companies mentioned above.

The current CAST working groups that are addressing data transport and control are the Rich Interactive Test Database (RITdb) WG and the Tester Event Messaging for Semiconductor (TEMS) WG.

Figure 2 SEMI CAST Working Group Focus Areas

Figure 2 SEMI CAST Working Group Focus Areas

Enabling Adaptive Test through Next Generation Standard Test Data Format

While Standard Test Data Format (STDF) is widely used in the semiconductor industry today, its current specification does not directly support the new use models in today’s test environment, such as real time or pseudo real time queries, adaptive test and streaming access. The STDF V4 record format is not extendible and the specification itself can be imprecise, such that it tends to result in many interpretations. These limitations become apparent when there is a need for more efficient and flexible format to manage “big test data.”

The RITdb group has been working on the next generation format following STDF with more flexibility in data types as well as allowing support for adaptive test. The WG aims to provide a standards-driven data environment for semiconductor test including simple standards-based data capture, transport and relationship model for eTest, probe, and final test data. Their work also aims to support equipment configuration management and operational performance data. RITdb is a SQLite database with one table, independent from an operating system. Key value store optimized for test data.

Figure 3 STDF to RITdb: PTR

Figure 3 STDF to RITdb: PTR

To date, the group has defined the mapping from STDF v4 to RITdb. A translator developed by the RITdb is also available. The overall schema has already been defined and many file translations have already been tested. Work by the RITdb group will ultimately be developed into SEMI Standards. Therefore, the group has been working on the (SEMI Standard) spec which will be in MS Word, while the database itself will be in a different format. There will be a spec editor that will help ensure the spec is used correctly. The group also plans to expand the spec beyond probe and final test. Meanwhile, the group is working on experiments related to streaming RITdb as well as work on using different extensions (e.g., tester log, streaming). Additional work will be needed on probe maps as well as on doing test cases (i.e., be able to run verifiers to validate the spec).

Improving Test Yield through Common ATE Data Communication Interface

Semiconductor test operations involved in ATE today continues to see a surging demand for data for real-time data analysis and real-time ATE input and control of the test flow to improve test yield, throughput, efficiency, and product quality.  At the same time, test equipment and test operations around the world utilize a diverse range of data formats, specifications, and interface requirements that create significant customer service and application engineering costs for ATE vendors, OSAT companies, IDM test operations, software providers, and handler equipment. A common ATE hardware and software communications interface would help reduce the cost, time and complexity of integrating ATE equipment into data-intensive test operations.

The TEMS WG was chartered to develop a standardized ATE data messaging system based on industry standard internet communication protocols between a Test Cell host and a server.  The standard will be limited to ATE data messaging, using RITdb entity types, where applicable, as well as the standard data format, and control requirements. It will have no impact on other test communication interfaces such as those involving handlers, probers, test instrumentation, and other systems covered by existing standards (e.g., SEMI E30, E4, E5, STDF, etc.).

The group will essentially develop a set of standards to define a vendor neutral way to collect test cell data. The primary spec defines the Model while a subordinate spec defines the Transport layer to maintain consistency with prior standards.

Figure 4 TEMS Focus Area

Figure 4 TEMS Focus Area

Similar to the RITdb activity, the TEMS group plans to transition its two working documents to the SEMI Standards space. As the group continues to fine-tune these documents while maintaining alignment with the RITdb WG, the preliminary SEMI Standards work (e.g., authorize formation of corresponding task force) is expected to occur by the end of the year.

Other ATE Challenges Looming

System Level Test (SLT) is an approach used to guarantee the performance of a product for a particular customer application. However, the term “System Level Test” (SLT) is frequently applied to both the testing of full systems as well as to the testing of chips to ensure their ultimate performance in target systems. This often leads to confusion.

For its 2016 workshop to be held in early November, CAST will address the topic of “Component SLT”, which is the set of application-specific functional tests that are performed prior to I.C. shipment to guarantee a chip’s quality and performance when it will be ultimately used in the final system.  It may also encompass incoming inspection of I.C. components by customers prior to assembly into systems.  Currently, component SLT tends to be implemented primarily on complex SoC devices using custom hardware and software.

Component SLT considerations:

  • Normally component SLT would be applied using a card or board based on the target system’s functional card or board — but with a socket where the IC component is temporarily placed while SLT tests are applied.
  • Component SLT is used by some chip vendors as an IC component test after conventional Final Test on ATE.
  • Potentially, component SLT could also be applied using a custom card within the ATE system that mimics system application tests.
  • Any level of standardization will ease the capital burden and operational flexibility at OSATs.
  • It will be a key requirement to be able to generate data from component SLT that can be shared backwards and forwards along the semiconductor supply chain for yield optimization and quality/reliability management.

Those looking to share their perspectives on component SLT and their vision for its future direction are invited to present at the CAST workshop. The community is particularly interested in opportunities to improve the Component SLT ​infrastructure or methods — that is, identify potential opportunities for CAST to drive improvements through pre-competitive collaboration.

Participating in SEMI CAST Special Interest Group

The SEMI CAST Special Interest Group is open to all SEMI Members. For more information or to join CAST, please contact Paul Trio at SEMI ([email protected]).

SEMI announced today that the deadline for presenters to submit an abstract for the annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is October 17.  ASMC, which takes place May 15-18, 2017 in Saratoga Springs, New York, will feature technical presentations of more than 90+ peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, as well as educational tutorials.

ASMC, in its 28th year, continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.  Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. In addition to publication in the ASMC proceedings, select papers will be invited to participate in a special section of ASMC 2017 to be featured in IEEE Transactions on Semiconductor Manufacturing. Technical abstracts are due October 17, 2016. 

This year SEMI (www.semi.org) is including two new technology areas (3D/TSV/Interposer; Fabless Experience). SEMI is soliciting technical abstracts in these key technology areas:

  • Packaging and Through Silicon Via (3D/TSV)
  • Fabless Experience (FE)
  • Advanced Equipment Processes and Materials (AEPM)
  • Advanced Metrology
  • Advanced Patterning / Design for Manufacturability (AP/DFM)
  • Advanced Process Control (APC)
  • Contamination Free Manufacturing (CFM)
  • Defect Inspection and Reduction (DI)
  • Data Management and Data Mining Tools (DM)
  • Discrete Power Devices (DP)
  • Equipment Reliability and Productivity Enhancements (ER)
  • Enabling Technologies and Innovative Devices (ET/ID)
  • Factory Automation (FA)
  • Green Factory (GF)
  • Industrial Engineering (IE)
  • Lean Manufacturing (LM)
  • MOL and Junction Interfaces (MJ)
  • Smart Manufacturing (SM)
  • Yield Methodologies (YM)

Complete descriptions of each topic and author kit can be accessed at http://www.semi.org/en/node/38316.  If you would like to learn more about the conference and the selection process, please contact Margaret Kindling at [email protected] or call 1.202.393.5552.

Papers co-authored between device manufacturers, equipment or materials suppliers, and/or academic institutions that demonstrate innovative, practical solutions for advancing semiconductor manufacturing are highly encouraged.  To submit an abstract, click here.

Technical abstracts are due October 17, 2016.  To learn more about the SEMI Advanced Semiconductor Manufacturing Conference, visit http://www.semi.org/en/asmc2017.

Semiconductor Research Corporation (SRC), the university-research consortium for semiconductors and related technologies, today announced that NXP Semiconductors has signed an agreement to participate in multiple SRC research initiatives.

NXP is the fifth of the top 10 global semiconductor companies to become a member of SRC, and represents the third non-U.S.-headquartered SRC member company.

NXP has joined three specific SRC research thrusts including Trustworthy and Secure Semiconductors and Systems (T3S); Analog/Mixed-Signal Circuits, Systems and Devices (AMS-CSD); and Computer-Aided Design and Test (CADT).

“For SRC, the NXP membership continues and expands the durable relationship that we have enjoyed first with Motorola’s Semiconductor Products Sector that spun out to become Freescale Semiconductor, which late last year merged with NXP,” said Ken Hansen, President & CEO, SRC. “We’re excited to continue the relationship in these three areas that are critical to advancing semiconductor technology for the electronic devices of today and the future.”

“SRC is a vital element of our global university program, providing access to leading edge research at universities in the U.S. and around the world,” said Hans Dollee, Senior Director and Head of Technology Partnerships at NXP. “As the world leader in secure connectivity solutions for embedded applications, NXP is pleased to join with SRC, other member companies and partner universities to drive future technological breakthroughs and educate the next generation of innovators.”

The three SRC initiatives where NXP is participating are part of 11 research thrusts under SRC’s Global Research Collaboration (GRC) program, which funds university research focused on the constantly evolving challenges for the global semiconductor industry. For a description of each research thrust, visit https://www.src.org/program/grc.

SEMI today announced the appointment of Lung Chu as president of SEMI China effective September 1, 2016. With the recent broadening ambitions for China’s indigenous semiconductor supply chain, Lung Chu joins SEMI at a critical inflection in the China market. Chu will be instrumental in evolving and repositioning SEMI’s programs, committees, products and services in China to deliver the highest member value in the rapidly changing China semiconductor ecosystem.

With the announcement of “National Guideline for IC Industry Development” and “Made in China 2025” initiatives, the China government and industry are set to significantly improve self-sufficiency for integrated circuits (ICs) manufacturing in China by 2025. This stimulated recent China M&A activity across the semiconductor manufacturing supply chain (Spreadtrum, OmniVision, ISS, Mattson Technology, STATS ChipPAC), new investments by Chinese companies (SMIC, XMC, etc.), and investment in China factories by multinationals (Intel, Samsung, SK Hynix, TSMC, GlobalFoundries).

“With China’s rapidly changing industry, Lung Chu was chosen for his wide range of semiconductor supply chain and leadership experience to ensure SEMI China delivers the best platform and services to its members and overall industry with growth and prosperity. Lung’s personal relationships and track record with industry executives and China government officials related to the semiconductor manufacturing industry will benefit SEMI members in China and worldwide. I look forward to working with Lung to transform SEMI China into a local partner for China’s “Made in China 2025″ initiative,” said Denny McGuirk, president and CEO of SEMI.

With over 30 years of experience in semiconductor equipment, IC design, EDA/IP, semiconductor manufacturing, and system integration, Chu is uniquely suited to lead SEMI China’s growth harmonized with the SEMI 2020 Vision to connect and increase collaboration across the entire semiconductor manufacturing supply chain. Most recently, Chu spent seven years as corporate VP and president of China Operations for Global Unichip. Chu served as president of Asia Pacific at Cadence Design Systems, Magma Design Automation; and held executive management positions at KLA-Tencor, Apple Computer, and Philips Semiconductor (in Silicon Valley, California).

Chu served as president/chairman of the Chinese American Semiconductor Professional Organization (CASPA) and currently heads Shanghai and Hsinchu chapters. Chu holds a Bachelor’s degree in engineering from National Taiwan University and a Master’s degree in engineering from Case Western Reserve University. He also has MSEE and MBA degrees from California State University.

IC Insights released its August Update to the 2016 McClean Report earlier this month.  This Update included an update of the semiconductor industry capital spending forecast, a look at the top-25 semiconductor suppliers for 1H16, including a forecast for the full year ranking, and Part 1 of an extensive analysis of the IC foundry industry (the ranking of the top-10 pure-play foundries is covered in this research bulletin).

In 2014, the pure-play IC foundry market registered a strong 17% increase, the largest increase since 2010 and eight points greater than the 9% increase in the worldwide IC market.  In 2015, the pure-play foundry market showed a 6% increase, about one-third the rate of growth in the previous year, but seven points higher than the total IC market growth rate of -1%.  For 2016, the pure-play foundry market is expected to increase by 9% and greatly outperform the growth rate of total IC market, which is forecast to drop by 2% this year.

Figure 1 shows that the top 10 pure-play foundries are expected to hold 95% of the total pure-play foundry market this year.  This year, the “Big 4” pure-play foundries (i.e., TSMC, GlobalFoundries, UMC, and SMIC) are forecast to hold an imposing 84% share of the total worldwide pure-play IC foundry market.  As shown, TSMC is expected to hold a 58% marketshare in 2016, down one point from 2015, as its sales are forecast to increase by $2.1 billion this year, up from a $1.5 billion increase in 2015.  GlobalFoundries, UMC, and SMIC’s combined share is expected to be 26% this year, the same as in 2015.

The two top-10 pure-play foundry companies that are forecast to display the highest growth rates this year are Israel-based TowerJazz, which is expected to edge-out Powerchip for the 5th spot in the pure-play foundry ranking in 2016, and China-based SMIC, with 30% and 27% sales increases, respectively. TowerJazz and SMIC have been on a very strong growth curve over the past few years.  TowerJazz is expected to grow from $505 million in sales in 2013 to $1,245 million in 2016 (a 35% CAGR) while SMIC is forecast to more than double its revenue from 2011 ($1,220 million) to 2016 ($2,850 million) and register a 19% CAGR over this five-year timeperiod.

Figure 1

Figure 1

Eight of the top-10 pure-play foundries listed in Figure 1 are based in the Asia-Pacific region.  Israel-based TowerJazz, and U.S.-headquartered GlobalFoundries are the only non-Asia-Pacific companies in the top-10 group.  While LFoundry is currently headquartered in Avezzano, Italy, China-based SMIC agreed in 2Q16 to purchase 70% of the company for approximately $55 million.  Since LFoundry has an installed capacity of 40K 200mm wafers/month, the acquisition of a controlling interest in the company essentially serves to immediately expand SMIC’s capacity by 13% this year.

Although SMIC is forecast to register strong sales growth of 27% this year, Chinese foundries, in total, are expected to hold only 8.2% of the pure-play foundry market in 2016, down 5.1 points from the peak share of 13.3% reached in 2006 and 2007.  IC Insights believes that the total Chinese company share of the pure-play foundry market will increase through 2020, as the China-based foundries take advantage of the huge amount of government and private investment that will be flowing into the Chinese semiconductor market infrastructure over the next five years.

Aemulus, a developer of automated test equipment (ATE) solutions, and Peregrine Semiconductor Corp., founder of RF SOI (silicon on insulator), announce their strategic partnership in the development of a new microwave frequency tester. Building on the success of Aemulus’s Amoeba AMB7600 RF tester, this next-generation test solution will extend its support into microwave frequency bands and enable more complex testing.

“This Aemulus microwave tester is the latest project in a series of successful collaborations with Peregrine Semiconductor,” says Sang Beng Ng, CEO of Aemulus Corporation. “Our two-year relationship has been an exciting journey as two agile industry leaders move the needle forward in microwave testing. This new tester will not only contribute to growth in test and measurement, but I foresee many opportunities flowing in from other markets with high frequency demands, such as automotive, radar and 5G wireless. With this strategic partnership, we look forward to duplicating the success of previous collaborative projects.”

For this new tester, the Aemulus Amoeba AMB7600 will be upgraded with key peripheral modules to expand into microwave bands X, Ku and Ka. The AMB7600 is the world’s first true multi-site, multi-instance RF tester, and it supports RF, digital and analog testing. While the AMB7600 addresses RF front-end devices, the new tester will enable more complex testing, such as the rigorous testing needs of radar products and mixers. Currently in design development, the new tester will be integrated into Peregrine’s test infrastructure in fall 2016 and will have full implementation by spring 2017.

“As the market demand for high frequency products increases, Peregrine has responded with a robust high frequency product portfolio and has set new records for SOI at microwave frequencies,” says Carl Tulberg, principal engineer, NPI operations at Peregrine Semiconductor. “But this innovation must be supported by a sophisticated test infrastructure and that boils down to the right test equipment. This Aemulus partnership aligns with our product roadmap and ensures we meet our microwave test equipment needs today and in the future. It also highlights Peregrine’s focus and investment in high frequency product development.”

Debunking the industry’s perceived boundaries of RF SOI technology, Peregrine Semiconductor’s high frequency portfolio includes RF switches, an image-reject mixer and monolithic phase and amplitude controllers (MPACs). It is Peregrine’s UltraCMOS technology platform that enables the company to reach these high frequencies without compromising performance or reliability.

Research and Markets has announced the addition of the “China Semiconductor Industry: Expansion Plans Analysis and Trends (Government Policies and Guidelines, Import and Export Impact on Trade Partners, Key Concepts, Case Study, Key Strategies Adopted, Future Plans, and Recommendation to Players)” report to their offering.

The China semiconductor industry is expected to reach $157.66 billion by 2020, at a CAGR of 12.8% between 2016 and 2020, according to this report. The major driving factors for the China semiconductor industry are the growing demand for semiconductors from major verticals and favorable government initiatives. There are also various opportunities available for the growth of the China semiconductor industry such as investment from foreign players and emerging new concepts.

Integrated Circuit (IC) is expected to hold the largest market share by 2020. The IC segment accounted for almost two-thirds of the total semiconductor industry in China in 2015.

Key topics covered:

  • Market Penetration: Comprehensive information on semiconductor products and services offered by the top players in the China semiconductor industry
  • Mergers & Acquisitions: Detailed insights on latest merger and acquisition activities and expansion in the semiconductor industry
  • Market Diversification: Exhaustive information about mergers and acquisitions, contracts, untapped geographies, recent developments, and investments in the China semiconductor industry
  • Competitive Assessment: In-depth assessment of market shares, strategies, products, and manufacturing capabilities of the leading players in the China semiconductor industry