Category Archives: Wafer Processing

Silicon Labs (NASDAQ: SLAB), a provider of silicon, software and solutions for a smarter, more connected world, today named Lori Knowlton as Senior Vice President and Chief People Officer (CPO). In this role, she is responsible for the company’s talent strategy, leadership development, community relations and culture.

“We are delighted to have Lori join the Silicon Labs management team,” said Tyson Tuttle, CEO of Silicon Labs. “She brings a proven ability to translate business strategies into people solutions, as well as deep expertise in attracting, developing and engaging high-caliber talent.”

Prior to joining Silicon Labs, Ms. Knowlton served as CPO for HomeAway.com where she led the company’s people agenda from early-stage growth through an IPO and ultimately through a sale to Expedia. During her nearly ten years at HomeAway, Ms. Knowlton grew the team exponentially and created scale through acquisitions, processes, systems and high employee management.

Previously, Ms. Knowlton served in a variety of human resources leadership roles at leading high-technology companies including Progress Software and its operating company Sonic Software, Interliant, Inc., C-bridge Internet Solutions and the Monitor Company.

“I am excited to join the Silicon Labs team and to have this opportunity to take a strong culture and help make it even better through connection, collaboration and feedback,” said Ms. Knowlton. “Silicon Labs is truly an innovative company filled with great talent. It’s clear that everyone here understands that people are the most important factor in the innovation equation.”

Ms. Knowlton has been a mentor at TechStars Austin for the past three years. In addition, she serves on the strategic planning committee of the Magellan International School, an Austin-based Spanish immersion IB school. She is a frequent and accomplished public speaker at numerous conferences. Ms. Knowlton holds a Bachelor of Arts degree in English literature (magna cum laude) from Bowdoin College in Brunswick, Maine.

ARM and Intel Custom Foundry this week at the Intel Developer Forum in San Francisco an agreement to accelerate the development and implementation of ARM SoCs on Intel’s 10nm process. In their joint press releases, Intel and ARM said that the agreement will enable Intel Custom Foundry to use its upcoming 10nm FinFET platform for fabricating chip designs based on ARM’s Artisan Physical IP.

“The initial POP IP will be for two future advanced ARM Cortex-A processor cores designed for mobile computing applications in either ARM big.LITTLE or stand-alone configurations,” according to ARM’s press release. Intel’s release says that LG will be using the process to “produce a world-class mobile platform based on Intel Custom Foundry’s 10nm design platform.”

The Intel-ARM partnership could provide new foundry options for chipmakers like Qualcomm — and potentially Apple — beyond current industry bigwigs Samsung and Taiwan Semiconductor Manufacturing Co. (TSMC).

Chips based on Intel’s 10nm process are expected at some point in 2017.

GlobalWafers Co., Ltd. and SunEdison Semiconductor Limited (NASDAQ:SEMI) announced today that they have entered into a definitive agreement for the acquisition by GlobalWafers of all of the outstanding ordinary shares of SunEdison Semiconductor in a transaction valued at US$683 million, including SunEdison Semiconductor outstanding net indebtedness.

Under the terms of the agreement, SunEdison Semiconductor shareholders will receive US$12.00 per share in cash for each ordinary share held, representing a 78.6% premium to the average closing price of SunEdison Semiconductor’s common stock for the 30 trading days prior to this announcement and a 44.9% premium to the closing price of SunEdison Semiconductor’s ordinary shares as of August 17, 2016, the last trading day prior to this announcement.  The transaction has been unanimously approved by both GlobalWafers’ and SunEdison Semiconductor’s boards of directors.

The transaction will be structured as a scheme of arrangement under Singapore law, and is subject to the approval of the shareholders of SunEdison Semiconductor, as well as other customary conditions including approvals from relevant regulatory authorities and the High Court of the Republic of Singapore.  SunEdison Semiconductor has requested and obtained a waiver from the Securities Industry Council of Singapore of the application of the Singapore Code on Take-overs and Mergers to the scheme of arrangement.

“We are very excited by this transaction,” said Doris Hsu, Chairperson and CEO of GlobalWafers.  “We believe this combination is unique in that it merges two of the market’s key suppliers with minimal overlap in customers, products and production capacities.  The combined company will bring together GlobalWafers’ unparalleled operating model and market strengths with SunEdison Semiconductor’s expansive global footprint and product development capabilities.  We will remain focused on our customers and will strengthen and build on our product offerings to deliver even greater value to our customers and shareholders,” Hsu concluded.

“We are pleased to have reached an agreement that delivers a significant premium to our shareholders,” said Shaker Sadasivam, President and Chief Executive Officer of SunEdison Semiconductor.  “We believe this transaction is in the best interest of our company.  We look forward to a smooth process to facilitate an efficient closing, which we hope can occur before the end of the year.”

GlobalWafers will finance the transaction, including payment of the purchase price and payment of SunEdison Semiconductor’s debt facilities at closing, through existing cash on hand and committed acquisition financing from the Bank of Taiwan, Hua Nan Commercial Bank, Mega International Bank, Taipei Fubon Bank, and Taishin International Bank.

GlobalWafers expects a number of strategic and operational benefits from this transaction, including:

  • Meaningful expansion of GlobalWafers’ production capabilities
  • Greater breadth in GlobalWafers’ product and global customer base, including greater access to the E.U. and Korea, as well as SOI product technologies
  • Significant increase in GlobalWafers’ financial scale

Related news: 

SunEdison Semiconductor announces manufacturing consolidation

SunEdison Semiconductor solidifies polysilicon supply

Is silicon’s heyday over? New materials challenge the industry workhorse

Technavio analysts forecast the global silicon photonics market to grow at an impressive CAGR of over 48% during the forecast period, according to their latest report.

The research study covers the present scenario and growth prospects of the global silicon photonics market for 2016-2020. The report also segments the market on the basis of application into the three categories consisting of communications, consumer electronics and others, with communications accounting for 95% of the market. The use of silicon photonics components in the consumer electronics sector is limited to a mere 1% during the forecast period, however, this segment is expected to grow at a CAGR of over 48% during the forecast period. Other sectors such as medical, military, and robotics present considerable growth potential for this technology. The others sector will grow at a CAGR of close to 61% during the forecast period.

The silicon photonics technology can achieve speeds of up to 100 Gbps. The use of this technology will help increase power efficiency and improve the data transfer rate.

Silicon photonics technology is a novel approach to manufacturing optical devices from silicon and uses photons to transfer large volumes of data at very high speeds using extremely low power over thin optical interconnects instead of using electrical signals over a copper cable.

Technavio hardware and semiconductor analysts highlight the following four factors that are contributing to the growth of the global silicon photonics market:

  • Need for higher network bandwidth
  • Reduction in transportation costs and scalability beyond 40G
  • Huge investments through public funding
  • Silicon photonics will improve energy efficiency

Need for higher network bandwidth

According to Asif Gani, a lead analyst at Technavio for embedded systems research, “The growth in internet bandwidth is fueled by two factors which are the proliferation of smartphones, tablets, and wearables with increasing functionalities and the emergence of disruptive technologies that increase bandwidth use.

Silicon photonic devices are capable of transmitting data using far less power and of moving information much more quickly by achieving speeds of up to 40 Gbps. The primary reason a large number of companies are pushing to bring this technology to the market, is that silicon photonics is required for exascale-level computing.

Reduction in transportation costs and scalability beyond 40G

The adoption of silicon photonics has benefited the carriers largely. This network structure has allowed them to transport to multiple clients on a single wavelength and preserve their specific requirements. The overall cost of transportation has also fallen, as they don’t need separate wavelengths for separate clients, thereby ensuring efficient bandwidth utilization.

With silicon photonics, carriers are able to provide high-capacity services at speeds of 100G and above. The network architecture of silicon photonics is designed and optimized to support massive capacity services such as 400G or even terabit payloads. This was not possible with the previous generation technologies such as SONET or software-defined networking (SDN). This will create demand for silicon photonics devices in the global market.

Silicon photonics technology is also able to support the partitioning of the network into separate private networks. This allows the carriers to offer clients dedicated, specific, and configurable bandwidth with a guarantee on network capacity and enhanced performance for each client. This portioning does not affect the existing services or existing users in any way. Thus, clients can now have a dedicated and independent set of network resources.

Huge investments through public funding

Silicon photonics technology shows significant potential for increasing data transmission speeds at lower costs in the coming years. In 2015, IBM announced a breakthrough in the field of silicon photonics by introducing the first fully integrated wavelength multiplexed chip. This new device is designed to aid the production of 100 Gbps optical transceivers and permits electrical and optical components to function side-by-side in one package. This type of on-die integration will be important to the long-term deployment of optical technology over short distances.

Apart from IBM, companies like Intel, Luxtera, and many more are investing heavily in making silicon photonics more efficient and reliable. The efforts made by these companies have been noticed by government organizations and investors around the globe. The silicon photonics market is receiving support in the form of large investments. In July 2015, the US government announced an investment of over USD 600 million in the photonics industry as a step toward investment in US manufacturing. A large portion of this funding will be dedicated solely to the development of silicon photonics technology. “These investments, will help the rapid development of silicon photonics technology and thus will continue to drive the growth of the market during the forecast period,” says Asif.

Silicon photonics will improve energy efficiency

Photonics technologies form the core of today’s telecommunication and data infrastructure. They will be integrated into communications networks. The adoption of a range of photonic technologies in the communications sector will have a considerable impact on the energy efficiency of these networks. Industry experts have estimated that photonic transmitters, photonic tunable lasers, photonic receivers, and photonic multiplexing components will contribute to energy savings of almost 5%-10% by 2020 with the integration of photonics integrated circuits.

This is primarily because photonic components will reduce the need for cooling by allowing devices to operate at higher temperatures, as well as make electrical-to-optical conversion efficient by removing non-radiative recombination processes. The complete implementation of the photonics technology into the communications sector will increase the energy efficiency even further. In 2015, major players in the communications sector such as AT&T, Bell Labs, Huawei, and Chunghwa Telecom agreed to improve energy efficiency by adopting silicon photonics technology.

BY ALLYN JACKSON, CyberOptics Corp., Minneapolis, MN

Key IC fabrication steps are sensitive to moisture in semiconductor wafer environments. As the technology node advances, the need for characterizing and minimizing the exposure to relative humidity (RH) has become critical in all 29nm geometry fabs and below. These RH control requirements create a need for a wireless wafer-like humidity sensor which simultaneously measures RH at several points across the wafer as well as throughout the entire IC manufacturing environment.

Challenges with current methods for characterizing N2 FOUPS

Current methods for characterizing N2 Purge FOUPs have problems. These methods are typically not real time, are time consuming, are hard to use and are not able to take RH measurements under production conditions therefore are not reflective of these conditions. In addition, wired (FIGURE 1) hand-held RH meters (FIGURE 2) and single trace hand-held meters are limited to one area and cannot move throughout the process environment. Other options are hand-made alternatives (FIGURE 3) such as a wafer with RH sensors simply taped on. Lastly, they are often limited without data files generated so conse- quently statistics and quality standards cannot be established.

FIGURE 1. FOUP with Wired RH Sensors Attached

FIGURE 1. FOUP with Wired RH Sensors Attached

FIGURE 2. Hand-held RH Meter with Single Trace RH Reading

FIGURE 2. Hand-held RH Meter with Single Trace RH Reading

FIGURE 3. Silicon Wafer With 4 RH Recording Sensors Taped on.

FIGURE 3. Silicon Wafer With 4 RH Recording Sensors Taped on.

RH environment test target and goals

The test at the customer involved putting an RH meter inside the FOUP pointing around slot 13. The goal was to repeat the RH meter profile for testing a FOUP on one loadport without the need to open the FOUP. Starting at 40% RH (cleanroom environment), the first step was to run high purity, high volumnet N2 pre-purge for 4-5 minute and then take the reading. The second step is to conduct a maintenance purge to 5% and measure the results in 5 locations across the wafer. The next step was to run a process purge to 20% and take sample readings across various locations. The goal of the testing it to test the efficiency of the N2 purge FOUP diffusers to ensure that uniform purge levels are maintained.

In response to the need for a reliable easy to use method of qualifying N2 and XCDA environments, the WaferSense® Auto Multi-Sensor (AMS) by CyberOptics (FIGURE 4) was developed. Wafer- Sense AMS is a wireless wafer-like device with five RH sensors to measure the RH profile across the entire wafer surface.

FIGURE 4. WaferSense® Auto Multi Sensor Measurement Device.

FIGURE 4. WaferSense® Auto Multi Sensor Measurement Device.

FIGURE 5. N2 Purge FOUP with 3 Inlet and one Outlet Ports.

FIGURE 5. N2 Purge FOUP with 3 Inlet and one Outlet Ports.

AMS is a complete and easy-to-use system which communicates wirelessly via Bluetooth to the MultiViewTM application (FIGURE 6) and moves like a normal wafer to all locations in the wafer process environment providing a true characterization of the N2 purge uniformity. Such previously hard to accomplish tasks such as characterizing purge FOUP diffuser uniformity and measuring actual RH percentages are now easily accomplished with AMS. (FIGURE 5) AMS is a true multi-functional device which also measures vibration and can be used for leveling to ensure proper wafer handling.

FIGURE 6. Profile of N2 Purge Using MultiViewTM Software to Displays RH Measurements in 4 Sensor Locations across the Wafer Surface.

FIGURE 6. Profile of N2 Purge Using MultiViewTM Software to Displays RH Measurements in 4 Sensor Locations across the Wafer Surface.

29nm geometry fabs and smaller require well controlled N2 and XCDA purge environments to prevent defects and yield loss. AMS300 simultaneously measures RH in real-time at five locations on the wafer while it transfers like a wafer to qualify N2 and XCDA environments. The AMS device significantly shortens the task of qualifying these environments. In addition, the AMS300 provides and vibration and leveling measurement capabilities to ensure proper wafer handling and reduced particles. The overall result for the fab is improved N2 purge environment uniformity which results in reduced defects and reduced labor costs.

Reducing reticle haze effects

193nm Immersion scanners are adversely affected by a phenomenon called “Reticle Haze” when proper measures are not taken to measure and control it. There are three areas that need to be controlled to reduce this haze effect on reticles, one of which is controlling RH. Reticle haze is accelerated when H2O is present. (FIGURE 7).

FIGURE 7. Reticle Haze Formation Accelerated with H2O

FIGURE 7. Reticle Haze Formation Accelerated with H2O

There is a key need for a measurement device that will eliminate the inefficiencies of the current methods.

Challenges with current methods for monitoring RH in reticle environments

There are several limitations with the current reticle environment RH measurement methods, for example, hand-held RH sensors (FIGURE 9) are inconvenient and they can compromise the reticle environment. Plus, many areas are inaccessible by hand-held RH sensors, in-situ RH sensors or benchtop type RH sensors. (FIGURE 8)

FIGURE 8. Benchtop RH Sensor

FIGURE 8. Benchtop RH Sensor

Figure 9: Wired In-Situ RH Sensor

Figure 9: Wired In-Situ RH Sensor

Additionally, the importance of particle, leveling, vibration and RH control has rarely been overlooked in reticle environment. However, the need to maximize both yields and tool uptimes in reticle mask environments requires best-in-class practices.

Whether for diagnostics, qualification or preventative maintenance, equipment engineers need to efficiently and effectively make measurements and adjustments to the tools. Legacy particle, vibration, leveling and RH measurement methods are typically cumbersome, non-representative, not real time, compromise the production environment and are costly with downtime required to take the tool offline for these tasks.

By contrast, best practice methods involve collecting and displaying data in real-time, speeding equipment alignment or set-up. Real-time data also speeds equipment diagnostic processes, saving valuable time and resources. Equipment engineers can also make the right adjustments consistently by using objective and reproducible data that enhances process uniformity.

The ReticleSense® AMSR (FIGURE 10) is an actual glass reticle that measures H2O in the reticle environment and is compatible with ASML, Canon and Nikon scanners. AMSR is used to travel throughout the entire reticle environment and measures RH. (FIGURE 11) It helps locate the sources of the H2O which results in increased reticle lifetime. Two additional measurement capabilities of the device include measuring X, Y and X vibration (FIGURE 12) and inclination. (FIGURE 13).

FIGURE 10. ReticleSense® Auto Multi Sensor Measurement Device.

FIGURE 10. ReticleSense® Auto Multi Sensor Measurement Device.

FIGURE 11. RH Measurement

FIGURE 11. RH Measurement

FIGURE 12. Vibration Measurement

FIGURE 12. Vibration Measurement

FIGURE 13. Leveling Measurement

FIGURE 13. Leveling Measurement

Conclusion

The AMSR travels the entire path of the reticle and can measure humidity in all locations. In immersion scanner environments, monitoring humidity is critical in reticle reducing haze. Equipment qualifications can be done faster as the same device also measures vibration and leveling. Controlling inclination, RH and vibration are all important factors in increasing yield and reducing downtime.

For RH measurements in N2 and XCDA reticle mask environments, the use of a real-time measurement device, the Auto Multi Sensor, delivers on three compelling bottom lines for the fab – saving time, saving expense and improving yields.

One of the most critical issues the United States faces today is preventing terrorists from smuggling nuclear weapons into its ports. To this end, the U.S. Security and Accountability for Every Port Act mandates that all overseas cargo containers be scanned for possible nuclear materials or weapons.

Detecting neutron signals is an effective method to identify nuclear weapons and special nuclear materials. Helium-3 gas is used within detectors deployed in ports for this purpose.

The catch? While helium-3 gas works well for neutron detection, it’s extremely rare on Earth. Intense demand for helium-3 gas detectors has nearly depleted the supply, most of which was generated during the period of nuclear weapons production during the past 50 years. It isn’t easy to reproduce, and the scarcity of helium-3 gas has caused its cost to skyrocket recently — making it impossible to deploy enough neutron detectors to fulfill the requirement to scan all incoming overseas cargo containers.

Helium-4 is a more abundant form of helium gas, which is much less expensive, but can’t be used for neutron detection because it doesn’t interact with neutrons.

A group of Texas Tech University researchers led by Professors Hongxing Jiang and Jingyu Lin report this week in Applied Physics Letters, from AIP Publishing, that they have developed an alternative material — hexagonal boron nitride semiconductors — for neutron detection. This material fulfills many key requirements for helium gas detector replacements and can serve as a low-cost alternative in the future.

The group’s concept was first proposed to the Department of Homeland Security’s Domestic Nuclear Detection Office and received funding from its Academic Research Initiative program six years ago.

By using a 43-micron-thick hexagonal boron-10 enriched nitride layer, the group created a thermal neutron detector with 51.4 percent detection efficiency, which is a record high for semiconductor thermal neutron detectors.

“Higher detection efficiency is anticipated by further increasing the material thickness and improving materials quality,” explained Professor Jiang, Nanophotonics Center and Electrical & Computer Engineering, Whitacre College of Engineering, Texas Tech University.

“Our approach of using hexagonal boron nitride semiconductors for neutron detection centers on the fact that its boron-10 isotope has a very large interaction probability with thermal neutrons,” Jiang continued. “This makes it possible to create high-efficiency neutron detectors with relatively thin hexagonal boron nitride layers. And the very large energy bandgap of this semiconductor — 6.5 eV — gives these detectors inherently low leakage current densities.”

The key significance of the group’s work? This is a completely new material and technology that offers many advantages.

“Compared to helium gas detectors, boron nitride technology improves the performance of neutron detectors in terms of efficiency, sensitivity, ruggedness, versatile form factor, compactness, lightweight, no pressurization … and it’s inexpensive,” Jiang said.

This means that the material has the potential to revolutionize neutron detector technologies.

“Beyond special nuclear materials and weapons detection, solid-state neutron detectors also have medical, health, military, environment, and industrial applications,” he added. “The material also has applications in deep ultraviolet photonics and two-dimensional heterostructures. With the successful demonstration of high-efficiency neutron detectors, we expect it to perform well for other future applications.”

The main innovation behind this new type of neutron detector was developing hexagonal boron nitride with epitaxial layers of sufficient thickness — which previously didn’t exist.

“It took our group six years to find ways to produce this new material with a sufficient thickness and crystalline quality for neutron detection,” Jiang noted.

Based on their experience working with III-nitride wide bandgap semiconductors, the group knew at the outset that producing a material with high crystalline quality would be difficult.

“It’s surprising to us that the detector performs so well, despite the fact that there’s still a little room for improvement in terms of material quality,” he said.

One of the most important impacts of the group’s work is that “this new material and its potential should begin to be recognized by the semiconductor materials and radiation detection communities,” Jiang added.

Now that the group has solved the problem of producing hexagonal boron nitride with sufficient thickness, as well as crystalline quality to enable the demonstration of neutron detectors with high efficiency, the next step is to demonstrate high-sensitivity of large-size detectors.

“These devices must be capable of detecting nuclear weapons from distances tens of meters away, which requires large-size detectors,” Jiang added. “There are technical challenges to overcome, but we’re working toward this goal.”

BY DR. ZHIHONG LIU, Chairman and CEO, ProPlus Design Solutions

Semiconductor processes have long been a mystery for many circuit designers. They didn’t need to worry about how chips were fabricated most of the time, thanks to the many EDA innovations that make their jobs easier and complex designs possible.

The success of the foundry-fabless business model over the past 20 years has been one of the main drivers of the booming of semiconductor industry. The cooperation between foundries and IC designs in fabless companies for process development worked so well that process engineers and circuit designers only needed to focus on their area of expertise. EDA flows simplified the interaction by using process design kits (PDKs) as the information carrier for circuit designs and sent tapeout databases (GDSII) back to the foundry for chip fabrication. Most designers didn’t need to dig into the process.

That was then. The designer now is forced to understand process and devices when moving to smaller nodes in order to achieve more competitive designs. Because process is the least understood, the loose link between process and design should be enhanced to improve design and tapeout confidence.

Knowing processes and devices would help designers make better use of the process platform and improve designs. Device geometries are getting smaller and new structures such as FinFET and FD-SOI are becoming mainstream leading to complicated device characteristics and SPICE models, the most critical components in the PDK. They represent a process platform’s performance and device characteristics, fundamental to good circuit design. A solid understanding of SPICE models becomes necessary to make full use of the process. This is true not only for designs at advanced nodes at 28nm beyond, such as 16nm, 14nm and10nm, but critical for some refreshed older technologies for IoT/Wearable applications.

Running a full evaluation of process and device performance would provide guidance to better select device types, optimize device sizes and bias conditions, trade-off circuit speed and power. The same logic can be applied to generic circuit designs at any technology node, such as analog
designs at 180nm or above.

This practice is used mostly within IDMs where process and design teams have fairly direct channels to work cooperatively. Recently, fabless companies strengthened links with foundries to under- stand the process and devices to improve design output or for process-circuit co-design for high-end chip designs with more aggressive speed, power and performance specifications.

These efforts are significant. Most companies don’t have the resources and time to build a dedicated team and flow and there have been no available EDA tools dedicated to helping designers understand process and facilitate process development interactions. Increasing time-to-market pressures and tough competition drive the need to a higher priority.

Without an EDA tool, current practices can easily take weeks or months to build, maintain and run a flow by creating scripts or SPICE netlists for different evaluation items. It’s practically impossible to run through the cases to generate a full picture of process platform for designers within a short turnaround time.

As a result, it’s hard to come up with a set standard for process evaluation before using it in design, as efforts can vary for different projects. For a big corporation with many design projects, dealing with multiple foundries, using multiple technology nodes and different process platforms, this type of work is critical to its success however becomes overloaded.

Furthermore, the complexity of SPICE models is exploding. Thousands of parameters in each model and a huge model library file with more than 100K lines of code are quite common. Macro models with complicated layout- dependent effects and random variations add more dimensions of complexity.

Complexity and time pressures are huge. An EDA tool to manage both would be indispensable.

One tool could use the PDK library as the input to explore, compare and verify models. It could help designers under- stand and explore the process-design space to guide process platform selection and enable quick adoption of the process and assist designs. It would help designers dig into the process from different angles, including a high-level summary of the process and device performance, device characteristics, statistical behavior and circuit performance related to the application. This should enable designers quickly adopt and make full use of a process platform that suits their needs.

IC Insights will release its August Update to the 2016 McClean Report later this month. This Update includes an update of the semiconductor industry capital spending forecast, an analysis of the IC foundry industry, and a look at the top-25 semiconductor suppliers for 1H16, including a forecast for the full year ranking (the top 20 1H16 semiconductor suppliers are covered in this research bulletin).

The top-20 worldwide semiconductor (IC and O-S-D—optoelectronic, sensor, and discrete) sales ranking for 1H16 is shown in Figure 1. It includes eight suppliers headquartered in the U.S., three in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and six fabless companies. If the three pure-play foundries were excluded from the top-20 ranking, China-based fabless supplier HiSilicon ($1,710 million), U.S.-based IDM ON Semiconductor ($1,695 million), and U.S.-based IDM Analog Devices ($1,583 million) would have been ranked in the 18th, 19th, and 20th positions, respectively.

IC Insights includes foundries in the top-20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted. With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers. As shown in the listing, the foundries and fabless companies are identified. In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-20 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

Thirteen of the top-20 companies had sales of at least $3.0 billion in 1H16.  As shown, it took $1.86 billion in sales just to make it into the 1H16 top-20 semiconductor supplier list.  There was one new entrant into the top-20 ranking in 1H16 as compared to the 2015 ranking—AMD, which replaced Japan-based Sharp.  In 2Q16, AMD registered a strong 23% increase in sales while Sharp was moving in the opposite direction logging a 13% decline in its 2Q16/1Q16 revenue.

Intel remained firmly in control of the number one spot in the top-20 ranking in 1H16.  In fact, it increased its lead over Samsung’s semiconductor sales from only 20% in 2015 to 33% in 1H16.  The biggest upward move in the ranking was made by Apple, which jumped up three positions in the 1H16 ranking as compared to 2015. Other companies that made noticeable moves up the ranking include MediaTek and the new Broadcom Ltd. (the merger of Avago and Broadcom), with each company moving up two positions.

Apple is an anomaly in the top-20 ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers.  IC Insights estimates that Apple’s custom ARM-based SoC processors had a “sales value” of $2.9 billion in 1H16, which placed them in the 14th position in the top-20 ranking.

In total, the top-20 semiconductor companies’ sales increased by 7% in 2Q16/1Q16.  Although, in total, the top-20 2Q16 semiconductor companies registered a 7% increase, there were seven companies that displayed a double-digit 2Q16/1Q16 jump in sales and only two that registered a decline (Intel and Renesas).

The fastest growing top-20 company in 2Q16 was Taiwan-based MediaTek, which posted a huge 32% increase in sales over 1Q16.  Although worldwide smartphone unit volume sales are forecast to increase by only 5% this year, MediaTek’s application processor shipments to the fast-growing China-based smartphone suppliers (e.g., Oppo and Vivo), helped drive its stellar 2Q16/1Q16 increase.  Overall, IC Insights expects MediaTek to register about $8.8 billion in sales in 2016, which would represent a 31% surge over the $6.7 billion in sales the company had last year.

As expected, given the possible acquisitions and mergers that could/will occur over the next few years, the top-20 ranking is likely to undergo a significant amount of upheaval as the semiconductor industry continues along its path to maturity.

A look at control of process uniformity across the wafer during plasma etch processes.

BY STEPHEN HWANG and KEREN KANARIK, Lam Research Corporation, Fremont, CA

Controlling process variability to achieve repeatable results has always been important for meeting yield and device performance requirements. With every advance in technology and change in design rule, tighter process controls are needed. In all of these cases, there are multiple sources of variability, often generalized as: within die, across wafer, wafer to wafer, and chamber to chamber. Typically, less than one third of the overall variation is allowed for variation across the wafer. For example, at the 14 nm node, the allowable variation for gate critical dimensions (CDs) is less than 2.4 nm, of which only about 0.84 nm is allowed for variation across the wafer [1]. At the 5 nm node, the allowable variation across the wafer may be less than 0.5 nm, or equivalent to two or three silicon atoms. In this article, we will discuss control of process uniformity across the wafer during plasma etch processes, its evolution in the industry, and some key focus areas.

A fundamental challenge in controlling uniformity in etch processes is the complexity of a plasma. Achieving the desired etch result (e.g., post-etch profile with selectivity to different film materials) requires managing the ratio of different ions and neutrals (e.g., Ar+, C4F8, C4F6+, O, O2+). Since the same plasma generates both types of species, the relative amount of ions to neutrals is strongly coupled. As a result, the impact of parameters typically used to control the plasma (e.g., source power and chamber pressure) are also interdependent.

Improving uniformity through design

Since the start of single-wafer processing in the early 1980s, etch chambers have been designed to produce similar plasma conditions on every location on the wafer to achieve uniform process results. This is especially challenging since there can be inherent electrical and chemical discontinuities at the edge (FIGURE 1) that affect uniformity across the wafer. Voltage gradients are created at the wafer edge due to the change from a biased surface to a grounded or floating surface. This bends the plasma sheath at the wafer edge, which changes the trajectory of ions relative to the wafer. The chemical potential discontinuity is analogous and produces concentration gradients for different species across the wafer. The gradients are caused by multiple phenomena, including variation in reactant consumption and by-products emissions rates at the center relative to the edge, as well as differences in temperature between the chamber and wafer that cause different absorption rates of chemical species.

Lam_Research_Figure_01

FIGURE 1. Discontinuities caused by the wafer edge create gradients that impact uniformity across the surface, with a significant impact at the edge.

 

Many chamber design changes have been implemented over the years to improve radial symmetry (FIGURE 2a). For example, a key hardware parameter for capacitively coupled plasma (CCP) chambers is the gap between the cathode and anode. Historically, the gap would be designed to provide the most uniform etch for a given power, pressure, and mixture of gas chemistries. On inductively coupled plasma (ICP) chambers, the gas injection location was a key design feature that would vary by process. In aluminum etch chambers, the reactant gas was delivered from a showerhead above the wafer. For silicon etch, the reactant gases were injected from around the perimeter of the wafer, but then evolved so that the gas was injected from above the center of the wafer.

FIGURE 2. Process non-uniformity has both radial and non- radial components (A). On a wafer map showing overall non- uniformity, removal of radial asymmetry allows isolating the more challenging non-radial component (B).

FIGURE 2. Process non-uniformity has both radial and non- radial components (A). On a wafer map showing overall non- uniformity, removal of radial asymmetry allows isolating the more challenging non-radial component (B).

With continuous optimization of chamber design, non-radial patterns became more apparent. On a uniformity map, the average of all the points within every radius can be taken and subtracted from the map, which leaves the more difficult asymmetric portion (FIGURE 2b). With this awareness, focus shifted toward elimi- nating asymmetries in the chamber design.

In retrospect, some of these improvements seem obvious. For instance, up to the late 1990s, it was not uncommon to have etch chambers with the turbomolecular pump located to the side of the wafer. This design created a side- to-side pattern due to the convective flow of reactants and by-products laterally across the wafer. By moving the pumps under the wafer, the flow became radially symmetric, thereby eliminating the process asymmetry.

In other cases, the source of asymmetry was more subtle. One interesting non-uniformity corrected with design was a problematic side-to-side pattern on the wafer that had a seemingly random orien- tation chamber-to-chamber. After extensive investigation to eliminate possible sources in the chamber hardware, the pattern was correlated with the Earth’s magnetic field (FIGURE 3). This example demon- strates the sensitivity of plasma processes, even to minor external influences. Although not specifically a chamber issue, the problem was corrected by applying special shielding with high magnetic-permeability materials around the chamber.

FIGURE 3. Non-uniformity induced by the Earth’s magnetic field was identified in an etch process (A). Applying magnetic shielding corrected the problem and provided uniform etch results (B).

FIGURE 3. Non-uniformity induced by the Earth’s magnetic field was identified in an etch process (A). Applying magnetic shielding corrected the problem and provided uniform etch results (B).

 

Development of process tuning capabilities

As etch processes became more varied and complex, fixed chamber designs were not sufficiently flexible to meet increasingly stringent requirements since it was not practical to provide a specific uniformity kit optimized for each etch process. Moreover, it was more challenging to achieve uniform results when etch technology transitioned from processing 200 mm to 300 mm wafers in the early 2000s. As a result, tuning capabilities were developed to deliver the uniformity control needed for a wide range of processes and larger wafer sizes.

By the early 2000s, the first uniformity tuning knobs focused on controlling the chemistry over the wafer. This was done in several ways, for example by splitting the main reactant gases into different locations or by adding tuning gases at separate locations from the main reactant gas. Since then, a number of tunable parameters have been identified for etch processes (Table 1). Ideally, orthogonal (independent) tuning knobs are used in order to match compensation as closely as possible to root causes. This provides the greatest impact on the process while limiting impact on other parameters. For example, in many dielectric etch processes, the etch rate is limited by the flux of ions from the plasma. Since gas injection doesn’t significantly impact plasma density uniformity, Lam Research developed tunable gap technology for CCP chambers to achieve uniform flux of ions across the wafer for a given set of process conditions.

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Over the years, continued development has focused on increasing the spatial resolution for better control across the wafer. For example, gas was at first only injected from the center location above the wafer. Then, additional capability was added that allowed controlling the ratio of gas directed to the center or edge of the wafer. Several years later, an additional gas injection location was added around the periphery of the wafer. To use wafer temperature as a control knob, different heating or cooling zones can be added to an electrostatic chuck (ESC), which holds the wafer. Historically, the number of temperature zones has increased from one to two (by 2002) to four radial zones (by 2006) to improve the radial uniformity of CDs. Since temperature directly affects CD uniformity (CDU), this is an effective way to tackle one of the most critical uniformity challenges.

Some of the most complex process flows today rely on these sophisticated tuning capabilities. Innovations that drive continuous scaling, such as 3D FinFET devices, advanced memory schemes, and double/quadruple patterning techniques, add to the challenge of reducing variability due to the increasing number of steps within the integration flows. Even if the uniformity for individual unit processes (including etch) are relatively good, their combined impact can be significant, and there is need to compensate somewhere in the flow.

When the uniformity profile of a step in the sequence, upstream or downstream, is known and difficult to correct, the profile of an etch step can be modified. For example, if one step is center fast, etch can compensate by being edge fast. This may sound simple, but it is actually quite difficult to achieve the level of process control that can essentially provide a mirror image of the non-uniformity in another process. Fortunately, plasma etch is one process that has matured to being capable of this level of control.

Uniformity control today

After many years of innovation, uniformity control capabilities now have the following characteristics:
• A high degree of granularity (numerous independent tuning locations across the wafer)
• Active tuning of both radial and non-radial patterns
• The ability to compensate for non-unifor- mities upstream and downstream of the etch process

One strategy being used at Lam to achieve the degree of control now needed is providing numerous independent heaters or micro-zones to control the wafer temperature, which is a critical parameter impacting CD uniformity. For example, using more than 100 localized heaters on one etch chamber delivers significantly higher spatial resolution than a system using only two or four heater zones for the entire wafer. Control of numerous individual heaters tunes both radial and non-radial patterns, whereas only center-middle-edge tuning was possible in previous generations (FIGURE 4).

FIGURE 4. Active uniformity control has evolved from limited radial tuning of large areas of the wafer to independent tuning of ever smaller regions across the wafer, enabling control of both radial and non-radial uniformity.

FIGURE 4. Active uniformity control has evolved from limited radial tuning of large areas of the wafer to independent tuning of ever smaller regions across the wafer, enabling control of both radial and non-radial uniformity.

With such high granularity, it is challenging for an individual engineer to manually determine the appropriate settings for so many heaters that will achieve a target thermal pattern across the wafer. To address this issue, advanced algorithms and controls with special temperature calibrations were developed so that the system automatically controls the heaters. Moreover, it can be difficult to determine the thermal map profile that will achieve the required process uniformity. Sophisticated software algorithms have also been developed to use process trends, chamber calibration data, and wafer metrology information to automatically create the appropriate thermal maps. With this capability, incoming non-uniformity can be reduced to less than 0.5 nm CDU after etch (FIGURE 5).

FIGURE 5. Proprietary hardware and software map incoming CDs and adjust etch process conditions in the numerous micro- zones across the wafer to compensate for variability from upstream processes.

FIGURE 5. Proprietary hardware and software map incoming CDs and adjust etch process conditions in the numerous micro- zones across the wafer to compensate for variability from upstream processes.

Future focus areas

Beyond the uniformity challenges discussed, performance at the edge of the wafer – the outer 10mm, where up to 10% of the die may be located – is an increasingly important area of future focus for improving yield. In this region, uniformity control is dominated by the electrical discontinuities at the edge of the wafer that can cause sheath bending. The impacted region of sheath bending is much smaller (~10-15 mm from the edge) compared to chemical or thermal effects (50-70 or 30-50 mm, respectively). While fixed edge hardware can be redesigned for optimal uniformity, new technologies are in development to provide in situ tunability of the sheath at the wafer edge.

Looking ahead, we can expect more types of control knobs and further granularity for finer tuning along with a greater focus on automation. Compensatory process control should continue to develop and be used as process modules become increasingly complex.

REFERENCES

1. ITRS 2013: Table FEP 12 Etch Process Technology Requirements

SEMI today announced that SEMICON Japan 2016, at Tokyo Big Sight on December 14-16, has increased exhibition and programming to keep pace with high-growth semiconductor segments in Japan. SEMICON Japan, celebrating its 40th anniversary, is the leading electronics event in Japan, with more than 700 exhibitors and 35,000 attendees.

With the world’s largest installed fab capacity of over 4.1 million (200mm equivalent) wafers per month and its diverse product mix, Japan is well-positioned to meet the increasing demands of the new world of electronics – from innovations in mobile technologies to the growing “World of IoT” devices.  SEMICON Japan 2016 connects the players and companies across the electronics manufacturing supply chain by facilitating communications and partnerships. Highlights of the exhibition area include:

  • Themain exhibit zone includes a Front-end Process zone and a Back-end/Materials Process zone.
  • “World of IoT (Internet of Things)”, a “show-within-a-show,” is where semiconductor manufacturing intersects IoT applications including wearable, health care, medical, automotive, and more. The World of IoT this year newly expands its scope to include flexible hybrid electronics (FHE), an essential enabling technology for IoT applications. Exhibiting companies include Japanese flexible and printed electronics companies from key institutes and associations for the industry area.
  • The Sustainable Manufacturing Pavilion, features solutions for the expanding IoT market driving 200mm lines; exhibitors include used and refurbished equipment, cleanroom-related, environmental safety, and more.
  • The Manufacturing Innovation Pavilion showcases innovations for leading-edge lower-cost semiconductor devices; exhibitors include advanced lithography, 2.5D/3D-IC, innovative manufacturing systems, specialty materials, OLED/LED/PE manufacturing equipment and materials.
  • Innovation Village, an interactive exposition showcase arena. Exhibitors are early-stage startups seeking funding, partners, and media exposure in the domain of electronics, materials, IT, tele-communications, bio, med-tech, environment, security or hardware.

For complete information of exhibits and programs, visit www.semiconjapan.org/en.