Category Archives: Wafer Processing

By Yoichiro Ando, SEMI Japan

The 2016 global semiconductor market is forecast to decrease by 2.4 percent from the previous year according to the World Semiconductor Trade Statistics (WSTS). SEMI forecasts that the global semiconductor manufacturing equipment market will be effectively flat this year. However, SEMI also forecasts double-digit growth in 2017 with significant new fab construction starts in 2016 and 2017 that will drive later equipment. The forecast foresees the Japan market will shrink through 2017. This article provides insight behind those forecast numbers.

Overview

Large-scale investments in 300mm wafer lines in Japan are primarily made by three companies: Toshiba (NAND Flash), Sony (image sensors) and Micron Memory Japan (DRAM). The logic players’ investments are largely for upgrading and expanding existing capacity; the companies producing power, surface acoustic wave (SAW), and automotive semiconductor devices are actively adding capacity by constructing new fabs and expanding existing fabs. These activities are planned on 200mm or smaller wafers, so the investments are smaller in terms of dollar values. However, they are important to Japan’s semiconductor industry in the coming Internet of Things (IoT) age.

Toshiba plans a new mega fab

Toshiba continues to expanding its 300 mm NAND fabs in Yokkaichi in 2015 and 2016 ─ including the second phase construction of Fab 5, new Fab 2 for 3D NAND flash memory production, and plan for a new fab (Fab 6).

Toshiba New Fab 2

Toshiba’s new Fab 2 cleanroom (Source: Toshiba)

The new Fab 6 will be dedicated to 3D NAND flash memory production, and is planned to be built in an adjacent area of the current Yokkaichi factory site. Detailed plans of the construction (such as construction period, production capacity, and investment to manufacturing instrument used) will be decided in FY 2016 based on market trends. Fab 6 is expected to be built in FY 2017. Production capacity of the fab is projected to be more than 200,000 wafers per month (300mm wafers) at full capacity.

Toshiba and Western Digital announced a plan in July 2016 to invest a total of 1.5 trillion JPY for the next three years in Yokkaichi operations. This investment will be for the construction of the new fab as well as for updating equipment for existing fabs such as new Fab 2 and Fab 5.

Sony expands 300mm capacity

Sony is also actively expanding its 300mm wafer fabs for increased production of complementary metal-oxide-semiconductor (CMOS) image sensors. Sony plans to expand production capacity not only with its existing lines but also to acquire fabs from other companies. Specifically, Sony acquired Tsuruoka factory in Yamagata prefecture in 2014 from Renesas Electronics Corporation, and it is now operated as Yamagata Technology Center (TEC) of Sony Semiconductor Manufacturing Corporation, which is a semiconductor production subsidiary of Sony Corporation. In 2015, Sony acquired the 300mm line of the Toshiba Oita factory, for production of CMOS image sensors.

Sony plans to invest 70 billion JPY in FY 2016, and expand image sensor production capacity ─ now 70,000 wafers per month as of first quarter of 2016. The restoration of Kumamoto TEC damaged by the Kumamoto earthquake would make investment in other TECs decrease.

Micron and TowerJazz

Micron Technology operates a 300mm fab in Hiroshima (Micron Memory Japan Fab 15). The fab manufactures DRAM with 12nm process technology. Micron invested US$750 million in 2015 and $500 million in 2016 for the technology upgrades. The capacity has been flat in these two years.

Panasonic TowerJazz Semiconductor, a Panasonic and TowerJazz joint venture, operates a 300mm foundry fab in Uozu. The company invested $10 million in 2015 and plans to invest the same amount in 2016 to improve the productivity.

Investments in 200mm and smaller wafer lines

Other major semiconductor manufacturers primarily invest in existing fabs and lines for maintenances and productivity improvements. Therefore, investment amount is modest. However, these fabs will be the major source for semiconductor devices of the Internet of Things applications.

  • Renesas Electronics Corporation plans upkeep of production capacity of Kumamoto fab (200mm wafer fab) and Naka fab (300mm wafer fab).
  • Fujitsu enhances Fab B2 of Mie Fujitsu Semiconductor Limited, which provides foundry services with 300mm wafer lines. Taiwan’s major foundry UMC participated in capital of Mie Fujitsu Semiconductor Limited, and assists with 40nm process technology.
  • Rohm Co., Ltd. plans to invest more than 10 billion JPY in enhancement of 200mm lines of fab and others in the headquarters.
  • Fuji Electric Co., Ltd. continues enhancement of its 200mm wafer lines for IGBT of Yamanashi plant in FY 2016. Fuji Electric further expands its SiC power device production capacity by enhancing 200mm wafer lines at Matsumoto fab.
  • Mitsubishi Electric Corporation manufactures power devices at 200mm wafer line of Kumamoto fab. Mitsubishi Electric continues enhancement of power device production capacity.
  • Shindengen Electric Manufacturing Co., Ltd. is enhancing its power semiconductor module production by adding a new line each for Akita Shindengen Co., Ltd. and Higashine Shindengen Co., Ltd. from FY 2015.

Electronic Parts and Optoelectronic Devices

The electronic parts companies are emerging as new fab owners in Japan. Their recent activities are summarized below:

  • New Japan Radio Co., Ltd. continues enhancement of production capacity of SAW devices and GaAs ICs at its Kawagoe fab in 2016.
  • Hamamatsu Photonics K.K. continues enhancement of MEMS fabrication facility (Fab 13) which started operation in March 2014.
  • Upkeep of new clean room of Toyota Motor Corporation, which started operation in 2014, is now underway. Currently, this line is used for research and development, and trial production of SiC devices.
  • Murata Manufacturing Company, Ltd. is building a new fab for SAW filter production at its headquarter factory in Toyama. The new fab construction will be completed in September 2016. Total investment to the facility is planned to be 12 billion JPY. Then it will be equipped with 200 mm (mostly secondary) equipment.
  • Taiyo Yuden Co., Ltd. continues its enhancement plan of Oume fab in FY 2016, which was acquired from Hitachi in 2013 for SAW device production.
  • TDK agreed to acquire 125mm wafer lines in Tsuruoka Factory from Renesas Electronics Corporation in November 2015. TDK plans to enhance its production capacity of super miniature electronic components at this plant. Production will start in FY 2016 after replacement of manufacturing equipment to conform to products to be manufactured. Investment will continue in FY 2016 as well for startup of the mass production and maintenance at this plant.

SEMI World Fab Forecast

To obtain line-by-line investment and capacity trends in Japan and other regions in the world, SEMI Fab Forecast is a powerful and affordable tool. The report is in easy to use, with Excel spreadsheet format that covers six quarters of actual data and six quarters of forecast on over 1,000 fab/lines. For further information, please see www.semi.org/en/MarketInfo/FabDatabase.

Connect with Japan Semiconductor Industry at SEMICON Japan
SEMICON Japan (December 14-16, Tokyo) offers excellent opportunities to interact and connect with the Japan semiconductor industry. To join the exhibition, please see www.semiconjapan.org/en/exhibit.

SJ Semiconductor Corp. (SJSemi) and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated (NASDAQ:  QCOM), jointly announced that SJSemi has begun mass production of 14nm wafer bumping for Qualcomm Technologies. In the wake of 28nm wafer bumping mass production, and with further improvement of its processing techniques and capabilities, SJSemi has become China’s first semiconductor company to enter the industrial chain with 14nm advanced process node mass production. Mass production of the 14nm wafer bumping in China is part of Qualcomm Technologies’ efforts to continuously drive the development of the Chinese integrated circuit industry, and it further reinforces Qualcomm Technologies’ commitment to China through industrial chain optimization, localized services, and superior offers to Chinese customers.

Founded in August 2014, SJSemi is a joint venture between Semiconductor Manufacturing International Corp. (SMIC) and Jiangsu Changjiang Electronics Technology Co., Ltd (JCET). In December 2015, Qualcomm Global Trading Pte Ltd., a subsidiary of Qualcomm Incorporated, participated in an additional investment in SJSemi. SJSemi realized mass production of the 28nm wafer bumping in early 2016, within two years of its inception, and it now ships 12-inch wafers in high volume every month. SJSemi has sharpened its unique competitive edge in 28nm bumping technology by achieving not only a first-class yield rate but also industry-leading key technical indicators such as contact resistance control over high-density copper pillar bumping. SJSemi will continue to expand the capacity of its 12-inch wafer bumping line, securing the supply chain for its customers. Currently, SJSemi has reached the production capacity of bumping 20,000 12-inch wafers per month.

“We are grateful to Qualcomm Technologies for its consistent support. With its assistance, we have managed to set up an advanced 12-inch bumping line with stable and efficient production to offer mass production services to our customers,” said Mr. Dong Cui, Chief Executive Officer of SJSemi. “The mass production of our 14nm wafer bumping technology is in recognition of our capabilities and strengths, and indicates our ability to offer comprehensive services to first-class global customers like Qualcomm Technologies. We expect to continuously keep pace with customer demand, further improve our technical capability, enrich our process methods, and boost our added value to the industrial chain.”

“The 14nm bumping production from SJSemi is very important to Qualcomm Technologies and has begun mass production, which demonstrates SJSemi’s world-class manufacturing capabilities in leading-edge bumping process technology,” said Dr. Roawen Chen, Senior Vice President, QCT global operations, Qualcomm Technologies, Inc. “We are pleased to work with SJSemi to expand our semiconductor supply chain footprint in China, which further shows our commitment to support China’s local IC manufacturing and better serve our Chinese customers.”

Over the past 20 years, China has become increasingly frustrated over the gap between its IC imports and indigenous IC production (Figure 1).  It has oftentimes been quoted over the last couple of years that China’s imports of semiconductors exceeds that of oil.

In its upcoming Mid-Year Update to The McClean Report 2016 (released at the end of this week), IC Insights examines the “Three-Phase” history of China’s attempt at strengthening its position in the IC industry that started in earnest in the late 1990s (Figure 2).

Figure 1

Figure 1

Figure 2

Figure 2

In the late 1990s, China began to contemplate ways to grow its indigenous IC industry and assisted in creating Hua Hong NEC, which was founded in 1997 as a joint venture between Shanghai Hua Hong and Japan-based NEC (it merged with Grace in 2011).  Then, as part of the country’s 10th Five Year Plan (2000-2005), establishing a strong China-based IC foundry industry became a priority.  As a result, pure play foundries SMIC and Grace (now Hua Hong Semiconductor) were both founded in 2000 and XMC was founded in 2006.  This effort is categorized by IC Insights as Phase 1 of China’s IC industry strategy.

In the early 2000s, to help boost the sales of its indigenous foundries, as well as ride the strong wave of fabless IC supplier growth, the Chinese government began attempts to foster a positive environment for the creation of Chinese fabless companies. It should be noted that eight of the current top 10 Chinese fabless IC suppliers were started between 2001 and 2004 and seven of them were in the top 50 worldwide ranking of fabless IC companies last year. This stage of China’s IC industry strategy is labeled by IC Insights as Phase 2.

IC Insights believes that Phase 3 of China’s attempt at creating a strong China-based IC industry began in 2014, just before the start of its 13th Five Year Plan which runs from 2015 through 2020.  As discussed in detail in the Mid-Year Update, this Phase is being supported by a huge “war chest” of cash that is intended to be used to purchase IC companies and their associated intellectual property, provide additional funding to China’s existing IC producers (e.g., SMIC, Grace, XMC, etc.), and to help establish new IC producers (e.g., Sino King Technology, Fujian Jin Hua, etc.).

In 1Q16, the U.S. Department of Commerce slapped an export ban on U.S. IC suppliers’ shipments of ICs to China-based telecom giant ZTE in response to the company allegedly shipping telecommunications equipment to Iran while it was under trade sanctions by the U.S. This ban, if fully enacted, would have a devastating effect on ZTE’s telecom equipment sales (including mobile phones). Thus far, the export ban has been postponed until August 30, 2016 pending further investigation by the U.S. Department of Commerce.

The situation regarding ZTE and the abrupt announcement earlier this year of export controls on the company by the U.S. government sent shock waves throughout the Chinese government as well as China’s electronic system manufacturers.  At this point in time, such potentially drastic measures taken by the U.S. government against such a large Chinese electronics company has bolstered the Chinese government’s resolve to make China more self-sufficient regarding IC component production, spurring increased emphasis on “Phase Three.”

Worldwide silicon wafer area shipments increased during the second quarter 2016 when compared to first quarter 2016 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,706 million square inches during the most recent quarter, a 6.6 percent increase from the 2,538 million square inches shipped during the previous quarter. New quarterly total area shipments are 0.1 percent higher than second quarter 2015 shipments and are at their highest recorded quarterly level.

“Silicon shipment growth continues to gain momentum resulting in a quarterly volume shipment high,” said Dr. Volker Braetsch, chairman SEMI SMG and senior vice president of Siltronic AG. “Although year-to-date shipments are effectively flat relative to the same period as last year.”

Silicon* Area Shipment Trends

Millions of Square Inches

2Q2015

1Q2016

2Q2016

1H2015

1H2016
Total

2,702

2,538

2,706

5,339

5,243

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

Smaller and faster has been the trend for electronic devices since the inception of the computer chip, but flat transistors have gotten about as small as physically possible. For researchers pushing for even faster speeds and higher performance, the only way to go is up.

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

University of Illinois researchers have developed a way to etch very tall, narrow finFETs, a type of transistor that forms a tall semiconductor “fin” for the current to travel over. The etching technique addresses many problems in trying to create 3-D devices, typically done now by stacking layers or carving out structures from a thicker semiconductor wafer.

“We are exploring the electronic device roadmap beyond silicon,” said Xiuling Li, a U. of I. professor of electrical and computer engineering and the leader of the study. “With this technology, we are pushing the limit of the vertical space, so we can put more transistors on a chip and get faster speeds. We are making the structures very tall and smooth, with aspect ratios that are impossible for other existing methods to reach, and using a material with better performance than silicon.”

The team published the results in the journal Electron Device Letters.

Typically, finFETs are made by bombarding a semiconductor wafer with beams of high-energy ions. This technique has a number of challenges, Li said. For one, the sides of the fins are sloped instead of straight up and down, making them look more like tiny mountain ranges than fins. This shape means that only the tops of the fins can perform reliably. But an even bigger problem for high-performance applications is how the ion beam damages the surface of the semiconductor, which can lead to current leakage.

The Illinois technique, called metal-assisted chemical etching or MacEtch, is a liquid-based method, which is simpler and lower-cost than using ion beams, Li said. A metal template is applied to the surface, then a chemical bath etches away the areas around the template, leaving the sides of the fins vertical and smooth.

“We use a MacEtch technique that gives a much higher aspect ratio, and the sidewalls are nearly 90 degrees, so we can use the whole volume as the conducting channel,” said graduate student Yi Song, the first author of the paper. “One very tall fin channel can achieve the same conduction as several short fin channels, so we save a lot of area by improving the aspect ratio.”

The smoothness of the sides is important, since the semiconductor fins must be overlaid with insulators and metals that touch the tiny wires that interconnect the transistors on a chip. To have consistently high performance, the interface between the semiconductor and the insulator needs to be smooth and even, Song said.

Right now, the researchers use the compound semiconductor indium phosphide with gold as the metal template. However, they are working to develop a MacEtch method that does not use gold, which is incompatible with silicon.

“Compound semiconductors are the future beyond silicon, but silicon is still the industry standard. So it is important to make it compatible with silicon and existing manufacturing processes,” Li said.

The researchers said the MacEtch technique could apply to many types of devices or applications that use 3-D semiconductor structures, such as computing memory, batteries, solar cells and LEDs.

Peregrine Semiconductor Corp. today announced the promotion of Takaki Murata to vice president and general manager of the high performance analog (HPA) business unit.

“Peregrine Semiconductor was acquired by Murata in December of 2014, and they have proven to be a powerful and supportive parent company,” says Jim Cable, CEO of Peregrine Semiconductor. “Takaki has been preparing for this promotion for the last year and a half, as he served on the executive staff of our HPA business. The timing of this promotion reflects the success of our integration and the logical next step to further our assimilation into the Murata family of companies.”

A long-time veteran of Murata, Takaki has a Ph.D. in electrical engineering and 12 years of experience at Murata, in a range of different assignments including: LTCC material development, SAW filter development, antenna sales engineering, RF front-end sales engineering, corporate accounting and inductor business strategic planning. Most recently, Takaki served as the vice president of business development inside HPA. He has been in that role since early 2015.

“I am so impressed with the quality of engineering talent here at the HPA business unit of Peregrine,” says Takaki Murata, now vice president and general manager of the Peregrine HPA business unit. “When you add that talented pool of engineers to the uniqueness of the Peregrine UltraCMOS® platform and recent advances in the power management market to the wide support of an industry giant, like Murata, you have an unstoppable force. I look forward to facilitating many more successful collaborations in the very near future.”

“Murata is looking to Peregrine to provide semiconductor innovation to be applied to the Murata advantage in our growth markets of power, automotive, healthcare and 5G,” says Norio Nakajima, EVP communication and sensor business unit, and energy business group of Murata Manufacturing Co. “We have heavily invested in Peregrine because we see their technological advantage as critical to many of our new and growth initiatives. We believe that Takaki is ideally suited to his new position because of his technological expertise and his deep and long history with Murata Manufacturing.”

Since the purchase by Murata in December 2014, Peregrine Semiconductor has increased their employee base by 40 percent. Jim Cable adds, “The continued investment in Peregrine by Murata is an indicator of the significance that it places on our technology and innovation.”

The HPA business unit of Peregrine Semiconductor serves more than over 4,000 global customers in end markets ranging from wireless infrastructure and wired broadband to test & measurement (T&M), automotive and aerospace. Most recently, it launched its first product into the power/energy marketplace.  Products include RF switches, digital step attenuators (DSAs), digitally tunable capacitors (DTCs), tuning control switches, power limiters, phase-locked loops (PLLs), mixers, prescalers, DC-DC converters, monolithic phase and amplitude controllers (MPACs) and the fastest GaN FET driver available today.

Worldwide semiconductor capital spending is projected to decline 0.7 percent in 2016, to $64.3 billion, according to Gartner, Inc. (see Table 1). This is up from the estimated 2 percent decline in Gartner’s previous quarterly forecast.

“Economic instability, inventory excess, weak demand for PC’s, tablets, and mobile products in the past three years has caused slow growth for the semiconductor industry. This slowdown in electronic product demand has driven semiconductor device manufacturers to be conservative in increasing production,” said David Christensen, senior research analyst at Gartner. “Looking ahead, it appears the second half of 2016 may see improved demand. However, following Brexit, semiconductor inventory levels may rise in the third and fourth quarters, which could lead to reduced production volumes.”

Table 1

Worldwide Semiconductor Capital Spending and Equipment Spending Forecast, 2015-2018 (Millions of Dollars)

2015

2016

2017

2018

Semiconductor Capital Spending ($M)

64,750.8

64,278.3

66,010.5

68,523.7

Growth (%)

0.3

-0.7

2.7

3.8

Wafer-Level Manufacturing Equipment ($M)

33,248.1

32,890.9

34,842.2

37,704.3

Growth (%)

-1.1

-1.1

5.9

8.2

Wafer Fab Equipment ($M)

31,485.4

31,071.8

32,862.1

35,491.5

Growth (%)

-1.3

-1.3

5.8

8.0

Wafer-Level Packaging and Assembly Equipment ($M)

1,762.7

1,819.1

1,980.1

2,212.9

Growth (%)

4.1

3.2

8.9

11.8

Source: Gartner (July 2016)

The PC, ultramobile (tablet) and smartphone production forecast for the second half of 2016 has been lowered from 2015, as the industry slowdown continues. These reductions have resulted in a forecasted 3 percent decline for the semiconductor market. Memory revenue growth for 2016 is also revised downward compared with the previous forecast, due to a weaker pricing outlook.

“While currency exchange rates are another reason for the ongoing revenue decrease, the aggressive pursuit of semiconductor manufacturing capability by the Chinese government and related investment companies is becoming a major factor,” said Mr. Christensen. “This will dramatically affect the competitive landscape of the global semiconductor manufacturing in the next few years as China becomes a major market for semiconductor usage and manufacturing.”

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends. Additional analysis on the outlook for the market can be found at “Forecast: Semiconductor Capital Spending, Worldwide, 2Q16 Update.”

North America-based manufacturers of semiconductor equipment posted $1.71 billion in orders worldwide in June 2016 (three-month average basis) and a book-to-bill ratio of 1.00, according to the June Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.00 means that $100 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in June 2016 was $1.71 billion. The bookings figure is 2.1 percent lower than the final May 2016 level of $1.75 billion, and is 12.9 percent higher than the June 2015 order level of $1.52 billion.

The three-month average of worldwide billings in June 2016 was $1.71 billion. The billings figure is 7.0 percent higher than the final May 2016 level of $1.60 billion, and is 10.2 percent higher than the June 2015 billings level of $1.55 billion.

“Although order activity slowed for the most recent month,” said Denny McGuirk, president and CEO of SEMI. “Billings activity for equipment companies based in North America are at their highest level since February 2011.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
January 2016

$1,221.2

$1,310.9

1.07
February 2016

$1,204.4

$1,262.0

1.05
March 2016

$1,197.6

$1,379.2

1.15
April 2016

$1,460.2

$1,595.4

1.09
May 2016 (final)

$1,601.5

$1,750.5

1.09
June 2016 (prelim)

$1,714.0

$1,713.2

1.00

Source: SEMI (www.semi.org), July 2016

For more than six decades, the annual IEEE International Electron Devices Meeting (IEDM) has been the world’s largest and most influential forum for technologists to unveil breakthroughs in transistors and related micro/nanoelectronics devices.

That tradition continues this year with a few new twists, including a supplier exhibition and a later paper-submission deadline (August 10) of a final, four-page paper. Accepted papers will appear in the proceedings without any changes. This streamlined process will ensure that even as the pace of innovation in electronics quickens, IEDM remains the place to learn about the latest and most important developments.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016, beginning with a weekend program of 90-minute tutorials and all-day Short Courses taught by industry leaders and world experts in their respective technical disciplines. These weekend events will precede a technical program of some 220 papers and a rich offering of other events including thought-provoking plenary talks, spirited evening panels, special focus sessions on topics of great interest, IEEE awards and an event for entrepreneurs sponsored by IEDM and IEEE Women in Engineering.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair, Intel Fellow, and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group.

Tibor Grasser, IEDM 2016 Exhibits Chair, IEEE Fellow and Head of the Institute for Microelectronics at TU Wien, added, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

Here are some of the noteworthy events that will take place at this year’s IEDM:

Special Focus Sessions

  • Wearable Electronics and Internet of Things
  • Quantum Computing
  • System-Level Impact of Power Devices
  • Ultra-High-Speed Electronics

90-Minute Tutorials – Saturday, Dec. 3

A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research. Advance registration is recommended.

  • The Struggle to Keep Scaling BEOL, and What We Can Do Next, Rod Augur, Distinguished Member of the Technical Staff, GLOBALFOUNDRIES
  • Electronic Circuits and Architectures for Neuromorphic Computing Platforms, Giacomo Indiveri, Univ. of Zurich and ETH Zurich
  • Physical Characterization of Advanced Devices, Robert Wallace, Univ. Texas at Dallas
  • Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Ben Kaczer, Principal Scientist, imec
  • Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications, Bernard Dieny, Chief Scientist, Spintec CEA
  • Technologies for IoT and Wearable Applications, Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories, Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Short Courses – Sunday, Dec. 4

The Short Courses provide the opportunity to learn about important areas and developments, and to benefit from direct contact with world experts. Advance registration is recommended.

  • Technology Options at the 5-Nanometer Node, organized by An Steegen and Dan Mocuta of imec (Sr. Vice President of Technology Development/Director of Logic Device and Integration, respectively)
  • Design/Technology Enablers for Computing Applications, organized by John Chen, Vice President of Technology and Foundry Management, NVIDIA

Plenary Presentations – Monday, Dec. 5

  • Memory Scaling – Challenges and Opportunities, Seok-Hee Lee, Executive Vice President and Head of DRAM Product and Technology, Hynix
  • Brain-Inspired Computing, Dharmendra S. Modha, IBM Fellow and Chief Scientist for Brain-Inspired Computing, IBM
  • Differentiating Technologies and Novel Opportunities for the Future Internet of Everything: the Quest for Power Efficiency, Marie-Noëlle Semeria, CEO, Leti

Evening Panel Session – Tuesday evening, Dec. 6

The IEDM offers attendees two evening sessions where experts give their views on important industry topics. Audience participation is encouraged to foster an open and vigorous exchange of ideas.

  • How Will the Semiconductor Industry Change to Enable 50 Billion Connected Devices? Moderator: Prof. Aaron Thean, University of Singapore
  • Challenges and Opportunities for Neuromorphic and Machine Learning, Moderator: Marc Duranton, Sr. Member of the Embedded Computing Lab, CEA

Entrepreneurs Lunch – Wednesday, Dec. 7

Jointly sponsored by IEDM and IEEE Women in Engineering, the Entrepreneurs Lunch will feature Vamsee Pamula, co-founder of Baebies, Inc. a company developing digital microfluidics technology for newborn screening and pediatric testing. Pamula co-founded Baebies in 2014, following the sale of a predecessor microfluidics company that he also co-founded – Advanced Liquid Logic – to Illumina, Inc.

Vamsee has years of experience with digital microfluidics. He has served as Principal Investigator on several National Institutes of Health-funded projects, and has led many talks and published more than 60 articles, five book chapters and a book on the topic. He has more than 200 issued and pending patents, a PhD in Electrical and Computer Engineering from Duke University, and also serves as Adjunct Professor there.

Late-News Deadline

A very limited number of Late News Papers will be accepted, focusing on very recent developments, with a submission deadline of September 12. The submission format is the same as for regular papers.

Further information about IEDM

For registration and other information, visit www.ieee-iedm.org.

The Semiconductor Industry Association (SIA) announced the release of the 2015 International Technology Roadmap for Semiconductors (ITRS), a collaborative report that surveys the technological challenges and opportunities for the semiconductor industry through 2030. The ITRS seeks to identify future technical obstacles and shortfalls, so the industry and research community can collaborate effectively to overcome them and build the next generation of semiconductors – the enabling technology of modern electronics. The current report marks the final installment of the ITRS.

“For a quarter-century, the Roadmap has been an important guidepost for evaluating and advancing semiconductor innovation,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The latest and final installment provides key findings about the future of semiconductor technology and serves as a useful bridge to the next wave of semiconductor research initiatives.”

Faced with ever-evolving research needs and technology challenges, industry leaders have decided to conclude the ITRS and transition to new ways to advance semiconductor research and bring about the next generation of semiconductor innovations. While the final ITRS report charts a path for existing technology research, additional research is needed as we transition to an even more connected world, enabled by innovations like the Internet of Things. Some of these technology challenges were outlined in a recent SIA-Semiconductor Research Corporation (SRC) report, “Rebooting the IT Revolution,” but work continues to define research gaps and implement new research programs.

The ITRS is sponsored by five regions of the world – Europe, Japan, Korea, Taiwan, and the United States. Through the cooperative efforts of the global chip manufacturers and equipment suppliers, research communities and consortia, the ITRS has identified critical gaps, technical needs, and potential solutions related to semiconductor technology.

“SIA appreciates the hard work, dedication, and expertise of those involved with the ITRS over the years and looks forward to continuing the industry’s work to strengthen semiconductor research and maintain the pipeline of semiconductor innovations that fuel the digital economy,” Neuffer said.