Category Archives: Wafer Processing

Silicon Valley specialty semiconductor foundry Noel Technologies, a provider of process development and substrate fabrication for a variety of high-technology industries, celebrates its 20th anniversary this month. According to market data from the industry trade association SEMI, Noel Technologies is one of only two companies still offering foundry services in Silicon Valley, where there were once dozens of wafer-fabrication facilities.

Using industry-standard process flows and materials, Noel Technologies develops and perfects semiconductor-manufacturing recipes for customers in the IC, renewable energy, automotive electronics, LED lighting, optoelectronics, MEMS and other nanoelectronics industries. The foundry can work with traditional silicon wafers up to 450mm as well as non-standard substrates including III-V compound materials, glass and fused silica.

The company provides chip makers with a bridge from IC development work to volume production, a much-needed service in proving the viability of new devices and innovative manufacturing processes. The multi-billion-dollar cost of building today’s wafer fabs has led many semiconductor companies to adopt a “fabless” strategy by outsourcing chip manufacturing to a foundry, many of which are located in Asia.

“While other companies have moved their fabrication operations out of Silicon Valley – whether in pursuit of lower labor costs, tax holidays or other financial incentives – we are dedicated to working with local and far-off semiconductor companies on their prototyping, pilot manufacturing and production needs,” said Leon Pearce, founder and chief technical officer of Noel Technologies.

To deliver short cycle times and maximize the utility of its installed equipment base, Noel Technologies operates seven days a week, 20 hours per day. Projects vary in size from single wafers to thousands per month, depending upon each customer’s unique needs.

Pearce and his daughter Kristin Boyce, president of Noel Technologies, co-founded the company in 1996 with three employees. Through strategic technology additions, tool acquisitions and facility expansions, they have grown the staff to 50 personnel. Hill joined the company 12 years ago, leveraging her extensive semiconductor experience to expand Noel Technologies’ foundry services and better serve its broad customer base. Together, the three senior executives focus on customer needs, emerging market requirements and new applications.

The company continues to operate at its original location and has no corporate debt, both extreme rarities in the semiconductor industry. Noel Technologies owns and operates a Class 100 cleanroom facility equipped with tools that support its process-driven services model and run by a well-trained engineering department.

This article was originally posted on SemiMD.com and was featured in the July 2016 issue of Solid State Technology.

By Ed Korczynski, Sr. Technical Editor

Applied Materials has disclosed commercial availability of new Selectra(TM) selective etch twin-chamber hardware for the company’s high-volume manufacturing (HVM) Producer® platform. Using standard fluorine and chlorine gases already used in traditional Reactive Ion Etch (RIE) chambers, this new tool provides atomic-level precision in the selective removal of materials in 3D devices structures increasingly used for the most advanced silicon ICs. The tool is already in use at three customer fabs for finFET logic HVM, and at two memory fab customers, with a total of >350 chambers planned to have been shipped to many customers by the end of 2016.

Figure 1 shows a simplified cross-sectional schematic of the Selectra chamber, where the dashed white line indicates some manner of screening functionality so that “Ions are blocked, chemistry passes through” according to the company. In an exclusive interview with Solid State Technology, company representative refused to disclose any hardware details. “We are using typical chemistries that are used in the industry,” explained Ajay Bhatnagar, managing director of Selective Removal Products for Applied Materials. “If there are specific new applications needed than we can use new chemistry. We have a lot of IP on how we filter ions and how we allow radicals to combine on the wafer to create selectivity.”

From first principles we can assume that the ion filtering is accomplished with some manner of electrically-grounded metal screen. This etch technology accomplishes similar process results to Atomic Layer Etch (ALE) systems sold by Lam, while avoiding the need for specialized self-limiting chemistries and the accompanying chamber throughput reductions associated with pulse-purge process recipes.

“What we are doing is being able to control the amount of radicals coming to the wafer surface and controlling the removal rates very uniformly across the wafer surface,” asserted Bhatnagar. “If you have this level of atomic control then you don’t need the self-limiting capability. Most of our customers are controlling process with time, so we don’t need to use self-limiting chemistry.” Applied Materials claims that this allows the Selectra tool to have higher relative productivity compared to an ALE tool.

Due to the intrinsic 2D resolutions limits of optical lithography, leading IC fabs now use multi-patterning (MP) litho flows where sacrificial thin-films must be removed to create the final desired layout. Due to litho limits and CMOS device scaling limits, 2D logic transistors are being replaced by 3D finFETs and eventually Gate-All-Around (GAA) horizontal nanowires (NW). Due to dielectric leakage at the atomic scale, 2D NAND memory is being replaced by 3D-NAND stacks. All of these advanced IC fab processes require the removal of atomic-scale materials with extreme selectivity to remaining materials, so the Selectra chamber is expected to be a future work-horse for the industry.

When the industry moves to GAA-NW transistors, alternating layers of Si and SiGe will be grown on the wafer surface, 2D patterned into fins, and then the sacrificial SiGe must be selectively etched to form 3D arrays of NW. Figure 2 shows the SiGe etched from alternating Si/SiGe stacks using a Selectra tool, with sharp Si corners after etch indicating excellent selectivity.

“One of the fundamental differences between this system and old downstream plasma ashers, is that it was designed to provide extreme selectivity to different materials,” said Matt Cogorno, global product manager of Selective Removal Products for Applied Materials. “With this system we can provide silicon to titanium-nitride selectivity at 5000:1, or silicon to silicon-nitride selectivity at 2000:1. This is accomplished with the unique hardware architecture in the chamber combined with how we mix the chemistries. Also, there is no polymer formation in the etch process, so after etching there are no additional processing issues with the need for ashing and/or a wet-etch step to remove polymers.”

Systems can also be used to provide dry cleaning and surface-preparation due to the extreme selectivity and damage-free material removal.  “You can control the removal rates,” explained Cogorno. “You don’t have ions on the wafer, but you can modulate the number of radicals coming down.” For HVM of ICs with atomic-scale device structures, this new tool can widen process windows and reduce costs compared to both dry RIE and wet etching.

—E.K.

By Pete Singer, Editor-in-Chief

Fan-out wafer level packaging (FOWLP) is gaining traction, leading to higher I/Os and larger formats, and new mobile displays are pushing the limits of pixel per inch (PPI) while also moving to larger formats. Both trends are driving new requirements for lithography equipment, including steppers, track systems and photoresists. Both packages and displays are employing new types of materials and thinner substrates as well. “There’s a lot of commonality between the advanced display technologies and packaging technologies,” said Rich Rogoff, vice president and general manager of Rudolph’s Lithography Systems Group. “The step-and-repeat system approach is ideally suited to address those challenges.”

Key lithographic challenges of advanced packaging and displays are shown in Figure 1.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Rogoff said another big challenge is the ability to manage what he calls dimensionally unstable material. “These are materials that change with time, with temperature, with humidity and with process steps, every time they come back through a lithography step they can change form. Steppers have to be able to deal with that,” he said.

Rogoff also said he’s seeing changes in imaging chemistries which are creating another challenges. “We’re doing things now from broadband resist to i-line resist, from thin-films to thick films, to dry films to organic chemistries. It’s all over the field here with respect to what types of chemistries are being used to image, and the challenge is of course when going from a thick material to a thin material and varied compositions, you get a much different kind of imaging characteristic. Really you need to be able to manage all of those without having to change your lithography system,” he said.

In packaging applications, large topography is yet another challenge. In a fan-out type of situation, there can be significant differences in heights between the substrate and the die, for example. “You’re having to image through, in some cases, >20 microns of photoresist for a two or three micron line, and that becomes a very big challenge,” Rogoff said. “The package size and the display sizes are also getting bigger, and so you need to try to get as much as you can into one imaging field. The lenses need to have a very large field of view.”

FOWLP, where individual die are connected on redistribution layer, is expected to lead to a major change in process equipment. Today, die are “reconstituted” on a wafer. In the future, as volume increases, a move to high density panels is expected. “As the demand goes up, certainly panels make the most sense,” Rogoff said.

Earlier this year, Rudolph announced that a leading outsourced assembly and test facility (OSAT) has placed an order for the JetStep Lithography System for the semiconductor advanced packaging industry’s first panel manufacturing line. “That’s the first true panel fan-out application that’s moving forward, especially in the OSAT world,” Rogoff said.

While the stepper part of the litho equation is ready for “panelization,” the rest of the industry infrastructure is working from two directions. One, from printed-circuit board type solutions where thick resist are dry films. The other, from the display side, uses thin chemical resists. “Somehow we have to bridge the gap between a thin film and a thick film,” Rogoff said. “These are some of the infrastructure things that are still being worked out, but I think those are relatively easy to solve.”

Elvino da Silveira, Rudolph’s vice president of marketing, said he’s seen some recent changes. “Last year, when we were talking to the various customer and partners that we interact with in terms of the panel level fan out, everybody was really focused on doing reconstituted panels, the face-down type chips. Basically taking the EWLB process and scaling it up to the panel level. As time has gone on, and with TSMC bringing out InFO and so forth, there have been several players that are more open to doing this on a carrier. It adds some costs, but at least based on the general feedback we’ve gotten from some of the industry , scaling up to the larger substrate offsets the additional cost of the carrier,” he said.

Figure 2 (presented at SEMI’s Industry Strategy Symposium in January by Babak Sabi, corporate vice president, director, assembly and test technology department, Intel Corp.) shows the expected progression of packaging technology as IO density increases. Flip chip, ball grid array on the left (the orange box) has 15-60 micron feature sizes depending on the layer and the type of feature being exposed.

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

The next generation, (the yellow box) indicates fan out packaging. “We’re still more towards that boundary between the orange and the yellow, because really no one’s producing sub-five microns in HVM today. Most of it is between 5 and 10,” da Silveira said.

The next level (the green box) indicates embedded technology, such as Intel’s Embedded Multi-die Interconnect Bridge (EMIB). Instead of using a large silicon interposer typically found in other 2.5D approaches, EMIB uses a very small bridge die, with multiple routing layers. Here, the IOs are getting much higher, and the feature sizes are getting pushed toward two microns. As technology moves from the yellow box to the green box, expect a switch from wafers to panels.

9:00 am – 10:00 am
“CONNECT” Executive Summit
SEMI’s Denny McGuirk moderates a panel of execs from Lam, Qualcomm, Intel and Entegris
Keynote Stage

9:00 am – 3:00 pm
Women in Technology Forum
Room 304, Esplanade

12:30 am –2:00 pm
The Business Case for Supplier Diversity: Why it Matters to You
Intel presentation and panel discussion
Rm 308, Esplanade

1:00 pm – 5:00 pm
From Collision to Convergence: Co-creating Soutions in the Semiconductor and MEMS/Sensors Industries
San Francisco Marriott Marquis

2:00 pm – 4:00 pm
World of IoT Innovation
Innovation and IoT Theater

3:00 pm –4:30 pm
Bulls & Bears Panel
W Hotel

200mm fabs reawakening


July 13, 2016

By David Lammers, Contributing Editor

Buoyed by strong investments in China, 200mm wafer production is seeing a re-awakening, with overall 200mm capacity expected to match its previous 2006 peak level by 2019 (Figure 1).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Speaking at a SEMI/Gartner market symposium at SEMICON West, SEMI senior analyst Christian Dieseldorff said over the next few years “we don’t see 200mm fabs closing, in fact we see new ones beginning operation. To me, that is just amazing.”

The numbers back up the rebound. Excluding LEDs, the installed capacity of 200mm fabs will reach about 5.3 million wafers per month (wspm) in 2018, almost matching the 2007 peak of 5.6 million wspm. As shown in Figure 1, By 2019 as new 200mm fabs start up in China, 200mm wafer production will surge beyond the previous 2007 peak, a surprising achievement for a wafer generation that began more than 25 years ago. Figure 2 shows how capacity, which held steady for years, is now on the increase.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Case in point: On the opening day of Semicon West, Beijing Yangdong Micro announced a new OLED 200mm fab that will be opening in the second half of 2018 to make OLED drivers, according to Dieseldorff.

Over the past few years, Japan-based companies have closed 10 200mm fabs, mostly outdated logic facilities, while expanding production of discrete power and analog ICs on 200mm wafers. But with China opening several new 200mm fabs and the expansions of existing 200mm fabs worldwide, SEMI sees an additional 274,000 wafer starts per month of 200mm production over the 2015-2018 period, adding expansions and additional fabs, and subtracting closed facilities.

“One message from our research is that we believe the existing 200mm fabs are full. Companies have done what they can to expand and move tools around, and that is coming to an end,” he said. SEMI reckons that 19 new 200mm fabs have been built since 2010, at least six of them in China.

SEMI’s Christian Dieseldorff.

SEMI’s Christian Dieseldorff.

Dieseldorff touched on a vexing challenge to the 200mm expansion: the availability of 200mm equipment. “People have problems getting 200mm equipment, used and even new. The (200mm) market is not well understood by some companies,” he said. With a shortage of used 200mm equipment likely to continue, the major equipment companies are building new 200mm tools, part of what Dieseldorff described as an “awakening” of 200mm manufacturing.

 

China is serious

Sam Wang, a research vice president at Gartner who focuses on the foundry sector, voiced several concerns related to 200mm production at the SEMI/Gartner symposium. While SMIC (which has a mix of 200mm and 300mm fabs) has seen consistently healthy annual growth, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

The challenge, he said, is for China’s foundries which rely largely on legacy production to grow revenues in a competitive market. And things are not getting any easier. While production of has shown overall strength in units, Wang cautioned that price pressures are growing for many of the ICs made on 200mm wafers. Fingerprint sensor ICs, for example, have dropped in price by 30 percent recently. Moreover, “the installation of legacy nodes in 300mm fabs by large foundries has caused concern to foundries who depend solely on 200 mm.”

But Wang emphasized China’s determination to expand its semiconductor production. “China is really serious. Believe it,” he said.

New markets, new demand

The smart phone revolution has energized 200mm production, adding to a growing appetite for MEMS sensors, analog, and power ICs. Going forward, the Internet of Things, new medical devices, and flexible and wearable products may drive new demand, speakers said at the symposium.

Jason Marsh, director of technology for the government and industry-backed NextFlex R&D alliance based in San Jose, Calif., said many companies see “real potential” in making products which have “an unobtrusive form factor that doesn’t alter the physical environment.” He cited one application: a monitoring device worn by hospital patients that would reduce the occurrence of bed sores. These types of devices can be made with “comparatively yesteryear (semiconductor) technology” but require new packaging and system-level expertise.

Legacy devices made on 200mm wafers could get a boost from the increasing ability to combine several chips made with different technologies into fan out chip scale packages (FO CSPs). Bill Chen, a senior advisor at ASE Group, showed several examples of FO CSPs which combine legacy ICs with processors made on leading-edge nodes. “When we started this wafer-level development around 2000 we thought it would be a niche. But now about 30 percent of the ICs used in smart phones are in wafer-level CSPs. It just took a lot of time for the market forces to come along.”

More coverage from this year’s SEMICON West can be found here.

By Shannon Davis, Web Editor

“There’s never been a better time to connect” was the theme of John Kern’s keynote address at SEMICON West 2016 Tuesday morning, though it was clear from his speech that connecting – or digitizing – supply chains is not just a good idea, but imperative in the current ever-changing climate of the electronics supply chain.

John Kern, Vice President of Supply Chains, Cisco Systems, speaking at SEMICON West 2016 on Tuesday morning. (Source: SEMI)

John Kern, Senior Vice President of Supply Chains, Cisco Systems, speaking at SEMICON West 2016 on Tuesday morning. (Source: SEMI)

“If you’re not investing in digitization today, it’s going to be very, very difficult for you to remain relevant over the next decade,” Kern urged his audience.

Kern, who is Senior Vice President of Supply Chains at Cisco Systems, came equipped with several compelling case studies from his team’s own experiments, to make the case for why connecting the supply chain is so vital to innovation and profitability.

The first case study that Kern presented showed Cisco’s results from monitoring energy and energy costs in a factory setting. His team deployed a network of thousands of sensors that monitored energy readings of every piece of equipment in one of Cisco’s Malaysian factories, so teams could gather data and analytics on each piece’s performance. This initiative allowed the factory team to make changes in equipment to optimize performance, which resulted in a 12% energy reduction and a 1 million USD cost savings, which amounted to a full return on investment achieved in less than 10 months.

Kern also envisions a path to tens of millions of dollars in capital savings each year with adaptive testing, an initiative that’s currently saving Cisco test engineers man hours and allowing them to return to high value work. Kern said that Cisco was able to leverage analytics capabilities of a software they owned called Auto Test, along with Cisco’s own 10-15 years of test information, to build a test system that is now capable of machine-to-machine learning.

“The tests are becoming adaptive; they’re changing themselves,” said Kern, “and they’re notifying the engineers when they’re making a change.”

In addition to the cost and time savings, Kern believes this also allows for engineers to develop higher quality products.

And these products are also reaching the market faster, thanks to a Cloud-based supplier collaboration platform Cisco is using, that is allowing all of their suppliers to see real-time changes in demand and real-time changes in supply response, eliminating the bull-whip effect in the supply chain.

“We’ve also seen substantial improvement in product lead time,” Kern said. “We’re able to solve issues [with our suppliers] in a much faster way.”

Ultimately, this is where Kern says Cisco and its supply chain is headed: to what he calls supply chain orchestration.

“We’re trying to move this from a big IT project to having literally hundreds of people in our supply chain that are equipped to change the nature of their work every day,” he said. “If they understand the technology, they’re empowered to change the nature of their work.”

“This is the path for breakthrough productivity,” he concluded. “If you’re not investing heavily in these concepts today, it will be hard for you to stay relevant in the next decade.”

Semiconductor manufacturers and their suppliers – both process tool vendors and providers of sub-fab systems – are looking to an open industrial networking methodology, EtherCAT, developed by Beckhoff Automation (Verl, Germany; m.beckhoff.com) to address the increasingly stringent control requirements of emerging high-precision processes.

During SEMICON West, early adopters are promoting EtherCAT as a next-generation real-time Ethernet control solution, with a variety of attributes: it is fast (good for controlling ever-more precise process recipes), open, and extendable to many more nodes than existing networking protocols. Those attributes make EtherCAT attractive to tool makers such as Applied Materials, Lam Research, and Tokyo Electron Ltd., as well as sub-systems suppliers such as Edwards (Crawley, England).

Fab managers increasingly are looking ahead to the availability of predictive maintenance and other data-based productivity approaches, all of which require fast, extendable networks.

EtherCAT is fast enough for near real-time control. Andrew Chambers, a product manager at Edwards, gave the example of a process recipe that requires a change in gas flow, resulting in a deviation in chamber pressure. To maintain good process control the pressure controller must respond to the change in flow as quickly as possible in order not to lose time as the process chamber conditions stabilize. The EtherCAT control architecture can enable the change in flow, and pre-emptively adjust the pressure control, in real time, using a central controller over the EtherCAT network, rather than relying on the devices responding individually to changes in circumstances.

Increasingly, shrinking device geometries and the trend towards “atomic-scale engineering” are putting pressure on the process tools to control all process parameters with high precision in real time. EtherCAT supporters argue that with very short cycle times and response rates, real-time process control becomes realizable, overcoming the problems that arise from serial control and looped-in control, which can introduce delays in the system.

Edwards’ Gerald Shelley said as tool vendors seek to improve processes, they may need to reduce individual process steps to less than one second. That in turn requires a fast network to enable parameter changes at a correspondingly high rate.

Beckhoff Automation developed EtherCAT based on a specific functional principle, they describe it as “processing on the fly,” which supports very short cycle times. EtherCAT’s rapid response times have therefore proved attractive to semiconductor process tool developers, Shelley said.

Flexibility, another key virtue, allows EtherCAT to support more than 65,000 nodes on a network. “It’s extendable. It can be reconfigured. And there is an emerging option where the network itself can provide power to the devices attached to the network, which reduces the cabling requirements to the system,” Chambers said. Pre-existing, conventional fieldbus networks can be added to the EtherCAT network as additional nodes. “If you’ve got a pre-existing system that you want to integrate into something new that has an EtherCAT network, then you can do that,” he also noted.

As an open protocol network, any party can use EtherCAT, which is described in international standards.

“It has the benefit that it doesn’t need any particularly special infrastructure components to make it run. There’s not a special master device. The devices themselves can incorporate the EtherCAT protocol. You can simply plug a device into the network and have it run. That makes it relatively easy to use,” Shelley added.

Toolmakers, such Applied Materials, Lam Research and Tokyo Electron Ltd., currently use a wide variety of tool control systems on their diverse product ranges. EtherCAT is seen as a route towards a common, adaptable control architecture that could support a diversity of process tools on a common platform.

Beckhoff Automation, with about 3,000 employees worldwide, has worked with its business partners to set up the EtherCAT Technology Group to further develop EtherCAT. The technology group currently has 3,810 members, up from just 300 in 2006.

“There will be open standards so that they’re available to all interested parties, but in particular the profiles of the devices which can be added to any EtherCAT network, the profiles which control how devices respond and communicate with a network, are being generated and developed by the supplier working groups, of which Edwards is a member. We, along with a wide range of other sub-system suppliers are developing devices to meet the requirements for installation in EtherCAT networks, to be able to provide the functions and features that are needed by the semiconductor industry,” Shelley said.

In the future, process tool manufacturers will be able to select from a range of devices with similar functionality which will fit on the same network, so it reduces the dependency of toolmakers on specific individual suppliers. This enables process tool makers to develop advanced bespoke control algorithms and address emerging process challenges.

“From a total process control perspective, our view is that as high volume manufacturing moves towards smaller and smaller nodes, introduction of those processes is going to depend on a complete sub-fab process solution per process tool. These solutions will be based on some kind of integrated best-known method that describes how you set up the sub-fab equipment to deliver what the process vendor needs,” Chambers added.

Predictive maintenance, Intelligent devices

Next-generation sub-fab systems will require the ability to analyze data gathered within the system, or within the submodules within the system. The system will be comprised of intelligent devices, all generating data. “The question that we all have to address is how do you turn huge amounts of data into useful information. We believe that the manufacturer of the sub-fab equipment is well placed to turn raw data into useful information, which then can be relayed to the process tool,” Chambers said.

Relaying that information to the process tool is where the EtherCAT network plays an important role. “The sub-fab equipment could be hooked up to the process tool control network as a node on the EtherCAT network, despite the fact that what’s going on within the integrated sub-fab system doesn’t depend on EtherCAT for its functionality,” he said.

The process tool and the sub-fab equipment are able to exchange operational data or information in real time over an EtherCAT network. “That means if things are happening in the process tool that would benefit from a change in what’s happening in the sub-fab, then that data can be shared, and the sub-fab equipment can adapt itself to whatever the process tool is doing at that specific time, with the result that new and more efficient modes of operation are possible across the tool” he added.

“The equipment in the sub-fab will be generating vast amounts of data. Our intent is that the sub-fab equipment itself processes the data to turn it into information, and the kinds of information that we’re talking about is working up predictive maintenance algorithms so you can effectively predict when, for example, a dry pump or abatement system is going to need service attention, with sufficient advance notice that it can be scheduled into the process tools job schedule,” he said.

“The key point is neither a process toolmaker nor a sub-fab equipment supplier is able to do this in isolation. The whole thing becomes an iterative partnership between the tool operator, the OEM, and the sub-fab equipment maker. Going forward, we can see the emergence of process-specific predictive algorithms as a necessary requirement to enable fully cost-effective device manufacturing,” Chambers said.

By Pete Singer, Editor-in-Chief

On Monday, imec – the Leuven Belgium-based research consortium – hosted its annual imec Technology Forum (ITF) USA, a half-day conference at the Marriott Marquis. With the theme ‘Towards the Ultimate System’, imec’s speakers and industrial keynote speakers looked at the co-optimization of design and new technology, and how technology innovation can deliver the right building blocks to build these systems.

Delivering the keynote address at the event was Luc Van den hove, President and CEO of imec. He talked about how the world was in the middle of a decade of digital disruption brought about by integrated circuit innovation. He then provided an outlook of how the industry could continue to stay on the path defined by Moore’s Law by moving to nanowires and the 3rd dimension.

Luc van den hove, president and CEO of imec, tipped his hat to Gordon Moore, showing a short video clip and describing a future where Moore’s Law will live on through 3D integration.

Luc van den hove, president and CEO of imec, tipped his hat to Gordon Moore, showing a short video clip and describing a future where Moore’s Law will live on through 3D integration.

Van den hove noted what he said were obvious example of disruption today: Uber, the world’s largest taxi company that doesn’t own any taxis. Airbnb, the world’s largest accommodation provider that doesn’t own any real estate. Facebook, the world’s largest media provider, that doesn’t generate any media content.

“These are just a few examples, but we will see this kind of disruption everywhere, in every market and every segment,” he said. “Companies will have to adapt. They will have to reposition themselves in the value chain and come up with new business models. This is just the beginning.”

What’s made this disruption possible is IC technology and ubiquitous mobile computing. What’s been particularly beneficial over the last 50 years is that, in addition to the increased functionality that comes with scaling, there were advantages of faster operation at lower power. “This combination of effects that occurs simultaneously with scaling has resulted in the phenomenal evolution,” he said.
After a short video clip of Gordon Moore talking about the benefits of microprocessors, Van den hove give a realistic view of the future.

“Today, there is a lot of debate about the continuity of Moore’s Law. Yes, we’re faced with several tradeoffs. It’s getting harder and harder (to scale) and when we scale down our transistors we do not automatically the performance improvement that we used to with previous generations,” he said. “But we are sure there are sufficient solutions out there that will allow us to continue Moore’s legacy for several more decades. I am convinced that scaling will not only continue, it has to continue. If you want to enable the IoT wave, we will have to succeed in extending Moore’s law to generate the required compute power and storage capacity.”

Van den hove added that Moore’s Law is on the verge of morphing. “We will need other techniques in order to realize this complexity increase,” he said. “We will continue 2D scaling. It will evolve from the FinFET that is in mass production today towards horizontal nanowires, towards most likely vertical nanowires. This will bring us to at least the 3nm generation if not one or two generations more. This will keep us busy for the next 10-15 years.”

He stood by his past comments on the production-worth status of EUV. “To enable this, we will need a cost-effective lithography. We absolutely need EUV lithography to make this happen. I’m sure, based on the progress I’ve seen over the last 12 months, that EUV is ready to enter manufacturing. But we have to be realistic. Eventually, 2D scaling will slow down. I’m not saying it’s going to stop. But it’s getting harder and harder and hence it will require more time to transition from one geometry-based node to the next geometry node. We will need other ways to compensate for this gradual slowdown. One of the obvious ways to do so is to start using more extensively the third dimension, as the memory guys have started to do already,” he said.

Van den hove presented a future where devices are stacked on top of one another like Lego blocks. “Once we are using these vertical nanowires, it’s not so difficult to imagine that we may be stacking those transistors on top of each other – stack an n-FET on top of a p-FET and realize an SRAM cell. It’s obvious that such a 3D version of an SRAM cell has a much smaller footprint than its 2D equivalent. Once we can do that, we can even imagine that we may start stacking some of these building blocks on top of each other,” he said.

“It’s more straightforward to imagine that this can be done with a regular structure such as an SRAM design, but also FPGAs are very regular structures. We can even imagine that we could design random logic and design standard cells within the constraints of such a 3D Lego block and build up a logic circuit with these Lego blocks in a 3D fabric,” he continued.

Heterogeneous integration with photonics is also on the drawing board. “We will combine this also with 3D heterogeneous integration where we will be using chip stacking technology with high bandwidth, high density through silicon vias. We can then combine all these layers with 3D stacking and through-silicon vias, integrate all of this on an interposer, which can also be the substrate to integrate these 3D cubes,” he said. “By adding also photonics on such an interposer, we can also realize optical IOs. This is just another rendition of Moore’s Law which will allow more complexity in a smaller form factor.”

By Ed Korcynzski, Sr. Technical Editor

The near-term outlook for semiconductor manufacturing is challenging, with revenues down slightly but equipment spending up a bit, as reported by experts during the SEMI/Gartner Market Symposium held yesterday afternoon. The global economy is facing extreme uncertainty and is still recovering from the 2008/2009 financial crisis. Duncan Meldrum, Chief Economist with Hilltop Economics, explained why the after-shocks of the 2008/2009 global financial crisis combined with current political uncertainties result in a difficult investment environment. Compared to the 1993-2007 era when world real GDP was +3.2%, there are many indicators that the current ~2.3% GDP growth is the ‘new normal.’

“Rolling recessions in different regions have been pulling down global growth,” explained Meldrum. “Before the financial crisis, all the growth rates tended to be together in a coordinated global market. We’re actually seeing potential growth cut in half compared to what it was before the recession. That will create a new speed limit on the global economy, so it’ll be a tougher world than we’re used to.” These are high level macro-economic global investment numbers, but there’s a high correlation between these numbers and semiconductor industry silicon wafer processing in Millions of Square Inches (MSI).

Capital equipment forecast

Bob Johnson, Gartner research vice president, presented the outlook for semiconductor capital equipment, based on Garner’s economic model assumptions:

  • Consumer demand will remain weak,
  • High inventory of chips in all channels,
  • NAND and DRAM in oversupply for the rest of 2016,
  • Demand weakness continues longer term,
  • No new significant demand driver, and
  • Uncertain global economic climate post-Brexit.

Gartner is not bullish on the Internet-of-Things (IoT) to provide a next wave of demand. Premium smart-phones are expected to soon saturate global markets, and PC markets see weak consumer demand. In emerging markets, smartphones will take the majority of disposable income, which lowers new PC and tablet purchases by 10% through 2020.

NAND Flash is the long-term bright spot in the industry, with most of the growth driven by solid-state drives (SSD). However short-term oversupply in the second-half of 2016 is expected due to weak end markets, and increased output of planar 3bit/cell products. 3D-NAND represents 19% of the PetaBytes (PB) of total demand in 2016, increasing dramatically to 70% by 2020. SSDs are not just for PCs and mobile devices, but are moving into the enterprise segment and data centers, and 84% of SSDS will use 3D-NAND by 2020.

“3D-NAND manufacturing represents a major shift from litho-centric to etch-centric processing,” reminded Johnson. “The cost structures is still not competitive with 2D-NAND, but there will still be ~300k wafer-starts-per-month in the fourths quarter of 2016. By 2018, 3D-NAND will be half of the total NAND bits produced.” In response to 3D-NAND competition, 2D-NAND suppliers will likely do another shrink using their fully depreciated fabs, which will contribute to short-term oversupply.

Chinese foundry plans

Sam Wong, Gartner research vice president, discussed challenges of the foundry market related to China’s plans to develop domestic IC fab capability that is globally competitive. “Believe that China is really serious this time, with $140B investment,” said Wong. “The SOC capability of China is world-standard.”

For foundry markets in general, with increases in the number of mask layers with successive nodes the selling prices for finished wafers has to continue increasing. Wafer costs for fabless customers buying from foundries are now <$4K for 28nm-node, and <$7K for 14nm-node. TSMC ramped 14nm in one-half-year, and reports unprecedentedly low defects per mask layer to allow them to produce large Apple chips with high yield.

Packaging trends and china

Jim Walker, Gartner vice president of research, presented on “Semiconductor Packaging: the crucial growth component in China’s electronics supply chain.” IC manufacturing is critical to the economic growth and national security of China, and it is part of the ‘made in China 2015’ plan issued by China’s State Council.

China todays has already invested sufficient resources to now have ~1/3 of the global floor-space in Outsourced Semiconductor Assembly and Test (OSAT) facilities, while the percent of global revenue taken by Chinese companies is still much less. Since China has updated investment plans earlier this year, both South Korea and Taiwan industry organizations issued public statements of the need for strategic counter-investments. The semiconductor industry production in Taiwan represents ~13% of its total GDP, so China’s investment into this market is seen as a major threat.

Applied Micro Circuits Corporation (NASDAQ:AMCC) today announced that it has adopted 7nm process technology from TSMC, a world-leading foundry, to enable AppliedMicro’s silicon products for cloud computing and networking applications.

“We are excited to extend our relationship with TSMC to ultimately bring cutting-edge technology to the cloud computing market,” said Paramesh Gopi, President and CEO of AppliedMicro. “We will work closely with TSMC to ensure our flagship silicon products benefit from their manufacturing excellence that is renowned throughout the industry. Together we will introduce technology to revolutionize the rapidly growing data-center market to deliver an unprecedented bundle of compute and connectivity performance, energy efficiency and bandwidth utilization at a low total cost of ownership.”

“We are pleased to be a part of AppliedMicro’s success,” said Dr. B.J. Woo, TSMC Vice President of Business Development. “TSMC’s advanced 7nm technology will empower AppliedMicro to deliver the critical performance needed in computing and connectivity applications.”

Recently introduced innovations from AppliedMicro include X-Gene 3 at ARM TechCon in November 2015, and single lambda, mixed signal 100G X-Weave PAM4 at the Optical Fiber Communications Conference in March 2016.  Both product functions were validated  with TSMC 16FF+ shuttle and are expected to sample to customers by early 2017.