Category Archives: Wafer Processing

Qualcomm Incorporated announced that it has filed a complaint against Meizu in the Beijing Intellectual Property Court. The complaint requests rulings that the terms of a patent license offered by Qualcomm to Meizu comply with China’s Anti-Monopoly Law, and Qualcomm’s fair, reasonable and non-discriminatory licensing obligations.  The complaint also seeks a ruling that the offered patent license terms should form the basis for a patent license with Meizu for Qualcomm’s fundamental technologies patented in China for use in mobile devices, including those relating to 3G (WCDMA and CDMA2000) and 4G (LTE) wireless communications standards.

Qualcomm has negotiated extensively and in good faith with Meizu to sign a patent license agreement consistent with the terms of the rectification plan submitted by Qualcomm to, and accepted by, China’s National Development and Reform Commission (NDRC) in 2015.  Although Qualcomm would have preferred to reach a resolution with Meizu without the need for litigation, Meizu, unfortunately, has been unwilling to negotiate in good faith and enter into a license agreement on the rectification plan terms while unfairly expanding its business through the use of Qualcomm’s innovations without compensating Qualcomm for the use of Qualcomm’s valuable technologies.  In contrast, more than 100 other companies have already accepted the rectification plan terms, including the largest Chinese mobile device suppliers.

“Qualcomm’s technologies are at the heart of all mobile devices.  Meizu is choosing to use these technologies without a license, which is not only unlawful, but is unfair to other licensees that are acting in good faith and respectful of patent rights, and ultimately damaging to the mobile ecosystem and consumers,” said Don Rosenberg, executive vice president and general counsel of Qualcomm Incorporated. “We are, and have been, a good partner in China, and we are pleased to see how China’s mobile ecosystem is thriving. Chinese smartphone suppliers are succeeding both domestically and globally, and we are pleased to help drive that growth.  Qualcomm looks forward to continuing to increase its level of commitment to, and investment in, China across both the wireless and semiconductor ecosystems.”

By Douglas G. Sutherland and David W. Price

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

In the early stages of development, having more process control can help reduce both the number and duration of cycles-of-learning (the iterations required to solve a particular problem). In high volume manufacturing a well-thought-out process control strategy can increase baseline yield and, at the same time, limit yield loss due to excursions. At all stages, an effective process control strategy is required to ensure that the fab is operating at its lowest possible cost. In addition to minimizing production costs, adding process control steps can, counterintuitively, also minimize cycle time.

Figure 1 shows a conceptual plot of how cycle time would vary as a function of the number of process control steps. On the left hand side of the chart where there are no metrology and inspection (M&I) steps in place, the cycle time is effectively infinite. If a lot reaches the end of the line and has zero yield there is no way to isolate the problem. Theoretically one could isolate the problem by trial and error, but with only 100 process steps and only two parameters each, there would be 2100 (1.3 x 1030) possible combinations. Even testing one parameter per second, it would take much longer than the age of the universe to exhaust all possible combinations of the parameter space.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

As process control steps are added the cycle time comes down from an effectively infinite value to some manageable number. At some point the cycle time will reach a minimum value. Beyond this point, adding in further process control steps will actually cause the cycle time to increase linearly with the number of added steps. The optimal amount of process control will always be a trade-off between minimizing cycle time, minimizing excursion cost, and maximizing baseline yield. The latter two usually have a much greater financial impact.

Adding process control steps can reduce a fab’s cycle time, but how does that work? A full treatment of cycle time (Queuing Theory) is far beyond the scope of this article, however at a high level, it can be broken down into a few manageable components. The total cycle time (CT) is the sum of the queue time (the time a lot spends waiting for a process tool to become available) and the processing time itself. Since the processing time is fixed, the only way to reduce CT is to concentrate on the queue time (Q). From Queueing Theory it can be shown that Q can be expressed by the product of three separate functions4,

Q = f(u) f(a) f(v)                                                                                           eqn 1

where f(u), f(a) and f(v) are, respectively, functions of utilization, availability and variability. The first two functions will always be finite, therefore it becomes clear that Q = 0 only when f(v) = 0. Put another way, reducing variability in the fab reduces the queue time, and if we remove all variability from the system the queue time will drop identically to zero and the CT will be equal to just the processing time.

Figure 2 shows a plot of CT as a function of utilization for three different levels of variability: zero, medium and high. The Y-axis measures cycle time in units of total processing time called the X-factor. When the variability is zero all the lots move through the fab in lock-step; there is no increase in CT with increasing utilization and all tools could be run, theoretically, at 100 percent utilization. In this case the queue time is zero and the CT is equal to the total processing time for all the steps (CT=1). As soon as some variability is introduced, the CT starts to increase exponentially with utilization and the more variability there is, the more dramatic the increase becomes.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Variability in the fab comes from many sources: in the lot arrival rate, in the frequency of maintenance requirements, and in the time required for that maintenance to be performed are just a few of the sources. An excursion—a lot that is out of control—affects all of the above.

Having more process control points will not immediately change the number of excursions in a fab but it will immediately improve the efficiency with which the fab reacts to them.

In fact, over time, having more process control points can also reduce the number of excursions because it increases a fab’s rate of learning.

Consider a lot that has been flagged for having a defect count that was beyond the control limit for process step N. If, as shown in figure 3a, there was another inspection point between process steps N and N-1, then the problem can be immediately isolated. Only the tool at step N (the process tool the offending lot went through) needs to be put down and only the lots that went through that tool since the last good inspection need to be put on hold for disposition.

By contrast, consider what would happen in figure 3b where the last inspection point was five steps ago at process step N-5. Practices differ from fab to fab, however in the worst case scenario, all ten tools that the lot went through would be put down and all lots that went through any of those tools would have to be put on hold. Instead of a minor disruption involving a single process tool and a few lots, entire modules and dozens of lots can be directly affected. Indirectly, it affects the entire fab.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3 shows that implementing fewer inspection steps has a threefold impact on cycle time:

  1. More process tools are involved and must be taken offline
  2. Each process tool is down for a much longer period of time because it takes longer to isolate the problem
  3. More wafers are in the impacted section of the production line. These wafers must be dispositioned

The variability introduced by these three impacts will also propagate through the fab; they constrict the flow of work in progress (WIP) through the fab, creating a WIP bubble that affects the lot arrival rate (increased variability) at every station downstream. All of these factors contribute to fab-wide variability and because of the re-entrant nature of the process flow, they add to the cycle time of every single lot in the fab.

When an excursion occurs, the resulting disruption impacts the cycle time of every lot in the fab and it quickly becomes a vicious cycle. The more excursions that happen during a given lot’s cycle time, the longer that cycle time will be. And the longer the cycle time is, the more likely it is that that lot will be in the fab when the next excursion occurs.

Adding inspection steps will add a small, known amount of cycle time to those lots that get inspected, but due to sampling (not every lot gets inspected) it will have a much smaller impact on the average. When an excursion does occur, comparatively few process tools will have to be put down and the module owner will be able to isolate the problem much sooner. The total disruption to the fab (the variability) will be reduced and the cycle time of all lots will be improved.

This counter-intuitive concept has been borne out by several fabs that have both added inspection steps and reduced cycle time simultaneously. Adding process control steps contributes to fab efficiency on several levels: accelerating R&D and ramp phases, increasing baseline yield, limiting the duration of excursions, and reducing cycle time. In short, a better-controlled process is a more efficient process.

The next article in this series will discuss the impact of process control to cycle time on so-called “hot lots” typically run during early ramp.

References:

  • “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014.
  • “Process Watch: Time is The Enemy of Profitability,” Solid State Technology, May 2015.
  • “Economic Impact of Measurement in the Semiconductor Industry,” Planning Report 07-2, National Institute of Standards and Technology, U.S. Department of Commerce, December 2007.
  • Hopp, W. J., and Spearman, M. L. Factory Physics (2nd). (New York: Irwin, McGraw-Hill, 2001), 325.

About the Authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

According to the latest market research report by Technavio, the global semiconductor capital equipment market is expected to reach $47.34 billion mark by 2020.

In this report, Technavio covers the present scenario and growth prospects of the global semiconductor capital equipment market education market for 2016-2020. To calculate the market size, the report considers the revenue generated from each equipment of the semiconductor production process.

The electrification and automation of automobiles have led to the increasing need for semiconductor wafers. Different types of semiconductor ICs are used in a number of automotive products like navigation control, infotainment systems and collision detection systems. There is also a growing demand for hybrid and electric vehicles (HEVs) with increased environmental awareness and emissions legislations. The demand for driverless and smart cars will generate demand for advanced sensors over the next four years.

“With advances like the emergence of 3D and ultra-high definition (UHD) TVs and hybrid laptops in the consumer electronics sector, the demand for semiconductor ICs will further increase during the forecast period. This rise in demand for semiconductor ICs will, in turn, generate demand for semiconductor devices,” said Asif Gani, one of Technavio’s lead industry analysts for semiconductor equipment.

“Technavio researchers expect the semiconductor market to grow at a CAGR of 6.42% during the forecast period. The increase in sales of microelectronics and consumer electronic devices is anticipated to support the growth of the semiconductor market,” added Asif.

Samco, a Japan-based semiconductor processing equipment manufacturer, held a completion ceremony for its second production center on June 17. The new production center, which began construction in January and is expected to begin operations during the fall of this year, boosts Samco’s original shipment capacity of 6-7 billion yen per year to a total of 10-11 billion yen per year.

“We expect to see an increased demand for dry etching and CVD systems due to the IoT’s rapid expansion, as well as anticipated growth in the medical and robotics industries,” says Osamu Tsuji, Samco’s president, chairman and CEO. “With the completion of our newest production center, Samco is prepared to meet those demands.”

Containing a total land area of 1,260 m2, Samco’s second production center’s total floor space is 1,130 m2 (which includes a 217.61 square-meter clean room), and will mainly be used to assemble and modify processing equipment for mass production. The 600 million yen investment also included renovations for the existing production technology building.

The two-floor steel-framed building stands adjacent to Samco’s headquarters in Kyoto, which has been described as the “Silicon Valley of Japan” due to its abundance of technology-based companies and manufacturers.

“Our second production center serves as a contribution to the local economy and is recognized by Kyoto City’s program to promote the siting of companies within the city,” says Tsuji.

The new production center’s eco-friendly design utilizes LED lighting that employs the latest energy-saving technology, as well as an energy efficient air conditioner and large-scale solar panel that spans across the roof and provides a portion of the building’s electricity (max. 50kW/h). Additionally, the roof is coated with a high-insulation paint.

“At the same time, the building also observes the city’s construction regulations that aim to protect Kyoto’s place as a historical and cultural treasure,” says Tsuji.

FEI announced today the release of three new tools for process control and defect/failure analysis in advanced semiconductor manufacturing. Two of the tools are specifically targeted at the 7nm node, and all are designed to allow manufacturers to address critical production issues with industry-leading time-to-data, throughput and low cost-per-sample.

“Perhaps more than any other industry, time is money in advanced semiconductor manufacturing,” said Rob Krueger, vice president and general manager of FEI’s Semiconductor Business. “The time required to analyze a sample affects the cost-per-sample directly, but even more importantly, the time required to answer critical production questions can reduce losses and increase production of the entire process. These new tools are the first on the market to allow fast, automated analysis of critical structures that are 7nm and smaller, enabling manufacturers to develop and scale new processes faster, and get new products to market sooner and more profitably than their competitors.”

The Helios G4 DualBeam EXL is a flexible, full-wafer, in-lab or in-fab DualBeam (focused ion beam/scanning electron microscope – FIB/SEM) system. In addition to performing the full range of sectioning, imaging and analyzing functions typical of DualBeam applications in semiconductor manufacturing, it is the only commercially-available full-wafer system in the market today capable of preparing transmission electron microscope (TEM) samples as thin as 7nm. The new Phoenix FIB column and monochromated Elstar SEM column deliver more precise milling with less surface damage and higher resolution imaging. Automation greatly reduces the difficulty, while also improving the speed and reproducibility of the sample preparation process.

The Metrios DX TEM incorporates new high-speed X-ray compositional analysis in conjunction with fully-automated workflows to improve defect analysis throughput by up to 50 percent. An automated aberration corrector improves low-voltage operation to minimize beam damage in ultrathin samples without sacrificing imaging resolution. Automated connectivity to upstream preparation tools minimizes operator interaction with the sample and improves data integrity. The Metrios DX is the only commercially-available fully-automated TEM in the market with the resolution required for process control and root cause analysis at the 7nm node.

The ExSolve 2 WTP is a dedicated, automated full-wafer DualBeam TEM sample preparation system capable of creating thin samples for 10nm and 14nm processes. This second generation ExSolve offers a 40 percent improvement in sample thickness, 50 percent better placement accuracy relative to its predecessor, while delivering  25 percent reduction in capex relative semi-automated/manual techniques. Automated sample preparation with ExSolve is two to three times faster than manual or small DualBeam procedures. The new ExSolve also adds semi-automated defect analysis capability for certain surface defects.

Leti, an institute of CEA Tech, is hosting a one-day conference covering “System Reliability & Security in a Connected World” in Lyon, France, on June 23.

Held at the Lyon Congress Center, this Leti Innovation Day event will explore novel, effective ways to ensure security in the emerging new phase of the digital revolution launched by the Internet of Things.

According to Alain Merle, Leti’s strategic marketing manager for security, this rapidly changing digital environment requires new paradigms for reliability, privacy and security in order to ensure a safe ecosystem for both industrials and consumers.  Hacking, data and identity theft, all digital threats to the real world, immediately follow the introduction or expansion of new applications of digital technology. The frontier between physical and digital security has vanished, he said.

“Companies must start implementing IoT security solutions at the start of the production cycle, and every new industrial project should be ruled not only by cost control, performance enhancement and energy savings, but also by security control,” added Lionel Rudant, Leti’s strategic marketing manager for IoT.

Presenters include Leti experts and industry leaders whose companies are collaborating with Leti on new security and reliability solutions for the next phase of the digital revolution. The lineup includes executives from Bureau Veritas, GLOBALFOUNDRIES, Intel, Mentor Graphics, Oberthur Technologies, Safran and STMicroelectronics, who will share their insights on topics such as enabling a connected world, assessing security and reliability, anticipating security challenges and how advanced technologies can strengthen security.

Leti is a world leader in security evaluations through advanced technology, applications and medical platforms prototyping new digital services and driving innovative requirements for integrated system architectures.

Visit Leti Innovation Day for the complete program, list of speakers and registration information.

By Paula Doe, SEMI

The changing market for ICs means the end of business as usual for the greater semiconductor supply chain. Smarter use of data analytics looks like a key strategy to get new products more quickly into high yield production at improved margins.

Emerging IoT market drives change in manufacturing

The emerging IoT market for pervasive intelligence everywhere may be a volume driver for the industry, but it will also put tremendous pressure on prices that drive change in manufacturing. Pressure to keep ASPs of multichip connected devices below $1 to $5 for many IoT low-to-mid end applications, will drive more integration of the value chain, and more varied elements on the die. “The value chain must evolve to be more effective and efficient to meet the price and cost pressures for such IoT products and applications,” suggests Rajeev Rajan, VP of IoT, GLOBALFOUNDRIES, who will speak on the issue in a day-long forum on the future of smart manufacturing in the semiconductor supply chain at SEMICON West 2016 on July 14.

“It also means tighter and more complete integration of features on the die that enable differentiating capabilities at the semiconductor level, and also fewer, smaller devices that reduce the overall Bill of Materials (BOM), and result in more die per wafer.” He notes that at 22nm GLOBALFOUNDRIES is looking to enable an integrated connectivity solution instead of a separate die or external chip. Additional requirements for IoT are considerations for integrating security at the lower semiconductor/hardware layers, along with the typical higher layer middleware and software layers.

This drive for integration will also mean demand for new advanced packaging solutions that deliver smaller, thinner, and simpler form factors. The cost pressure also means than the next nodes will have to offer tangible power/performance/area/cost (PPAC) value, without being too disruptive a transition from the current reference flow. “Getting to volume yields faster will involve getting yield numbers earlier in the process, with increasing proof-points and planning iterations up front with customers, at times tied to specific use-cases and IoT market sub-segments,” he notes.

Rapid development of affordable data tools from other industries may help

Luckily, the wide deployment of affordable sensors and data analysis tools in other industries in other industries is developing solutions that may help the IC sector as well.  “A key trend is the “democratization” – enabling users to do very meaningful learning on data, using statistical techniques, without requiring a Ph.D. in statistics or mathematics,” notes Bill Jacobs, director, Advanced Analytics Product Management, Microsoft Corporation, another speaker in the program. “Rapid growth of statistics-oriented languages like R across industries is making it easier for manufacturers and equipment suppliers to capture, visualize and learn from data, and then build those learnings into dashboards for rapid deployment, or build them directly into automated applications and in some cases, machines themselves.”

Intel has reported using commercially available systems such as Cloudera, Aquafold, and Revolution Analytics (now part of Microsoft) to combine, store, analyze and display results from a wide variety of structured and unstructured manufacturing data. The system has been put to work to determine ball grid placement accuracy from machine learning from automatic comparison of thousands of images to select the any that deviate from the known-good pattern,  far more efficiently than human inspectors, and also to analyze tester parametrics to predict 90% of potential failures of the test interface unit before they happen.

“The IC industry may be ahead in the masses of data it gathers, but other industries are driving the methodology for easy management of the data,” he contends. “There’s a lot that can be leveraged from other industries to improve product quality, supply chain operations, and line up-time in the semiconductor industry.”

Demands for faster development of more complex devices require new approaches

As the cost of developing faster, smaller, lower power components gets ever higher, the dual sourcing strategies of automotive and other big IC users puts even more pressure on device makers to get the product right the first time. “There’s no longer time to learn with iterations to gradually improve the yield over time, now we need to figure out how to do this faster, as well as how to counter higher R&D costs on lower margins,” notes Sia Langrudi, Siemens VP Worldwide Strategy and Business Development,   who will also speak in the program.

The first steps are to recognize the poor visibility and traceability from design to manufacturing, and to put organizational discipline into place to remove barriers between silos. Then a company needs good baseline data, to be able to see improvement when it happens. “It’s rather like being an alcoholic, the first step is to recognize you have a problem,” says Langrudi. “People tell me they already have a quality management system, but they don’t. They have lots of different information systems, and unless they are capturing the information all in one place, the opportunity to use it is not there.”

Other speakers discussing these issues in the Smart Manufacturing Forum at SEMICON West July 14 include Amkor SVP Package Products Robert Lanzone, Applied Materials VP New Markets & Services Chris Moran, Intel VP IoT/GM Industrial Anthony Neal Graves, NextNine US Sales Manager Don Harroll, Optimal+ VP WW Marketing David Park, Qualcomm SVP Engineering Michael Campbell, Rudolph Technologies VP/GM Software Thomas Sonderman, and Samsung Sr Director, Engineering Development, Austin, Ben Eynon.

Learn more about the speakers at the SEMICON West 2016 session “Smart Manufacturing: The Key Opportunities and Challenges of the Next Generation of Manufacturing for the Electronics Value Chain.” To see all sessions in the Extended Supply Chain Forum, click here.

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $25.8 billion for the month of April 2016, a decrease of 1.0 percent from last month’s total of $26.1 billion and 6.2 percent lower than the April 2015 total of $27.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects decreased annual semiconductor sales in 2016, followed by slight market growth in 2017 and 2018.

“Global semiconductor sales decreased marginally in April, continuing a recent trend of market sluggishness driven by soft demand and a range of macroeconomic headwinds,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Despite a cumulative decrease across all product categories, year-to-year sales of microprocessors and analog products increased modestly, perhaps foreshadowing stronger sales ahead. The latest industry forecast suggests global sales may indeed rebound somewhat in the second half of 2016, but still fall short of last year’s total. The global market is projected to grow slightly in 2017 and 2018.”

Regionally, year-to-year sales increased in Japan (2.2 percent) and China (0.3 percent), but decreased in Asia Pacific/All Other (-8.2 percent), Europe (-8.6 percent), and the Americas (-14.8 percent). Compared with last month, sales were up slightly Japan(0.2 percent) and Asia Pacific/All Other (0.1 percent), but down in Europe (-0.8 percent), China (-1.8 percent), and the Americas (-2.2 percent).

Additionally, SIA today endorsed the WSTS Spring 2016 global semiconductor sales forecast, which projects the industry’s worldwide sales will be $327.2 billion in 2016, a 2.4 percent decrease from the 2015 sales total. WSTS projects year-to-year decreases across all regional markets for 2016: Europe (-0.1 percent), Asia Pacific (-1.2 percent), Japan (-1.7 percent), and the Americas (-7.3 percent). On the positive side, WSTS predicts growth in 2016 for several semiconductor product categories, including discretes, analog, and MCU products.

Beyond 2016, the semiconductor market is expected to grow at a modest pace across all regions. WSTS forecasts 2.0 percent growth globally for 2017 ($333.7 billion in total sales) and 2.2 percent growth for 2018 ($340.9 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

April 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

4.89

4.78

-2.2%

Europe

2.66

2.64

-0.8%

Japan

2.59

2.60

0.2%

China

7.93

7.79

-1.8%

Asia Pacific/All Other

8.02

8.03

0.1%

Total

26.09

25.84

-1.0%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.61

4.78

-14.8%

Europe

2.89

2.64

-8.6%

Japan

2.54

2.60

2.2%

China

7.77

7.79

0.3%

Asia Pacific/All Other

8.74

8.03

-8.2%

Total

27.56

25.84

-6.2%

Three-Month-Moving Average Sales

Market

Nov/Dec/Jan

Feb/Mar/Apr

% Change

Americas

5.41

4.78

-11.7%

Europe

2.70

2.64

-2.4%

Japan

2.49

2.60

4.3%

China

8.42

7.79

-7.4%

Asia Pacific/All Other

7.87

8.03

2.0%

Total

26.89

25.84

-3.9%

Media Contact 

By Debra Vogler, SEMI

A forum of industry experts at SEMICON West 2016 will discuss the challenges associated with getting from node 10 — which seems set for HVM — to nodes 7 and 5. Confirmed speakers at the “Node 10 to Node 5 ─ Dealing with the Slower Pace of Traditional Scaling (Track 2)” session on Tuesday, July 12, 2:00pm-4:00pm, are Lode Lauwers (imec), Guy Blalock (IM Flash), Kelvin Low (Samsung), Mike Chudzik (Applied Materials), Kevin Heidrich (Nanometrics), and David Dutton (Silvaco). SEMI interviewed Lauwers and Chudzik to see what challenges they see ahead as the industry progresses from node 7 to node 5.

According to Mike Chudzik, senior director, Cross-Business Unit Modules Team at Applied Materials, “The top tw or three process development challenges facing the industry at node 7 are RC reduction, RC reduction, and RC reduction,” Chudzik told SEMI. “At the 7nm node, parasitic resistance and parasitic capacitance delays are predicted to be greater than the inherent transistor delay.” Among the solutions he cites are new materials such as cobalt for the contact fill, lower-k spacers, and integration solutions, such as air-gap and replacement contact schemes. “While FinFETs are expected to scale to the 7nm node, their days are numbered. If you want to scale to the true historical 0.7X 7nm node, it’s a challenge for FinFETs because continuing to scale the gate length requires scaling the fin width.” He also explained that the variability in patterned fins will cause serious device performance challenges at near 5nm fin width on account of quantum confinement. “Something new like gate-all-around (GAA) devices are needed to fuel the next-generation of device scaling.”

Figure 1: At the 7nm node (CD of 13nm), the resistance of the TiN/W fill materials for the contact plug is expected to become higher than the interfacial contact resistance. SOURCE: Applied Materials

Figure 1: At the 7nm node (CD of 13nm), the resistance of the TiN/W fill materials for the contact plug is expected to become higher than the interfacial contact resistance. SOURCE: Applied Materials

Among the materials challenges in getting to nodes 7 and 5 are cobalt implementation for the contact, and Si/SiGe superlattices for the 5nm node, explained Chudzik. “The former challenge concerns replacing tungsten in the contact plug, and the latter is needed to form horizontal GAA structures.” Figure 1 shows that at the 7nm node (CD of 13nm) the resistance of the TiN/W fill material for the contact plug is expected to become higher than the interfacial contact resistance. “A TiN/Co solution provides relief.”

In addition to improving the performance of the interconnect, Lode Lauwers, VP, business development for CMOS technology at imec, told SEMI that getting to node 7 will require very advanced fin technology combined with a patterning solution. Looking ahead to node 5, he said it is expected that the fin will still be the reference technology, along with the introduction of new materials such as SiGe, and a high concentration of Ge in the channel as a mobility improvement, and possibly even the consideration of III-V materials (particularly at N5) (see Figures 2 and 3).

Figure 2: Performance and energy efficiency roadmap: devices architectures. SOURCE: imec

Figure 2: Performance and energy efficiency roadmap: devices architectures. SOURCE: imec

Figure 3: Performance and energy efficiency roadmap: transistor features that are driving the logic roadmap. SOURCE: imec

Figure 3: Performance and energy efficiency roadmap: transistor features that are driving the logic roadmap. SOURCE: imec

In looking out towards the horizon, Lauwers pointed out that the industry has to consider alternatives to the fin because there is an engineering limit to how small the fin dimensions can be made. “There is the possibility that at node 5 the industry will consider alternatives to the traditional fin, said Lauwers. “For example, the GAA structure (also referred to as a lateral or horizontal nanowire, HGAA) is superior in terms of gate control and will have better leakage control. That means you will be able to have better performance over a lower supply voltage with a lower threshold voltage.”

Beyond HGAA structures, Lauwers observed that the industry could move to a vertical nanowire structure (VGAA). But there are several contenders (see Figure 2). “It’s not up to imec to choose and it’s too early to say what will be the right option,” Lauwers told SEMI. “Maybe for certain applications or a certain technology positioning, a device maker might make a different compromise.”

In addition to imec and Applied Materials, speakers from IM Flash, Nanometrics, Samsung, and Silvaco will present at the “Scaling: Node 10 to Node 5” session of the three-day Advanced Manufacturing Forum (see Schedule-at-a-Glance) at SEMICON West 2016 which takes place July 12-14 in San Francisco, Calif.