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Research included in the April Update to the 2018 edition of IC Insights’ McClean Report shows that the world’s leading semiconductor suppliers significantly increased their marketshare over the past decade. The top-5 semiconductor suppliers accounted for 43% of the world’s semiconductor sales in 2017, an increase of 10 percentage points from 10 years earlier (Figure 1).  In total, the 2017 top-50 suppliers represented 88% of the total $444.7 billion worldwide semiconductor market last year, up 12 percentage points from the 76% share the top 50 companies held in 2007.

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Figure 1

As shown, the top 5, top 10, and top 25 companies’ share of the 2017 worldwide semiconductor market each increased from 10-12 percentage points over the past decade.  With the surge in mergers and acquisitions expected to continue over the next few years (e.g., Qualcomm and NXP), IC Insights believes that consolidation will raise the shares of the top suppliers to even loftier levels.

As shown in Figure 2, Japan’s total presence and influence in the IC marketplace has waned significantly since 1990, with its IC marketshare (not including foundries) residing at only 7% in 2017.  Once-prominent Japanese names missing from the top IC suppliers list are NEC, Hitachi, Mitsubishi, and Matsushita. Competitive pressures from South Korean IC suppliers—especially in the memory market—have certainly played a significant role in changing the look of the IC marketshare figures over the past 27 years. Moreover, depending on the outcome of the sale of Toshiba’s NAND flash division, the Japanese-companies’ share of the IC market could fall even further from its already low level.

Figure 2

Figure 2

With strong competition reducing the number of Japanese IC suppliers, the loss of its vertically integrated businesses, missing out on supplying ICs for several high-volume end-use applications, and its collective shift toward the fab-lite IC business model, Japan has greatly reduced its investment in new semiconductor wafer fabs and equipment.  In fact, Japanese companies accounted for only 5% of total semiconductor industry capital expenditures in 2017 (two points less than the share of the IC market they held last year), a long way from the 51% share of spending they represented in 1990.

Unlike the slow ferroelastic domain switching expected for ceramics, high-speed sub-microsecond ferroelastic domain switching and simultaneous lattice deformation are directly observed for the Pb(Zr0.4Ti0.6)O3 thin films. This exciting finding paves the way for high-frequency ultrafast electromechanical switches and sensors.

Piezo micro electro mechanical systems (piezoMEMS) are miniaturized devices exhibiting piezoelectricity, i.e., the appearance of an electric charge under applied mechanical stress. These devices have many diverse applications in energy harvesters, micropumps, sensors, inkjet printer heads, switches, and so on. In permanently polarized (ferroelectric) materials, ferroelastic domain switching affects the piezoelectric properties significantly, and this behavior can be exploited for piezoMEMS applications.

Pb(Zr1-xTix)O3 (PZT) thin films have excellent piezoelectric and ferroelectric properties; therefore, they are potential candidates for MEMS applications. Under an applied electric field, both lattice elongation and 90° ferroelastic domain switching are observed in tetragonal PZT thin films. In particular, non-180° ferroelastic domain switching has important implications for the future realization of high-performance piezoMEMS devices.

However, before the recent investigation, the speed of this 90° domain switching was unknown. In addition, the relationship between the speeds of the lattice deformation and ferroelastic domain switching had not been determined. To investigate these speeds, the research team led by Hiroshi Funakubo examined the switching behavior of Pb(Zr0.4Ti0.6)O3 thin films under applied rectangular electric field pulses.

To observe the changes in the lattice and the domain structure, time-resolved in situ synchrotron X-ray diffraction was carried out in synchronization with a high-speed pulse generator. These observations were performed at the BL13XU beamline at the SPring-8 synchrotron radiation facility. The electric field pulses were applied to the PZT thin films through Pt top electrodes, which were fabricated on top of the films.

Investigation of the diffraction peaks in the PZT thin films revealed elongation of the surface normal c-axis lattice parameter of the c-domain with a simultaneous decrease in the surface normal a-axis lattice parameter of the a-domain under the applied electric field. The intensities of the diffraction peaks also changed under the electric field. These observations provided direct evidence of 90° domain switching.

To determine the switching speed, the lattice elongation and domain switching behaviors were plotted as functions of time (Figure 1). These plots revealed that these processes were completed within 40 ns and occurred simultaneously in response to the applied electric field. The switching behavior was also shown to be perfectly repeatable.

The (a-f) capacitance, strain, tilting angle, intensity, difference capacitance, and volume fraction of the c domain were measured as functions of time, respectively. The elastic deformation and ferroelastic domain switching were completed within 40 ns. Credit: Scientific Reports

The (a-f) capacitance, strain, tilting angle, intensity, difference capacitance, and volume fraction of the c domain were measured as functions of time, respectively. The elastic deformation and ferroelastic domain switching were completed within 40 ns. Credit: Scientific Reports

The high-speed switching observed in these experiments was limited by the present electrical equipment, but is faster than that reported in previous studies. Further, this high-speed 90° switching is reversible and can be used to enhance the piezoelectric response in piezoMEMS devices by several tens of nanoseconds. Therefore, this finding is of considerable importance for the ongoing development of ultrafast electromechanical switches and sensors.

By Pete Singer, Editor-in-Chief

A new roadmap, the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS), aims to integrate fast optical communication made possible with photonic devices with the digital crunching capabilities of CMOS.

The roadmap, announced publicly for the first time at The ConFab in June, is sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI and the IEEE Electron Devices Society (EDS).

Speaking at The ConFab, Bill Bottoms, chairman and CEO of 3MT Solutions, said there were four significant issues driving change in the electronics industry that in turn drove the need for the new HITRS roadmap: 1) The approaching end of Moore’s Law scaling of CMOS, 2) Migration of data, logic and applications to the Cloud, 3) The rise of the internet of things, and 4) Consumerization of data and data access.

“CMOS scaling is reaching the end of its economic viability and, for several applications, it has already arrived. At the same time, we have migration of data, logic and applications to the cloud. That’s placing enormous pressures on the capacity of the network that can’t be met with what we’re doing today, and we have the rise of the Internet of Things,” he said. The consumerization of data and data access is something that people haven’t focused on at all, he said. “If we are not successful in doing that, the rate of growth and economic viability of our industry is going to be threatened,” Bottoms said.

These four driving forces present requirements that cannot be satisfied through scaling CMOS. “We have to have lower power, lower latency, lower cost with higher performance every time we bring out a new product or it won’t be successful,” Bottoms said. “How do we do that? The only vector that’s available to us today is to bring all of the electronics much closer together and then the distance between those system nodes has to be connected with photonics so that it operates at the speed of light and doesn’t consume much power. The only way to do this is to use heterogeneous integration and to incorporate 3D complex System-in-Package (SiP) architectures.

The HITRS is focused on exactly that, including integrating single-chip and multi­chip packaging (including substrates); integrated photonics, integrated power devices, MEMS, RF and analog mixed signal, and plasmonics. “Plasmonics have the ability to confine photonic energy to a space much smaller than wavelength,” Bottoms said. More information on the HITRS can be found at: http://cpmt.ieee.org/technology/heterogeneous-integration-roadmap.html

Bottoms said much of the technology exists today at the component level, but the challenge lies in integration. He noted today’s capabilities (Figure 1) include Interconnection (flip-chip and wire bond), antenna, molding, SMT (passives, components, connectors), passives/integrated passive devices, wafer pumping/WLP, photonics layer, embedded technology, die/package stacking and mechanical assembly (laser welding, flex bending).

Building blocks for integrated photonics.

Building blocks for integrated photonics.

“We have a large number of components, all of which have been built, proven, characterized and in no case have we yet integrated them all. We’ve integrated more and more of them, and we expect to accelerate that in the next few years,” he said.

He also said that all the components exist to make very complex photonic integrated circuits, including beam splitters, microbumps, photodetectors, optical modulators, optical buses, laser sources, active wavelength locking devices, ring modulators, waveguides, WDM (wavelength division multiplexers) filters and fiber couplers. “They all exist, they all can be built with processes that are available to us in the CMOS fab, but in no place have they been integrated into a single device. Getting that done in an effective way is one of the objectives of the HITRS roadmap,” Bottoms explained.

He also pointed to the potential of new device types (Figure 2) that are coming (or already here), including carbon nanotube memory, MEMS photonic switches, spin torque devices, plasmons in CNT waveguides, GaAs nanowire lasers (grown on silicon with waveguides embedded), and plasmonic emission sources (that employ quantum dots and plasmons).

New device types are coming.

New device types are coming.

The HITRS committee will meet for a workshop at SEMICON West in July.

Nanofluidic channels are useful for many biological and chemical applications, such as DNA sequencing, drug delivery, blood cell sorting and molecular sensing and detection. But in the effort to build a versatile lab-on-a-chip, it has been challenging to develop a wafer-scale nanochannel fabrication process compatible with CMOS technology.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 9-11 in Washington, D.C., IBM researchers will report on a CMOS-compatible 200 mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules.

Through the use of sacrificial XeF2 etching and various UV and e-beam lithography methods, sub-20-nm patterns in silicon were converted into macro-scale fluidic ports, micro-scale fluidic feed channels, and nano-scale channels for DNA imaging. Gradient nanopillars were located in the channels to stretch DNA molecules prior to imaging them. Fluid wasn’t pumped through the channels, but instead was transported by the force of gravity. The researchers say their techniques lead to highly manufacturable structures and can produce chips for a variety of biological applications.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

SEM electron microscope photo of silicon nanochannels.

SEM electron microscope photo of silicon nanochannels.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Wang (14.1) Fig.12 (450x338)

 

An alternative to scaling is to expand vertically, by thinning, stacking and interconnecting ICs, commonly called 3D integration. Chip-to-chip Interconnections are are typically made with through-silicon vias (TSVs), but some TSVs also have major disadvantages, including relatively large dimensions, parasitic capacitances and thermal mismatch issues.

At the upcoming International Electron Devices Meeting (IEDM) in December, researchers from Taiwan’s National Nano Device Laboratories avoided the use of TSVs by fabricating a monolithic sub-50nm 3D chip, which integrates high-speed logic and nonvolatile and SRAM memories. They built it from ultrathin-body MOSFETs isolated by 300-nm-thick interlayer dielectric layers.

To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.

The process flow used to fabricate the 3D IC without TSVs.

The process flow used to fabricate the 3D IC without TSVs.

A TEM electron microscope view of the 3D chip.

A TEM electron microscope view of the 3D chip.

 

Packaging at The ConFab


September 18, 2013

At The ConFab conference in Las Vegas in June, Mike Ma, VP of Corporate R&D at Siliconware (SPIL), announced a new business model for interposer based SiP’s, namely the “turnkey OSAT model.” In his presentation “The expanding Role of OSATS in the Era of System Integration,” Ma looked at the obstacles to 2.5/3D implementation and came up with the conclusion that cost is still a significant deterrent to all segments.

By Dr. Phil Garrou, Contributing Editor

Over the past few years, TSMC has been proposing a turnkey foundry model which has met with significant resistance from their IC customers. Under the foundry turnkey model, the foundry handles all operations including chip fabrication, interposer fabrication, assembly and test. Foundry rivals UMC and GlobalFoundries, have been supporting an OSAT/Foundry collaboration model where the foundries would fabricate the chips with TSV and the OSATs would do assembly of chips and interposers that could come from several different sources.

packaging
FIGURE 1. Amkor’s “possum” stacking technology.

SPIL is the first OSAT to propose this OSAT centric model where the interposer is fabricated by the OSAT who then assembles and tests modules made with chips from multiple sources. The impediment to this route in the past has been the lack of OSAT capability to fabricate the fine pitch interposers which require dual damascene processing capability, which until now was only available in the foundries. This week SPIL announced the equipment for fine pitch interposer capability (>2 layers, 0.4-3µm metal line width and 0.5µm TSV) has been purchased and is in place.

Ma indicates that while the foundries are not happy with this SPIL proposal, their customers, especially their fabless customers have been very supportive. He feels the inherent lower cost structure of OSATS will have a positive impact on the 2.5/3D market which has been somewhat stagnant since the FPGA and memory product announcements in 2010.

Also presenting at The ConFab: Bob Lanzone, Senior VP of Engineering Solutions for Amkor. He, like the other OSATS, sees smartphones and tablets driving the market moving forward.

Amkor’s update on Copper Pillar technology indicates an expected doubling in demand this year and continued expansion into “all flip chip products”. Their “TSV status” takes credit for being the first into production with TSMC and Xilinx.

Looking at the 2.5D TSV and interposer supply chain they see different requirements for high end, mid-range and lower cost products. For high end, such as networking and servers, silicon interposers are needed with < 2µm L/S, 25k μbumps per die. Amkor is engaged with foundries to deliver silicon interposers today.

For mid-range products, such as gaming, graphics, HDTV, and tablets, silicon or Glass interposers are need with < 3µm L/S, < 25ns latency and ~10k μbumps/die. Amkor is not actively pursuing glass interposers yet as the infrastructure is still immature.

For lower cost products, such as lower end tablets and smart phones, silicon, glass or laminate interposers are needed, with < 8um L/S, low resistance and ~2k μbumps per die. Lazone said a cost reduction path must be provided to enable this sector, and they are working with the laminate supply chain to do that. They are targeting 2014 for their “possum” stacking as shown in FIGURE 1. •

It’s apparent that the world’s appetite for electronics has never been greater. That has increasingly taken the form of mobile electronics, including smartphones, tablets and tablets and the new “phablets.” People want to watch movies and live sports on their phones. They want their mobile devices to be “situationally aware” and even capable of monitoring their health through sensors. That drives higher bandwidth (6G is on the drawing board), faster data rates and a demand for reduced power consumption to conserve battery life. At the same time, “big data” and the internet of things (IoT) are here, which drives the demand for server networks and high performance semiconductors, as well as integrated sensors and inventive gadgets such as flexible displays and human biosensor networks.

All of this is pushing the semiconductor manufacturing industry and related industry (MEMS, displays, packaging and integration, batteries, etc.) in new directions. The tradeoffs that chipmakers must manager between power, performance, area and cost/complexity (PPAC) are now driven not by PCs, but by mobile devices.

In a keynote address at Semicon West 2013, Ajit Monacha, CEO of Global Foundries, expanded on his Foundry 2.0 concept, talking about how the requirements of mobile devices were, in fact, changing the entire semiconductor industry. He noted that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

Manocha presented the audience with what he sees as today’s Big Five Challenges: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition. I don’t recall when cost wasn’t an issue, but an audience poll revealed that most people believe economic challenges will be the main factor limiting industry growth, not technical challenges. I agree, but I’m also thinking new applications will emerge particularly in the health field that could push the industry in yet another new direction.

Peter Singer, Editor-in-Chief