Category Archives: LEDs

Due to the growth of the semiconductor business, the wider adoption of Cu pillar solutions and the introduction of Flip Chip technology for LED and CMOS Image Sensors (CIS) applications, the Flip Chip market is expending. Under this context, more and more industrial companies including OSATs, IDMs IC foundries and bumping house undertake in this market.

The “More than Moore” market research and strategy consulting company Yole Développement (Yole) explored this industry and proposes today a detailed technology and market report, entitled “Flip Chip: Technologies & Market Trends”. Yole’s team is daily discussing with the leaders of the Advanced Packaging industry. Based on these interactions, the consulting company highlights the evolution of the technical needs and market trends. These major results make Yole’s analysts to think that full capacity should be reached in 2017.

What are the required investments to support this growth? Are there competitive technologies such as TSMC’s new solution, high-performance integrated fan-out wafer level packaging (InFO-WLP), that could answer the market needs and compete Flip Chip technology?

Under “Flip Chip: Technologies & Market Trends” report, Yole’s advanced packaging team provides an overview of Flip Chip technology and market trends. The company reviews the competitive landscape including player dynamics and key market trends; they also detail the Flip Chip market capacity and wafer forecast. Yole’s report also includes a detailed technology roadmap.

“Based on the discussions we had with the major advanced packaging companies, at Yole, we think that demand for Flip Chip is expected to reach the current maximum capacity in 2017,” said Santosh Kumar, Senior, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole. And he adds: “Therefore, new investment will be needed starting in 2018.”

Since Cu pillar processing can be performed by standard foundries and IDMs, the supply chain may see some slight modification. Yole’s analysts expect higher investment in Cu pillar 12” line wafer bumping lines from wafer foundries such as TSMC and SMIC. This change will affect OSATs’ wafer bumping revenue since foundries will gain market share.

OSATs will maintain their strong position in wafer bumping and assembly thanks to of their huge experience and low cost solutions. Their business model enables them to better control the supply chain, as they provide for the complete set of flip-chip services: package design and qualification, wafer bumping, substrate in-sourcing, assembly and final test.

However, big IDM companies like Intel and Samsung maintain their dominance in terms of wafer bumping capacity.

flip chip bump

“At Yole, we expect that even in 2020 Intel will remain the highest-capacity player in Cu pillar wafer bumping,” commented Thibault Buisson, Technology & Analyst, Advanced Packaging at Yole. Foundries and OSATs are also establishing joint ventures for wafer bumping to provide turnkey solutions to customers from chip fabrication to assembly at competitive cost.

And what about the Chinese companies? Do they have a role to play in the Flip Chip market? Chinese players are significantly increasing their presence in wafer bumping and Flip Chip assembly by mergers and acquisitions. JCET acquired STATS ChipPAC and FCI was acquired by Tianshui Huatian Technology Company.

In that context, Yole’s report, Flip Chip: Technologies & Market Trends report gives insights on the future strategies that players may adopt. A detailed description of this report is available on www.i-micronews.com, advanced packaging reports section.

Today, SEMI announced additional details on the 29th annual SEMICON Korea, with more than 40,000 expected attendees, the largest semiconductor technology event in Korea.  The theme for the January 27 through 29 exhibition at Seoul’s COEX is “Connect to the Future – Markets, Technology, and People.”  SEMICON Korea will feature new innovations, technologies and present the future of semiconductor processing technology. The event will be co-located with LED Korea 2016, the leading exhibition for LED manufacturing.

SEMICON Korea 2016 will feature over 530 leading companies from 20 countries with expectation of a record 1,870 exhibition booths. With 97 presentations on diverse topics for 60 hours, the event offers exceptional opportunities to learn and network. In addition, four industry thought leader keynotes will provide insight into the future of global semiconductor industry (including a keynote that will be announced soon before SEMICON Korea):

  • Dr. Ahmad Bahai, CTO of Texas Instruments
  • Dr. Aart de Geus, chairman and co-CEO of Synopsys: “IoT: from Silicon to Software”
  • Berthold Hellenthal, head of the Audi Progressive Semiconductor Program at Audi: “Inventing the Automotive Future”

The keynotes will be followed by a broad offering of deep programs including the SEMI Technology Symposium where experts in semiconductor manufacturing processes will discuss the latest issues and new technologies. The event also covers advanced lithography, advanced process technology, device technology, plasma science and etching, contamination-free manufacturing and CMP, and advanced packaging technologies.

In addition, forums and seminars cover major issues in the semiconductor market, including System LSI, Metrology and Inspection (MI) and Test. The SEMI Standards Program, which develops the global standards indispensable in the strengthening of international competitiveness, will conduct a strong program. Two other programs are increasingly popular with their exclusive navigation of the semiconductor manufacturing supply chain:  Supplier Search – featuring the world’s leading materials manufacturers, and OEM Supplier Search – which facilitates business cooperation between global suppliers and Korea’s parts manufacturers.  The President Reception is a SEMICON Korea highlight where industry leaders network — bringing together suppliers, customers, and innovation leaders.

For a complete schedule of technical sessions and events, visit http://www.semiconkorea.org/en/attend/program-sessions.

SEMICON Korea 2016 registration (www.semiconkorea.org/en) opens November 16. Complimentary registration includes access to the exhibition area and attendance of the keynote speeches.

Systematic – and predictive – cost reduction in semiconductor equipment manufacturing

BY TOM MARIANO, Foliage, Burlington, MA

After a period of double-digit growth, the semiconductor equipment industry has now stabilized to the point where recent market forecasts are predicting anemic single-digit growth rates. This is driven by total market demand from chipmakers. For example, despite strong growth of 12.9 percent in 2014, Gartner, Inc. projects worldwide semiconductor capital spending to only grow 0.8 percent in 2015, to $65.7 billion. [1] Additionally, this industry has always been subject to volatile demand cycles that are notoriously difficult to predict.

Translation: It’s extremely challenging for today’s semiconductor equipment manufacturers to improve their financial performance. There are fewer and fewer opportunities to grow topline revenue through innovation and new product development. And, after several years of cutting costs on existing products and not realizing enough cost reduction to improve margins, it’s difficult to know how to do it differently.

Yet a viable alternative to improve financial performance does exist: A disciplined, rigorous, and systematic approach to reducing costs that delivers more predictive results.

A systematic approach to cost reduction

Where cutting costs was once perceived as the end result of “desperate times, desperate measures,” many innovators are now using this approach much more proactively. By
meeting the idea of cost reduction head on – as an opportunity, not a last resort – many semiconductor equipment makers are uncovering wasteful, inefficient, and costly processes, often in areas they once overlooked. At this point, you may be thinking, “All of this sounds great, but what is a systematic approach to cost reduction, and how is it different from what I’m doing?”

Remember that many manufacturers (in all industries) tend to have a hard time driving costs down. They may set cost reduction goals and then attempt to achieve them using various ad hoc approaches. But they really need to understand exactly what their true costs are, where they exist, and which areas will improve their margins.

A systematic approach to cost reduction gives them this insight. With improved visibility into the entire organization, various processes, and how they execute, semiconductor equipment manufacturers can’t identify the right places to cut costs and hit their cost savings goals. This is a very detailed and planned approach in which organizations closely examine areas such as cost of goods sold, R&D, and service to make more informed decisions that will position their business for long-term success. This is the value of a systematic approach to cost reduction.

This approach also introduces the element of speed, helping equipment makers realize cost savings much faster than ad hoc cost-cutting initiatives and puts them on a path to achieve more predictive results. Beyond the positive (and more obvious) impact successful cost reduction has on a semiconductor equipment manufacturer’s bottom line, it also provides a number of significant benefits such as improving productivity, freeing up key personnel, and providing needed capital to fuel new growth.

The path to predictive results

Even if the concept of a more strategic approach to cutting costs sounds reasonable, many semiconductor equipment manufacturers struggle with how to begin and where to focus. All to often they resort to making reactive decisions regarding existing products without the necessary data, leading them to ask questions such as, “Should we have an obsolescence plan for this product?” “How much could we save?” and “Will this lead to bigger problems down the road?”

Without understanding where your best opportunities for cost cutting are, it’s a lot larder to predict when, and if, cost reduction goals will be met. A systematic approach to cost reduction includes establishing clear cost targets, communicating them to leadership, and measuring and reporting results along the way.

The first step is to engage with an outside firm that has a singular focus on cost reduction, and one that is clearly separated from day-to-day operations and current organizational dynamics. Such an engagement will yield an actionable list of improvements with specific cost targets, realistic timelines for achieving these goals, and future plans for reinvesting the cost savings.

More specifically, a systematic cost reduction approach will focus on three key areas: material costs, R&D costs, and service costs:

1. Material costs: The bill of materials is one of the most common ways to see all the components needed to produce the end product. But this goes well beyond the pure cost of materials. Research has shown that improving the way these components are managed can affect 80-90% of the product’s total costs.[2]

For semiconductor equipment manufacturers, the cost reduction process should start with the selection of the products or sub-assemblies that have the highest potential for savings. Focus on those products that are still generating significant revenue, but may not be receiving much attention in terms or engineering upgrades and enhancements. Thoroughly examine the bill of materials for these products by addressing materials, design, complexity reduction, the potential to create common assemblies, and more.

Value engineering efforts can simultaneously improve product functionality and performance while reducing bill of material costs. This effort should factor in ways to meet RoHS requirements and when to make end-of-life decisions for various electrical components to improve design efficiency and the effectiveness of the product.

A realistic cost reduction goal can then be created and a resulting value-engineering project can commence, often using low-cost offshore resources to best achieve those savings.

2. R&D costs: Making better decisions related to R&D processes and product development can shave considerable costs. Some areas to focus on include:

• When to officially end of life non-performing products
• When to consolidate products, or possibly even entire R&D departments
• When and how to move sustaining engineering efforts offshore, or to other lower-cost alternatives

The critical next step is to look at all products and all product variations to determine if an official end-of-life program should be employed. These decisions are notoriously hard to make and often require difficult conversations with key customers, but they are necessary nonetheless.

Many semiconductor equipment manufacturers have grown through acquisitions, creating redundant engineering groups that can be eliminated or downsized. Performing an organizational analysis of all R&D activities may uncover opportunities to consolidate and combine functions or create centers of excellence that focus on specific technical areas eliminating redundancies of technical specialty.

3. Service costs: Examine engineering and design processes to find ways to improve performance, reliability, and costs. For example, adding data collection technology or product diagnostics to enhance remote support efforts and predictive maintenance.

Improvement of product reliability is usually a large multiplier when it comes to service and spare parts costs. Collect and analyze field data to find the most significant issues driving service costs and then look to cut where possible.

For example, equipment in the field often does not have the capability to report enough information to effectively identify a problem. Adding increased data logging and communication can be used to clarify machine status and point services in the right direction. Connectivity can also help with remote diagnostics, all of which helps reduce costs, uptime, and customer satisfaction.

Cost Reduction as a Competitive Advantage

Short-term market forecasts will continue to make it challenging for semiconductor equipment manufacturers to deliver improved financial results. Yet the concept of a systematic approach to cost reduction is a proven way for them to proactively cut costs – in the right places – and also make better decisions related to existing products and other business systems and processes.

By taking a disciplined, rigorous, and objective look at any and all parts of their organization, semiconductor equipment makers can capitalize on new opportunities to free valuable resources, improve processes and future technology, and reinvest savings for future growth. For many equipment manufacturers the greatest obstacle to successfully exploiting these opportunities is insufficient experience and expertise with a disciplined and unconventional way of approaching cost reduction projects. A systematic approach to cost reduction will be the key to success for companies looking to improve their competitive advantage.

References

1. Gartner, Inc., “Gartner Says Worldwide Semiconductor Capital Spending to Increase 0.8 Percent in 2015: Conser- vative Investment Strategies Paving the Way to Slower Growth in 2015,” January 13, 2015. http://www.gartner. com/newsroom/id/2961017.

2. Forbes, “Product Lifecycle Management: A New Path to Shareholder Value?” August 5, 2011, http://www. forbes.com/sites/ciocentral/2011/08/05/product-lifecycle- management-a-new-path-to-shareholder-value/.

Sapphire is hard, strong, optically transparent and chemically inert.

BY WINTHROP E. BAYLIES and CHRISTOPHER JL MOORE, BayTech-Resor LLC, Maynard, MA

Have you ever wondered what blue gemstone earrings, an LED lightbulb and an Apple Watch have in common? The answer (at least for this article) is that all depend on sapphire as part of their manufacturing process. In part 1 of the following two part article, we will discuss how sapphire is becoming an important part of the mobile device food chain. Part 2 will concentrate on how sapphire is used in LED production.

Sapphire (chemical composition Al2O3) has a high melting point of 2040°C (3704°F) and is chemically resistant even at high temperatures. It is an anisotropic material meaning that its mechanical/thermal properties depend on the direction of the crystal plane that is cut and polished. An insulator with a 9.2 eV energy gap it is optically transparent. With a hardness of 9 on the Mhos scale, it is almost as hard and strong as diamond (10 Mhos).

To summarize, sapphire has some good points: hard, strong, optically transparent and chemically inert (there is a reason high end watches use sapphire crystals) and some bad points: hard, strong, and chemically inert (which is why sapphire crystals are more expensive than glass). That is, the very properties that make it ideal for applications needing mechanical strength and hardness mean that it is a difficult material to grow, machine and polish.

There are several places where sapphire can be (or is now) used in the manufacture of mobile devices. The most publicity in this area was generated in 2014 with significant speculation in both the trade magazines and newspapers (such as the Wall Street Journal) that the iPhone 6 would be released with a sapphire touch screen or at the very least a sapphire cover glass over the existing touchscreen. Part of this speculation was fueled by the large number (1700 to 2500 depending on source) of sapphire producing furnaces being installed at an Apple facility in Mesa Arizona. However, the sapphire iPhone 6 was not released due in part to the difficulties in growing and processing enough sapphire screens at a reasonable cost to supply the significant number of phones produced. There are now sapphire touch screen phones available from other suppliers and recently, the Apple Watch was released with a sapphire screen. In addition, many fingerprint sensors and camera cover glasses are now produced using sapphire as the cover material.

Requirements for sapphire material is clear (forgive the pun). For screens and cameras, it must be of good optical quality i.e. transmit light well and have low surface roughness. For fingerprint sensors, it needs consistent surface quality and electrical properties.

Production process

FIGURE 1 shows a schematic of the production process for sapphire used in a mobile device screen. The following paragraphs provide more detail on this process [1] as well as a few of problems encountered along the way.

Sapphire Fig 1

The sapphire production process starts when a seed crystal and a mixture of aluminum oxide and crackle (un-crystallized sapphire material) is heated using a specific temperature/time profile, then cooled (this process can take two weeks depending on the amount of sapphire being produced) using a carefully controlled set of time/temperature profiles. When done correctly, the cookie sized seed grows and produces a single-crystal sapphire boule. That at least is the theory. In reality, two weeks is a long time and any number of problems can go wrong during this process including gas bubbles, mechanical faults such as cracks and contamination. Each of these problems can affect the sapphire and its optical/electrical properties. There is a clear correlation between the time taken to grow a boule and the potential quality of the boule produced. Many of the problems encountered in the upscaling of the sapphire production process sprang from trying to grow large boules at high speeds.

It is at the next step in the process where boule size does matter. Typically, the boule will be drilled or cut to produce material near the size needed for the particular application. It makes a significant difference if the material is for a watch crystal (say 1.5 inch diameter ~ 1.7 square inches). Here you can “core-drill” a boule to produce a number of smaller cylinders. For a phone screen/cover plate (at 4 by 6 inch i.e. 24 square inches) a larger portion of the boule is needed for a box shape. The ability to grow large sized boules on a regular basis is not in question; most important is how much of that boule is bubble-, crack- and impurity-free. In some cases the boules are inspected with various metrology techniques to determine which sections of the boule can be used and which cannot. The section of the boules not used is recycled into the original growth process (unless contaminated).

Given the hardness of the sapphire, diamond wire saws or diamond core drills are used for cutting or coring the boules. The yield from any boule is a function of the original boule size, the size of the cores or slabs being produced and the volume of the boule free from imperfections. As was discussed earlier, and is typical of many processes, the larger the size of the piece the lower the yield.

The next step is to take the cylindrical cores (or rectangular slabs) and cut them into appropriate sized pieces. The thickness of the desired part and the amount the producer is willing to invest in high technology solutions determines what is done next. On one end of the technology scale, the parts are cut using a wire saw or an abrasive cutoff saw. On the other end of the scale, you can ion implant the surface to produce a damaged layer at a depth below the surface determined by the original ion energy. If the slab is heated after sufficient implantation is done, a thin sheet will separate from the surface. Both processes result in parts of the approximate size needed for the application; a discussion of the pros and cons of each approach is beyond the scope of this article.

The process after this point depends on the parts’ final application and their manufacturer. Given the difficulty of polishing a material this hard many of the bigger companies have developed proprietary process for grinding or mechanically polishing the sapphire parts to the desired shape and surface roughness/finish. From a mechanical strength standpoint, it is important that there be no significant scratching of the surface or chipping of the edges which could severely limit the mechanical strength of the final piece. From an optical standpoint, it is important to produce a uniform finish so as not to effect the overall appearance of the part. At this stage, the parts are then ground to their final size and any additional shaping of the part including holes/ profiles is done. FIGURE 2 shows a variety of sapphire parts at this stage of the process.

Sapphire Fig 2

In most sapphire part production these parts are next coated with a variety of optical and/or electrical and/ or chemical films again depending on their application. Because of its high index of refraction (1.76) a sapphire screen or watch crystal is highly reflective. For this application, the parts are typically coated with a series of films to produce an anti-reflection coating enhancing final screen readability. For parts that will be touched on a regular basis such as touchscreens or fingerprint sensors coatings, it is important that they be “self-cleaning.” In these cases, hydrophobic and oleophobic coatings are used to make sure your fingerprints are less likely to stay behind after the material has been touched. FIGURE 3 shows a series of parts after the coating and silk screening process. They are now ready for assembly into the mobile device.

Sapphire Fig 3

The use of sapphire in mobile devices is driven by two main concerns. One is that the final screen/sensor be mechanically stronger and harder than most glasses. There are a number of videos [2] available showing cement blocks being dragged over cell phones to show the sapphire screens’ scratchproof capabilities. The second (and not as well known) factor is the significant data showing that touch sensors made using sapphire have better performance characteristics due to its superior electrical properties and electrical uniformity. This allows the development of sensors which have improved performance in the field.

The downside of using sapphire remains its cost. Estimates [3] have reported sapphire costs 2 to 10 times the price of an equivalent glass part. Although these costs are coming down, in price sensitive applications glass continues to dominate at this time and it is expected that only higher end phones will use sapphire screens.

In the second part of this article, we will discuss the importance of sapphire in the LED industry and the difference in process needed for this material.

Additional reading/viewing material

1. http://www.businessinsider.com/how-sapphire- glass-screens-are-made-2014-9
2. Video Aero Gear’s Flight Glass SX Sapphire Crystal vs a Concrete
3. http://seekingalpha.com/article/2230553-ignore- the-sapphire-threat-corning-is-on-a-roll

Security by design


November 13, 2015

Chowdary_Yanamadala-150x150By Chowdary Yanamadala, Senior Vice President of Business Development, ChaoLogix

The advent of Internet-connected devices, the so-called Internet of Things (IoT), offers myriad opportunities and significant risks. The pervasive collection and sharing of data by IoT devices constitutes the core value proposition for most IoT applications. However, it is our collective responsibility, as an industry, to secure the transport and storage of the data. Failing to properly secure the data risks turning the digital threat into a physical threat.  

Properly securing IoT systems requires layering security solutions. Data must be secured at both the network and hardware level. As a hardware example, let’s concentrate, on the embedded security implemented by semiconductor chips.

Authentication and encryption are the two main crypto functions utilized to ensure data security. With the mathematical security of the standardized algorithms (such as AES, ECDSA, SHA512, etc.) is intact, hackers often exploit the implementation defects to compromise the inherent security provided by the algorithms.

One of the most dangerous and immediate threats to data security is a category of attacks called Side Chanel Analysis attacks (SCA). SCA attacks exploit the power consumption signature during the execution of the crypto algorithms. This type of attack is called Differential Power Analysis (DPA). Another potent attack form of SCA is exploiting the Electromagnetic emanations that are occurring during the execution of the crypto algorithm – or Differential Electromagnetic Analysis attacks (DEMA).

Both DPA and DEMA attacks rely on the fact that sensitive data, such as secret keys, leaks via the power signature (or EM signature) during execution of the crypto algorithm.

DPA and DEMA attacks are especially dangerous, not only because of their effectiveness in exploiting security vulnerabilities but also due the low cost of the equipment required for the attack. An attacker can carry out DPA attacks against most security chips using equipment costing less than $2,000.

There are two fundamental ways to solve the threat of DPA and DEMA. One approach is to address the symptoms of the problem. This involves adding significant noise to the power signature in order to obfuscate the sensitive data leakage. This is an effective technique.  However, it is an ad-hoc and temporary measure against a potent threat to data security. Chip manufacturers can also apply this technique as a security patch, or afterthought, once  and architecture work is completed.

Another way (and arguably a much better way) to solve the threat of DPA is to address the problem at the source. The source of the threat derives from the leakage of sensitive data the form of power signature variations. The power signature captured during the crypto execution is dependent on the secret key that is processed during the crypto execution. This makes the power signature indicative of the secret key.

What if we address the problem by minimizing the relation between the power signature and the secret key that is used for crypto computation? Wouldn’t this offer a superior security? Doesn’t addressing the problem at the source provide more fundamental security? And arguably a more permanent security solution?

Data security experts call this Security By Design. It is obvious that solving a problem at the source is a fundamentally better approach than providing symptomatic relief to the problems. This is true in the case of data security as well. In order to achieve the solution (against the threat of DPA and DEMA) at the source, chip designers and architects need to build the security into the architecture.

Security needs to be a deliberate design specification and needs to be worked into the fabric of the design. Encouragingly, more and more chip designers are moving away from addressing security as an afterthought and embracing security by design.

As an industry, we design chips for performance, power, yield and testability. Now it is time to start designing for security. This is especially true for chips used in IoT applications. These chips tend to be small, have limited computational power and under tight cost constraints. It is, therefore, difficult, and in some cases impossible, to apply security patches as an afterthought. The sound approach is to start weaving security into the building blocks of these chips.

In sum, designing security into a chip is as much about methodology as it is about acquiring various technology and tools. As IoT applications expand and the corresponding demand for inherently secure chips grows, getting this methodology right will be a key to successful deployment of secure IoT systems.

Related data security articles: 

Security should not be hard to implement

ChaoLogix introduces ChaoSecure technology to boost semiconductor chip security

From laptops and televisions to smartphones and tablets, semiconductors have made advanced electronics possible. These types of devices are so pervasive, in fact, that Northwestern Engineering’s Matthew Grayson says we are living in the “Semiconductor Age.”

“You have all these great applications like computer chips, lasers, and camera imagers,” said Grayson, associate professor of electrical engineering and computer science in Northwestern’s McCormick School of Engineering. “There are so many applications for semiconductor materials, so it’s important that we can characterize these materials carefully and accurately. Non-uniform semiconductors lead to computer chips that fail, lasers that burn out, and imagers with dark spots.”

Grayson’s research team has created a new mathematical method that has made semiconductor characterization more efficient, more precise, and simpler. By flipping the magnetic field and repeating one measurement, the method can quantify whether or not electrical conductivity is uniform across the entire material – a quality required for high-performance semiconductors.

“Up until now, everyone would take separate pieces of the material, measure each piece, and compare differences to quantify non-uniformity,” Grayson said. “That means you need more time to make several different measurements and extra material dedicated for diagnostics. We have figured out how to measure a single piece of material in a magnetic field while flipping the polarity to deduce the average variation in the density of electrons across the sample.”

Remarkably, the contacts at the edge of the sample reveal information about the variations happening throughout the body of the sample.

Supported by funding from the Air Force’s Office of Scientific Research, Grayson’s research was published on October 28 online in the journal Physical Review Letters. Graduate student Wang Zhou is first author of the paper.

One reason semiconductors have so many applications is because researchers and manufacturers can control their properties. By adding impurities to the material, researchers can modulate the semiconductor’s electrical properties. The trick is making sure that the material is uniformly modulated so that every part of the material performs equally well. Grayson’s technique allows researchers and manufacturers to directly quantify such non-uniformities.

“When people see non-uniform behavior, sometimes they just throw out the material to find a better piece,” Grayson said. “With our information, you can find a piece of the material that’s more uniform and can still be used. Or you can use the information to figure out how to balance out the next sample.”

Grayson’s method can be applied to samples as large as a 12-inch wafer or as small as an exfoliated 10-micron flake, allowing researchers to profile the subtleties in a wide range of semiconductor samples. The method is especially useful for 2-D materials, such as graphene, which are too small for researchers to make several measurements across the surface.

Grayson has filed a patent on the method, and he hopes the new technique will find use in academic laboratories and industry.

“There are companies that mass produce semiconductors and need to know if the material is uniform before they start making individual computer chips,” Grayson said. “Our method will give them better feedback during sample preparation. We believe this is a fundamental breakthrough with broad impact.”

Baltimore, MD — November 11, 2015 — Pixelligent, a leader in high-index advanced materials, today launched a new family of PixClear® materials for display and optical components and films. The PixClear product line is now available in a new solvent system — a low boiling ethyl acetate (ETA) — that delivers the same high performance while easing integration with customer manufacturing processes. Now leading manufacturing companies will have the choice of a standard, high boiling propylene glycol methyl ether acetate (PGMEA) or the low boiling ETA for their testing. These materials are available in both 20 percent and 50 percent loadings for PixClear PG and PixClear PB.

“The launch of our new PixClear ETA materials is a response to customer demand. These low boiling ETA dispersions will result in brighter, clearer devices produced at a lower cost, which directly supports reducing time to innovation for our customers in the display and adhesives space,” said Craig Bandes, President and CEO of Pixelligent. “At Pixelligent, we continue to expand our matrix of high quality, high-index nanomaterials in order to support the growth of our customers.” Matt Healy, Vice President of Product Management adds, “In August, we launched a full OLED materials family, which includes four products for testing internal light extraction structures for OLED lighting. All totaled, we have introduced 12 new products for customer testing in the past three months.”

PixClear zirconia dispersions are now available for order in two solvents, and at two different loadings, to complement the processes used for the production of displays and optical components.

Gartner, Inc. forecasts that 6.4 billion connected things will be in use worldwide in 2016, up 30 percent from 2015, and will reach 20.8 billion by 2020. In 2016, 5.5 million new things will get connected every day.

Gartner estimates that the Internet of Things (IoT) will support total services spending of $235 billion in 2016, up 22 percent from 2015. Services are dominated by the professional category (in which businesses contract with external providers in order to design, install and operate IoT systems), however connectivity services (through communications service providers) and consumer services will grow at a faster pace.

“IoT services are the real driver of value in IoT, and increasing attention is being focused on new services by end-user organizations and vendors,” said Jim Tully, vice president and distinguished analyst at Gartner.

Enterprises to Bolster IoT Revenue

“Aside from connected cars, consumer uses will continue to account for the greatest number of connected things, while enterprise will account for the largest spending,” said Mr. Tully. Gartner estimates that 4 billion connected things will be in use in the consumer sector in 2016, and will reach 13.5 billion in 2020 (see Table 1).

Table 1: Internet of Things Units Installed Base by Category (Millions of Units)

Category 2014 2015 2016 2020
Consumer 2,277 3,023 4,024 13,509
Business: Cross-Industry 632 815 1,092 4,408
Business: Vertical-Specific 898 1,065 1,276 2,880
Grand Total 3,807 4,902 6,392 20,797

Source: Gartner (November 2015)

In terms of hardware spending, consumer applications will amount to $546 billion in 2016, while the use of connected things in the enterprise will drive $868 billion in 2016 (see Table 2).

Table 2: Internet of Things Endpoint Spending by Category (Billions of Dollars)

Category 2014 2015 2016 2020
Consumer 257 416 546 1,534
Business: Cross-Industry 115 155 201 566
Business: Vertical-Specific 567 612 667 911
Grand Total 939 1,183 1,414 3,010

Source: Gartner (November 2015)

In the enterprise, Gartner considers two classes of connected things. The first class consists of generic or cross-industry devices that are used in multiple industries, and vertical-specific devices that are found in particular industries.

Cross-industry devices include connected light bulbs, HVAC and building management systems that are mainly deployed for purposes of cost saving. The second class includes vertical-specific devices, such as specialized equipment used in hospital operating theatres, tracking devices in container ships, and many others.

“Connected things for specialized use are currently the largest category, however, this is quickly changing with the increased use of generic devices. By 2020, cross-industry devices will dominate the number of connected things used in the enterprise,” said Mr. Tully.

 

Cambridge, UK — November 9, 2015 — Xaar plc, a world leader in industrial inkjet technology, and Lawter, along with its parent company Harima Chemicals Group (HCG), announced a collaboration to optimize the performance of a line of nanosilver conductive inks in the Xaar 1002 industrial inkjet printhead. The combined solution will be of particular interest to manufacturers of consumer electronics goods looking for a robust and reliable method for printing antennas and sensors with silver nanoparticle ink as part of their manufacturing processes.

Industrial inkjet offers significant advantages over traditional print technologies to manufacturers of consumer electronics products. Inkjet is a cleaner process than other methods of printing silver inks; this is especially relevant when printing onto a substrate, such as a display, in which any yield loss is very expensive. With inkjet, manufacturers can very precisely control the amount of ink dispensed in certain areas of a pattern so that the ink or fluid deposited can be thicker in some areas and thinner in others. Similarly, inkjet enables the deposition of a much thinner layer of fluids than traditional methods, which is significant for the manufacturers looking to produce thinner devices. In addition, inkjet is one of the few technologies able to print a circuit over a substrate that has a structured surface.

“This is an excellent opportunity to showcase our latest technological breakthroughs and demonstrate the unique value that our revolutionary nanoparticle inkjet solutions can play as part of an integrated system solutions in the PE world,” says Dr. Arturo Horta Ph.D., Business Development Manager for Lawter Innovation Group.

HCG pioneered the development and manufacture of silver nanoparticle conductive inks for the printed electronics industry over 20 years ago and has over 100 patents related to its nanoparticle dispersion technology. This line of nanosilver conductive inks for inkjet printing offers a unique combination of low temperature sintering and high circuit conductivity. In addition, Lawter’s novel inks are compatible with a range of photonic curing tools as well as a variety of substrates.  These value-added features, together for the first time in a single product, provide increased project efficiency, decreased raw material costs and finer line printing.  All of this adds up to significant, quantifiable benefits for the end-user.

Xaar, also a major player in industrial manufacturing applications, has been delivering inkjet technology for 25 years. Its leading printhead, the Xaar 1002 is particularly suitable for Lawter’s nanosilver conductive inks due to the printhead’s unique TF Technology™ (fluid recirculation) which ensures a continuous flow of the heavy particulate in the ink to deliver uninterrupted high volume production printing.

“The applications that will benefit from the combination of Lawter’s nanosilver conductive inks and Xaar’s 1002 printhead are exciting,” says Keith Smith, Director of Advanced Manufacturing at Xaar. “We are seeing more and more that the consumer electronics market is looking for a printing solution that provides the quality of the Lawter ink and production reliability of the Xaar GS6 1002 to allow designers to make thinner devices.  The printhead and ink combination, along with photonic sintering, is unlocking mechanical and electrical designs never thought possible before.”

 

Plasma-Therm announced that it has acquired an innovative High Density Radical Flux plasma technology, which enables low-temperature Bosch polymer removal.

High Density Radical Flux — HDRF® —was developed by Nanoplas France as a superior plasma process for low-temperature removal of photoresists and organic polymer residues. These capabilities are especially important for device fabrication steps in the MEMS, LED, and advanced packaging markets.

Plasma-Therm is integrating HDRF technology into its existing suite of plasma etching, deposition, and wafer-dicing products. The Nanoplas-developed HDRF low-temperature photoresist stripping capability is also applicable to Bosch polymer removal after DRIE processing.

“We are eager to make the HDRF technology available to our existing customers and potential customers,” said Ed Ostan, vice president of marketing for Plasma-Therm. “HDRF fits very well into our etch and deposition product line, because this will allow Plasma-Therm to provide multi-step solutions to specialized device manufacturers for both R&D and production use.”

Plasma-Therm will also offer ongoing support to Nanoplas customers. The Nanoplas installed baseis primarily made up of DSB 6000 and DSB 9000 HDRF systems.

HDRF enables removal of photoresist, as well as organic polymers left on trench sidewalls following DRIE processes. These applications are sought for advanced packaging, MEMS, and power devices.

HDRF systems incorporate a multi-zone, remote, inductively coupled plasma (ICP) source, which produces up to 1,000 times greater chemical concentration than a conventional ICP source.

HDRF provides better performance than wet processing and regular plasma processing in terms of selectivity, low damage, flexibility, and high-aspect-ratio efficiency. HDRF provides superior polymer removal efficiency for high-aspect-ratio (greater than 50:1) structures.

With operating temperatures lower than 80° C., and with high selectivity to TiN, Al, Au, SiO2, and Si3N4, HDRF provides damage-free residue removal for ultra-sensitive devices.

Nanoplas introduced the semi-automatic DSB 6000 system in 2008. It was followed in 2011by the fully automatic 200mm DSB 9000 system, which accommodates one or two process modules. Both systems are capable of chemical downstream etching, stripping and cleaning applications. The company also designed the HDRF300 system for advanced cleans for 3D-IC fabrication. Nanoplas customers include global companies utilizing the systems in volume production, and also R&D and pilot line facilities, company officials said.