Category Archives: LEDs

Cambridge Nanotherm today announced that Howard Ford has joined the board as chairman. Ford brings unrivalled experience operating at the highest level in both start-up and global technology companies. His knowledge and experience of transforming companies into global brands will help to ensure Cambridge Nanotherm continues its rapid growth.

Sales of Cambridge Nanotherm’s thermal management solutions for LEDs have exploded in 2015 and Ford will help continue the drive for expansion into key markets in Asia and the US.

“Howard has an outstanding track record in companies large and small. Both our employees and investors are delighted that he has agreed to join as we expand our product offering, customer base and geographical presence and continue to aggressively grow global sales,” commented Ralph Weir, CEO. “Howard’s experience, both at the helm of multinational organisations and moulding tech start-ups into global players makes him the perfect fit for Cambridge Nanotherm as we reinforce our strategic direction and cement our position as one of the market leaders for LED thermal management.”

“Cambridge Nanotherm is transforming the landscape of thermal management,” added Ford. “I’m relishing the opportunity to bring my experience to bear on a company that is making such big waves in the LED market.”

Ford has worked for a wide variety of high-profile technology companies in his career. Significant roles include chief executive of BT Cellnet and general manager of IBM’s European PC business; Ford was also managing director of Equant Network Services before it was acquired by France Telecom in 2005. In addition to Cambridge Nanotherm, Howard currently holds the position of chairman with Display Data, Pyreos, Light Blue Optics and Filtronic plc.

Cambridge Nanotherm’s innovative nanoceramic thermal management solutions have seen unprecedented market demand. Ford’s commercial expertise and strategic vision will help the board and management team build on this foundation. Cambridge Nanotherm’s move to strengthen the board with this appointment follows on from the appointment of Ewald Braith as non-executive director in April.

By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

Scaling is now bifurcating – some scaling on with 28/22nm, while other push below 14nm.

In his famous 1965 paper Cramming more components onto integrated circuits, Moore wrote: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year”. Dimensional scaling below 28nm will only increase the ‘component cost’ as we described in Moore’s Law has stopped at 28nm and is detailed in the following tables published recently by IBS.

Fig 1

 

While there is still a strong effort behind dimensional scaling to 14, 10 and 7nm – and possibly even beyond, a new scaling effort is emerging to reduce the ‘component costs’ and increase integration yet still utilize the 28 nm process node. The semiconductor industry is now going through a bifurcation phase.

This new emerging trend of scaling by factors other than dimensional scaling was recognized early-on by Gordon Moore and was detailed in his 1975 famous IEDM paper “Progress in digital integrated electronics.”. In that paper Moore updated the time scaling rate to every two years and suggested the following factors are helping to drive scaling forward:

  1.  “Die size” – “larger chip area”
  2. “Dimension” – “higher density” and “finer geometries”
  3. “Device and circuit cleverness”

A fourth factor should have been added to the list above – improvement in manufacturing efficiency, which ensued from the increase in wafer sizes from 4” to 5” and all the way to the 12” of today, and many other manufacturing improvements.

In the past, all of these factors were aggregated into dimensional scaling as old fabs got obsolete and improvements were implemented predominantly in the new emerging node. Nowadays, as dimensional scaling has reached its diminishing returns phase, we can see a very diverse adaption of technology improvments.

In his keynote presentation at the 2014 Synopsys user group meeting, Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys’ newer tools to improve older node design effectiveness. The following is one of them:

Fig 2

AMD’s recent presentation at ISSCC 2015 clearly illustrates this point by showing device improvements while still staying at the same 28 nm process node, see slide below. As could be seen, major improvements in power, yield, and performance are possible over time without changing the technology node. AMD’s President & CEO Dr. Lisa Su presentation in 2015 Semicon China, reiterated AMD’s technology progress within the same 28nm technology node:

Fig 3

Even more significant would be the adoption of a breakthrough technology. A good example is the SRAM technology developed by Zeno Semiconductor, which has recently been validated on a 28nm process. This new SRAM technology replaces the 6T SRAM bit cell with 1T SRAM (true SRAM – no refresh is needed) providing significant reduction of ‘component costs’ as is illustrated in the following two slides.

Fig 4

Fig 5

This new industry trend was nicely articulated by Kelvin Low of Samsung covered in “Samsung Describes Road to 14nm, FinFETs a challenge, FD-SOI an alternative.” Quoting: “Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price …The cost per transistor has increased in 14nm FinFETs and will continue to do so, Low said, so an alternative technology such as 28nm SOI is necessary”. TSMC too is now spending on new R&D efforts to improve their 28 nm as was presented in TSMC 2015 Technology Symposium, introducing new 28nm processes, 28HPC+ and 28ULP. 28HPC+ is for high performance, a speed gain of about 15% for the same leakage, or a reduction of 30-50% in leakage for the same speed. The 28ULP (for ultra-low power) process is for IoT applications with a lower operating voltage of 0.7V (versus 0.9V for 28HPC+). And also new standard cell libraries were developed for this process with 9 and 7 track libraries (compared to 12T/9T before).

“Device and circuit cleverness” as a factor will never stop; however, it is made of a series of individual improvements that will not be enough to sustain a long-term scaling path for the industry. An alternative long-term path will be “Die size” – “larger chip area,” which is effectively monolithic 3D, and manufacturing efficiency, which will have an important role in monolithic 3D.

And who is better to call it than Mark Bohr of Intel? In a recent blog piece “Intel predicts Moore’s Law to last another 10 years” Bohr is quoted predicting “that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”

And this is also visible in the marketplace by the industry-wide adoption of 3D NAND devices that Samsung started to mass-produce in 2014, and followed with a second generation 32 layer-stack device this year, and forecasting going to ~ 100 layers, as illustrated in their slide:

Fig 6

 

In the recent webcast “Monolithic 3D: The Most Effective Path for Future IC Scaling,” Dr. Maud Vinet of CEA Leti presented their “CoolCube” monolithic 3D technology, which was followed by our own, i.e., MonolithIC 3D, presentation. An important breakthrough presented by us was a monolithic 3D process flow that does not require changes in transistor-formation process and could be easily integrated by any fab at any process node.

Finally, I’d like to quote Mark Bohr again as we reported in our blog “Intel Calls for 3D IC”: “heterogeneous integration enabled by 3D IC is an increasingly important part of scaling” as was presented in ISSCC 2015.

Fig 7

 

This is illustrated nicely by the following figure presented by Qualcomm in their ISPD ‘15 paper titled “3D VLSI: A Scalable Integration Beyond 2D.”

Fig 8

 

In summary, the general promise of Moore’s Law is not going to end any time soon. Yet it is not going to be the simple brute-force x0.7 dimensional scaling that dominated the industry for the last 5 decades. Quoting Mark Bohr again, it “will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”

P.S. –

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies.

Samsung Electronics Co., Ltd. today announced the Samsung ARTIK platform to allow faster, simpler development of new enterprise, industrial and consumer applications for the Internet of Things (IoT). ARTIK is an open platform that includes a best-in-class family of integrated production-ready modules, advanced software, development boards, drivers, tools, security features and cloud connectivity designed to help accelerate development of a new generation of better, smarter IoT devices, solutions and services.

“We are providing the industry’s most advanced, open and secure platform for developing IoT products”, said Young Sohn, president and chief strategy officer, Samsung Electronics. “By leveraging Samsung’s high-volume manufacturing, advanced silicon process and packaging technologies, and extensive ecosystem, ARTIK allows developers to rapidly turn great ideas into market leading IoT products and applications.”

The ARTIK Family

All members of the Samsung ARTIK family incorporate unique embedded hardware security technology, on-board memory and advanced processing power in an open platform. Security is also a key element of the advanced software integrated into the platform, along with the ability to connect to the Internet for cloud-based data analytics and enhanced services. As an open platform, Samsung ARTIK can be easily customized for more rapid deployment of IoT devices and the services that can be delivered using them.

The Samsung ARTIK platform comes in a variety of configurations to meet the specific requirements of a wide range of devices from wearables and home automation, to smart lighting and industrial applications. Initial members of the ARTIK family include:

  • ARTIK 1, the smallest IoT module currently available in the industry at 12mm-by-12mm, combines Bluetooth/BLE connectivity and a nine-axis sensor with best-in-class compute capabilities and power consumption. It is specifically designed for low-power, small form-factor IoT applications.
  • ARTIK 5 delivers an outstanding balance of size, power and price-performance and is ideal for home hubs, drones and high-end wearables. It incorporates a 1GHz dual-core processor and on-board DRAM and flash memory.
  • ARTIK 10 delivers advanced capabilities and high-performance to IoT with an eight-core processor, full 1080p video decoding/encoding, 5.1 audio and 2GB DRAM along with 16GB flash memory. The Samsung ARTIK 10 includes Wi-Fi, Bluetooth/BLE and ZigBee connectivity and is designed for use with home servers, media applications, and in industrial settings.

“Industry requirements for IoT devices vary in terms of battery life, computational horse power and form factor,” said Sohn. “With this family of ARTIK offerings, Samsung is directly addressing the needs of the widest range of customers, uses and applications.”

The 61st annual IEEE International Electron Devices Meeting (IEDM) has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development. The paper submission deadline is Monday, June 22, 2015 at 23:59 p.m. Pacific Time.

Overall, the 2015 IEDM is seeking increased participation in the areas of ‘Beyond CMOS’ devices, flexible devices, neuromorphic computing, power devices, sensors for the Internet of Things (IoT) and variation/reliability.

In addition, Special Focus Sessions will be held on the following topics: neural-inspired architectures; 2D materials and applications; flexible electronics and applications; power devices and reliability on non-native substrates; and silicon-based nanodevices for detection of biomolecules.

The 2015 IEDM will take place at the Washington, DC Hilton Hotel from December 7-9, 2015, preceded by a collection of 90-minute afternoon Tutorial sessions on Saturday, Dec. 5, and a full day of Short Courses on Sunday, Dec. 6. On Wednesday the conference will continue the successful Entrepreneurs Luncheon sponsored by IEDM and EDS Women in Engineering.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics from industry, academia and government gather to participate in a technical program of more than 220 presentations, along with a special Luncheon Presentation on Tuesday, Dec. 8 and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events spotlighting more leading work in more areas of the field than any other conference.

Papers in the following areas are encouraged:
– Circuit and Device Interaction
– Characterization, Reliability and Yield
– Display and Imaging Systems
– Memory Technology
– Modeling and Simulation
– Nano Device Technology
– Power and Compound Semiconductor Devices
– Process and Manufacturing Technology
– Sensors, MEMS and BioMEMS

By combining 3D holographic lithography and 2D photolithography, researchers from the University of Illinois at Urbana-Champaign have demonstrated a high-performance 3D microbattery suitable for large-scale on-chip integration with microelectronic devices.

“This 3D microbattery has exceptional performance and scalability, and we think it will be of importance for many applications,” explained Paul Braun, a professor of materials science and engineering at Illinois. “Micro-scale devices typically utilize power supplied off-chip because of difficulties in miniaturizing energy storage technologies. A miniaturized high-energy and high-power on-chip battery would be highly desirable for applications including autonomous microscale actuators, distributed wireless sensors and transmitters, monitors, and portable and implantable medical devices.”

CREDIT: University of Illinois

CREDIT: University of Illinois

“Due to the complexity of 3D electrodes, it is generally difficult to realize such batteries, let alone the possibility of on-chip integration and scaling. In this project, we developed an effective method to make high-performance 3D lithium-ion microbatteries using processes that are highly compatible with the fabrication of microelectronics,” stated Hailong Ning, a graduate student in the Department of Materials Science and Engineering and first author of the article, “Holographic Patterning of High Performance on-chip 3D Lithium-ion Microbatteries,” appearing in Proceedings of the National Academy of Sciences.

“We utilized 3D holographic lithography to define the interior structure of electrodes and 2D photolithography to create the desired electrode shape.” Ning added. “This work merges important concepts in fabrication, characterization, and modeling, showing that the energy and power of the microbattery are strongly related to the structural parameters of the electrodes such as size, shape, surface area, porosity, and tortuosity. A significant strength of this new method is that these parameters can be easily controlled during lithography steps, which offers unique flexibility for designing next-generation on-chip energy storage devices.”

Enabled by a 3D holographic patterning technique–where multiple optical beams interfere inside the photoresist creating a desirable 3D structure–the battery possesses well-defined, periodically structured porous electrodes, that facilitates the fast transports of electrons and ions inside the battery, offering supercapacitor-like power.

“Although accurate control on the interfering optical beams is required to construct 3D holographic lithography, recent advances have significantly simplified the required optics, enabling creation of structures via a single incident beam and standard photoresist processing. This makes it highly scalable and compatible with microfabrication,” stated John Rogers, a professor of materials science and engineering, who has worked with Braun and his team to develop the technology.

“Micro-engineered battery architectures, combined with high energy material such as tin, offer exciting new battery features including high energy capacity and good cycle lives, which provide the ability to power practical devices,” stated William King, a professor of mechanical science and engineering, who is a co-author of this work.

BY GREG SHUTTLEWORTH, Global Product Manager at LINDE ELECTRONICS

The market expectations of modern electronics technology are changing the landscape in terms of performance and, in particular, power consumption, and new innovations are putting unprecedented demands on semiconductor devices. Internet of Things devices, for example, largely depend on a range of different sensors, and will require new architectures to handle the unprecedented levels of data and operations running through their slight form factors.

The continued shrinkage of semiconductor dimensions and the matching decreases in microchip size have corresponded to the principles of Moore’s Law with an uncanny reliability since the idea’s coining in 1965. However, the curtain is now closing on the era of predictable / conventional size reduction due to physical and material limitations.

Thus, in order to continue to deliver increased performance at lower costs and with a smaller footprint, different approaches are being explored. Companies can already combine multiple functions on a single chip–memory and logic devices, for example–or an Internet of Things device running multiple types of sensor through a single chip.

We have always known that we’d reach a point where conventional shrinking of semiconductor dimensions would begin to lose its effect, but now we are starting to tackle it head on. A leading U.S. semiconductor manufacturer got the ball rolling with their FinFET (or tri–gate) design in 2012 with its 3D transistors allowing designs that minimize current leakage; other companies look set to bring their own 3D chips to market.

At the same time, there’s a great deal of experimentation with a range of other approaches to semiconductor redesign. Memory device manufacturers, for instance, are looking to stack memory cells vertically on top of each other in order to make the most of a microchip’s limited space. Others, meanwhile, are examining the materials in the hope of using new, more efficient silicon–like materials in their chips.

Regardless of the approach taken, however, this step change in microchip creation means new material demands from chip makers and new manufacturing techniques to go with them.

The semiconductor industry has traditionally had to add new materials and process techniques to enhance the performance of the basic silicon building blocks with tungsten plugs, copper wiring / CMP, high–k metal gates, for example. Now, however, it is beginning to become impossible to extend conventional materials to meet the performance requirements. Germanium is already added to Si to introduce strain, but its high electron mobility means Germanium is also likely to become the material of the Fin itself and will be complemented by a corresponding Fin made of III–V material, in effect integrating three semiconductor materials into a single device.

Further innovation is required in the areas of lithography and etch. This is due to the delay in production suitability of the EUV lithography system proposed to print the very fine structures required for future technology nodes. Complex multi-patterning schemes using conventional lithography are already underway to compensate for this technology delay, requiring the use of carbon hard masks and the introduction of gases such as acetylene, propylene and carbonyl sulphide to the semiconductor fab. Printing the features is only half of the challenge; the structures also need to be etched. The introduction of new materials always presents some etch challenges as all materials etch at slightly different rates and the move to 3D structures, where very deep and narrow features need to be defined through a stack of different materials, will be a particularly difficult challenge to meet.

The microchip industry has continuously evolved to deliver amazing technological advances, but we are now seeing the start of a revolution in microchip design and manufacturing. The revolution will be slow but steady. Such is the pattern of the microchip industry, but it will need a succession of new materials at the ready, and, at Linde, we’re prepared to make sure the innovators have everything they need.

Quantum dots are finally ready for prime time and will exceed traditional phosphor revenue by 2020 by allowing LCD to compete with OLED in the race for the next display generation.
Yole Développement (Yole), the “More than Moore” market research and strategy consulting company releases a LED downconverters technology & market report, entitled “Phosphors & Quantum Dots 2015: LED Downconverters for Lighting & Displays”. Under this new report, the company proposes a deep review of the industry, especially the impact of the quantum dots development on the display and traditional phosphors industry. Are the quantum dots a real competitor of OLEDs technology?

After the lukewarm reception of 3D and 4K, the display industry needs a new and disruptive experience improvement to bring consumers back to the store. Image quality perception increases significantly when color gamut and dynamic contrast ratio are improved. Leading movie studios, content providers, distributors and display makers gathered and formed the “UHD Alliance” to promote those features.

“OLED was believed to be the technology of choice for this next generation of displays. But production challenges have delayed the availability of affordable OLED TVs. LCD TVs with LED backlights based on quantum dots downconverters can deliver performance close to, or even better than OLED in some respects, and at a lower cost,” said Dr. Eric Virey, Senior Analyst, LEDs at Yole.

Until OLEDs are ready, QD-LCD have a unique window of opportunity to try to close enough of the performance gap that the majority of the consumers won’t perceive the difference between the two technologies and price would become the driving factor in the purchasing decision. Under this scenario, QD-LCD could establish itself as the dominant technology while OLED would be cornered into the high end of the market. OLED potentially offers more opportunities for differentiation but proponents need to invest massively and still have to resolve manufacturing yield issues. For tier-2 LCD panel makers who can’t invest in OLED, QDs offer an opportunity to boost LCD performance without additional CAPEX on their fabs. At the 2015 CES, 7 leading TV OEMs including Samsung and LG showed QD-LCD TVs.

With tunable and narrowband emissions, QDs offer unique design flexibility. But more is needed to enable massive adoption, including the development of further improved Cd-free compositions.

And traditional phosphors haven’t said their last word. If PFS could further improve in term of stability and decay time and a narrow-band green composition was to emerge, traditional phosphors could also be part of the battle against OLED.

“… LCD TVs with LED backlights based on quantum dots downconverters can deliver performance close to, or even better than OLED in some respects, and at a lower cost.” said Dr. E. Virey, Yole.

Yole’s analysis, “Phosphors & Quantum Dots 2015: LED Downconverters for Lighting & Displays”, presents an overview of the quantum dot LED market for display and lighting applications including quantum dot manufacturing, benefits and drawbacks, quantum dots LCD versus OLED and detailed market forecast.

Researchers at the University of Rochester have shown that defects on an atomically thin semiconductor can produce light-emitting quantum dots. The quantum dots serve as a source of single photons and could be useful for the integration of quantum photonics with solid-state electronics – a combination known as integrated photonics.

Scientists have become interested in integrated solid-state devices for quantum information processing uses. Quantum dots in atomically thin semiconductors could not only provide a framework to explore the fundamental physics of how they interact, but also enable nanophotonics applications, the researchers say.

Quantum dots are often referred to as artificial atoms. They are artificially engineered or naturally occurring defects in solids that are being studied for a wide range of applications. Nick Vamivakas, assistant professor of optics at the University of Rochester and senior author on the paper, adds that atomically thin, 2D materials, such as graphene, have also generated interest among scientists who want to explore their potential for optoelectronics. However, until now, optically active quantum dots have not been observed in 2D materials.

In a paper published in Nature Nanotechnology this week, the Rochester researchers show how tungsten diselenide (WSe2) can be fashioned into an atomically thin semiconductor that serves as a platform for solid-state quantum dots. Perhaps most importantly the defects that create the dots do not inhibit the electrical or optical performance of the semiconductor and they can be controlled by applying electric and magnetic fields.

Vamivakas explains that the brightness of the quantum dot emission can be controlled by applying the voltage. He adds that the next step is to use voltage to “tune the color” of the emitted photons, which can make it possible to integrate these quantum dots with nanophotonic devices.

A key advantage is how much easier it is to create quantum dots in atomically thin tungsten diselenide compared to producing quantum dots in more traditional materials like indium arsenide.

“We start with a black crystal and then we peel layers of it off until we have an extremely thin later left, an atomically thin sheet of tungsten diselenide,” said Vamivakas.

The researchers take two of these atomically thin sheets and lay one over the other one. At the point where they overlap, a quantum dot is created. The overlap creates a defect in the otherwise smooth 2D sheet of semiconductor material. The extremely thin semiconductors are much easier to integrate with other electronics.

The quantum dots in tungsten diselenide also possess an intrinsic quantum degree of freedom – the electron spin. This is a desirable property as the spin can both act as a store of quantum information as well as provide a probe of the local quantum dot environment.

“What makes tungsten diselenide extremely versatile is that the color of the single photons emitted by the quantum dots is correlated with the quantum dot spin,” said first author Chitraleema Chakraborty. Chakraborty added that the ease with which the spins and photons interact with one another should make these systems ideal for quantum information applications as well as nanoscale metrology.

A new study coauthored by Wellesley economist, Professor Daniel E. Sichel, reveals that innovation in an important technology sector is happening faster than experts had previously thought, creating a backdrop for better economic times ahead.

The Producer Price Index (PPI) of the United States suggests that the prices of semiconductors have barely fallen in recent years. The slow decline in semiconductor prices stands in sharp contrast to the rapidly falling prices reported from the mid-1980s to the early 2000s, and has been interpreted as a signal of sluggish innovation in this key sector.

The apparent slowdown puzzled Sichel and his coauthors, David M. Byrne of the Federal Reserve Board, and Stephen D. Oliner, of the American Enterprise Institute and UCLA–particularly in light of evidence that the performance of microprocessor units (MPUs), which account for about half of U.S. semiconductor shipments, has continued to improve at rapid pace. After closely examining historical pricing data, the economists found that Intel, the leading producer of MPUs, dramatically changed the way it priced these chips in the mid-2000s–roughly the same time when the slowdown reported by government data occurs. Prior to this period, Intel typically lowered the list prices of older chips to remain competitive with newly introduced chips. However, after 2006, Intel began to keep chip prices relatively unchanged over their life cycle, which affected official statistics.

To obtain a more accurate assessment of the pace of innovation in this important sector, Sichel, Byrne, and Oliner developed an alternative method of measurement that evaluates changes in actual MPU performance to gauge the rate of improvement in price-performance ratios. The economists’ preferred index shows that quality-adjusted MPU prices continued to fall rapidly after the mid-2000s, contrary to what the PPI indicates–meaning that worries about a slowdown in this sector are likely unwarranted.

According to Sichel, these results have important implications, not only for understanding the rate of technological progress in the semiconductor industry but also for the broader debate about the pace of innovation in the U.S. economy.

“These findings give us reason to be optimistic,” said Sichel. “If technical change in this part of the economy is still rapid, it provides hope for better times ahead.”

Sichel and his coauthors also acknowledge that their results raise a new puzzle. “In recent years,” they write, “the price index for computing equipment has fallen quite slowly by historical standards. If MPU prices have, in fact, continued to decline rapidly, why have prices for computers–which rely on MPUs for their performance–not followed suit?” The researchers believe it is possible that the official price indexes for computers may also suffer from measurement issues, and they are investigating this possibility in further work.

“How Fast Are Semiconductor Prices Falling,” coauthored by Daniel E. Sichel, Wellesley College and NBER; David M. Byrne, Federal Reserve Board; and Stephen D. Oliner, American Enterprise Institute and UCLA, is available as an NBER working paper and is online at http://www.nber.org/papers/w21074 and https://www.aei.org/publication/how-fast-are-semiconductor-prices-falling/.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $83.1 billion during the first quarter of 2015, an increase of 6.0 percent compared to the first quarter of 2014. Global sales for the month of March 2015 were $27.7 billion, 6.0 percent higher than the March 2014 total of $26.1 billion and 0.1 percent lower than last month’s total. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Despite macroeconomic challenges, first quarter global semiconductor sales are higher than they were last year, which was a record year for semiconductor revenue,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas region posted its sixth straight month of double-digit, year-to-year growth to lead all regional markets, and DRAM and analog products continue to be key drivers of global sales growth.”

Regionally, sales were up compared to last month in Asia Pacific/All Other (3.1 percent), Europe (2.7 percent), and China (1.0 percent), which is broken out as a separate country in the sales data for the first time. Japan(-0.4 percent) and the Americas (-6.9 percent) both saw sales decrease compared to last month. Compared to March 2014, sales increased in the Americas (14.2 percent), China (13.3 percent), and Asia Pacific/All Other (3.8 percent), but decreased in Europe (-4.0 percent) and Japan (-9.6 percent).

“Congress is considering a legislative initiative called Trade Promotion Authority (TPA) that would help promote continued growth in the semiconductor sector and throughout the U.S. economy,” Neuffer continued. “Free trade is vital to the U.S. semiconductor industry. In 2014, U.S. semiconductor company sales totaled $173 billion, representing over half the global market, and 82 percent of those sales were to customers outside the United States. TPA paves the way for free trade, and Congress should swiftly enact it.”

March 2015
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 6.23 5.80 -6.9%
Europe 2.88 2.95 2.7%
Japan 2.55 2.54 -0.4%
China 7.75 7.83 1.0%
Asia Pacific/All Other 8.33 8.59 3.1%
Total 27.74 27.71 -0.1%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 5.08 5.80 14.2%
Europe 3.08 2.95 -4.0%
Japan 2.81 2.54 -9.6%
China 6.91 7.83 13.3%
Asia Pacific/All Other 8.27 8.59 3.8%
Total 26.15 27.71 6.0%
Three-Month-Moving Average Sales
Market Oct/Nov/Dec Jan/Feb/Mar % Change
Americas 6.73 5.80 -13.8%
Europe 3.01 2.95 -1.7%
Japan 2.80 2.54 -9.1%
China 8.03 7.83 -2.5%
Asia Pacific/All Other 8.57 8.59 0.2%
Total 29.13 27.71 -4.9%

About SIA