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Semiconductor equipment manufacturer ClassOne Technology announced today that it has signed a joint electrochemical deposition (ECD) applications lab agreement with Shanghai Sinyang Semiconductor Materials Co., Ltd.  Sinyang, China’s premier supplier of ECD chemicals, is purchasing ClassOne electroplating equipment and will be providing a site for demonstrating ClassOne’s tools in the Chinese marketplace. SPM International Ltd., ClassOne’s representative in China will also be providing product support and process assistance.

“This collaborative lab will be the first of its kind in the region,” said Byron Exarcos, President of ClassOne Technology. “Now, in a single location, users will be able to see the advanced performance of ClassOne’s electroplating tools and Sinyang’s electroplating chemicals and also be able to evaluate processes. It allows us to provide a complete solution — and a significant convenience — to users throughout the region.”

“We are looking forward to working with customers on the Solstice LT plating system because it is a high-performance tool and will provide an excellent real-world laboratory for ongoing enhancement of our chemicals,” said Dr. Wang Su, Vice President of Sinyang. “The new working arrangement will also enable us to provide direct input to ClassOne as they develop future generations of wet processing equipment.”

Shanghai Sinyang is purchasing ClassOne’s Solstice LT Electroplating System and Trident Spin Rinse Dryer (SRD). The Solstice LT is a two-chamber plating development tool designed for <200mm wafers. In Sinyang’s applications, one chamber will be dedicated to copper plating and the second to nickel plating, with the Trident SRD servicing both process streams. This will provide significant flexibility while substantially reducing cycle time and streamlining process development. The new equipment will be installed at the Sinyang lab facility in Shanghai, which is scheduled to begin live demonstrations in late May. The lab will be able to plate virtually all metals except gold, and it can also cross-reference with all chemicals for comparison benchmarks.

In addition to the LT development tool, ClassOne also offers the Solstice S8, an 8-chamber, fully-automated electroplating system for high-volume production needs. These tools are particularly well suited to wafer level packaging (WLP), through silicon via (TSV) and other applications that are important for MEMS, Sensors, LEDs, RF, Power and many other devices.

ClassOne Technology products have been described as “Advanced Wet Processing Tools for the Rest of Us” because they address the needs of many cost-conscious users. The company’s stated aim is to provide advanced yet affordable alternatives to the large systems from the large manufacturers. ClassOne supplies a range of innovative new wet processing tools, including its Solstice Electroplating Systems, Trident Spin Rinse Dryers and Trident Spray Solvent Tools (SSTs).

April 2015 marks the 50th anniversary of one of the business world’’s most profound drivers, now commonly referred to as Moore’s Law.  In April 1965, Gordon Moore, later co-founder of Intel, observed that the number of transistors per square inch on integrated circuits would continue to double every year.  This “observation” has set the exponential tempo for five decades of innovation and investment resulting in today’s $336 billion USD integrated circuits industry enabled by the $82 billion USD semiconductor equipment and materials industry (SEMI and SIA 2014 annual totals).

SEMI, the global industry association serving the nano- and micro-electronic manufacturing supply chains, today recognizes the enabling contributions made by the over 1,900 SEMI Member companies in developing semiconductor equipment and materials that produce over 219 billion integrated circuit devices and 766 billion semiconductor units per year (WSTS, 2014).

50 years of Moore’’s Law has led to one of the most technically sophisticated, constantly evolving manufacturing industries operating today.  Every day, integrated circuit (IC) production now does what was unthinkable 50 years ago.  SEMI Member companies now routinely produce materials such as process gases, for example, to levels of 99.994 percent quality for bulk Silane (SiH4) in compliance with the SEMI C3.55 Standard.  Semiconductor equipment manufacturers develop the hundreds of processing machines necessary for each IC factory (fab) that are at work all day, every day, processing more than 100 silicon wafers per hour with fully automated delivery and control – all with standardized interoperability. SEMI Member companies provide the equipment to inspect wafer process results automatically, and find and identify defects at sizes only fractions of the 14nm circuit line elements in today’s chips, ensuring process integrity throughout the manufacturing process.

“”It was SEMI Member companies who enabled Moore’’s Law’’s incredible exponential growth over the last 50 years,”” said Denny McGuirk, president and CEO of SEMI.  “”Whereas hundreds of transistors on an IC was noteworthy in the 1960s, today over 1.3 billion transistors are on a single IC.  SEMI Member companies provide the capital equipment and materials for today’s mega-fabs, with each one processing hundreds or thousands of ICs on each wafer with more than 100,000 wafers processed per month.””

To celebrate SEMI Member companies’ contribution to the 50 years of Moore’s Law, SEMI has produced a series of Infographics that show the progression of the industry.

1971

2015

Price per chip

$351

$393

Price per 1,000 transistors

$150

$0.0003

Number of transistors per chip

2,300

1,300,000,000

Minimum feature size on chip

10,000nm

14nm

From SEMI infographic “Why Moore Matters”: www.semi.org/node/55026

Sensor shipments are getting a big boost from the spread of embedded measurement functions for automated intelligent controls in systems and new high-volume applications—such as wearable electronics and the huge potential of the Internet of Things (IoT)—but sales growth is being pulled down significantly by price erosion in this once high-flying semiconductor marketplace, according to IC Insights’ new 2015 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.

Average selling prices (ASPs) for all types of semiconductor sensors are forecast to fall by a compound annual growth rate (CAGR) of -5 percent in the next five years, which is double the rate of decline in the previous five years (2009-2014), says the new IC Insights report. Unit volume growth is expected to climb by a strong CAGR of 11.4 percent in the 2014-2019 timeframe and reach 19.1 billion sensor shipments worldwide in five years and revenue growth is projected to rise by an annual rate of 6.0 percent in the forecast period. In comparison, sensor sales grew by a CAGR of 17.1 percent between 2009 and 2014 to reach a new record high of $5.7 billion last year, according to analysis found in the 360-page annual O-S-D Report, which also covers actuators, optoelectronics, and discrete semiconductors.

ASP erosion is partly a result of intense competition among a growing number of sensor suppliers pursuing new portable, consumer, and IoT applications. Sensor ASPs are also being driven much lower because many new high-volume applications require rock-bottom prices. The fall in prices is not only undermining revenue growth in the highly competitive sensor segment, but it is also now squeezing profit margins among suppliers.

Semiconductor sensors make up nearly two-thirds of the total sensor/actuator market segment, according to the 2015 O-S-D Report. As shown in Figure 1, acceleration/yaw sensors (i.e., accelerometers and gyroscope devices) remained the largest sensor category, in terms of dollar sales volume, accounting for 26 percent of the total sensor/actuator market. The acceleration/yaw sensor category continued to struggle due to price erosion and a significant deceleration in unit growth to just 1 percent in 2014, which resulted in a 4 percent drop in worldwide sales to $2.4 billion after falling 2 percent in 2013. Magnetic-field sensors (including electronic compass chips) rebounded in 2014 with an 11 percent increase in sales to set a new record high of about $1.6 billion after slumping 1 percent in 2013. Pressure sensor sales remained strong in 2014, growing 15 percent to a new record-high $1.5 billion after climbing 16 percent in 2013.

sensor shipments

Figure 1

 

The forecast in the O-S-D Report shows total sensor sales growing 7 percent in 2015 to $6.1 billion after rising just 5 percent in 2014. Sensor shipments are projected to climb 16 percent in 2015 to 12.9 billion units after a 13 percent increase in 2014.

About 80 percent of the sensors/actuators market’s sales in 2014 came from semiconductors built with microelectromechanical systems (MEMS) technology—primarily pressure and acceleration/yaw sensors and actuator devices.  MEMS-based product sales grew about 5 percent to a record-high $7.4 billion in 2014 from $7.0 billion in 2013.  Sensors accounted for 53 percent of MEMS-based semiconductor sales in 2014 ($3.9 billion) while 46 percent of the total ($3.5 billion) came from actuators, such as micro-mirrors for displays and digital projectors, microfluidic devices for inkjet printer nozzles and other application, radio frequency (RF) MEMS filters, and timekeeping silicon oscillators.

In terms of unit volumes, sensors represented 80 percent of the 5.1 billion MEMS-based semiconductors shipped in 2014 (4.1 billion) with the remaining 20 percent being actuators (about 1.0 billion).

After dropping slightly more than 1 percent in 2012 and being flat in 2013, sales of MEMS-based semiconductors recovered in 2014 with actuators ending a two-year decline, rising 7 percent, and pressure sensors continuing double-digit growth with a 15 percent increase in the year.  Sales of MEMS-based sensors and actuators are forecast to grow 7 percent in 2015 to $7.9 billion and reach $9.8 billion in 2019, representing a CAGR of 12.0 percent from 2014.

By Lara Chamness, senior market analyst manager, SEMI

Semiconductor Market Trends

2014 was the second record breaking year in a row in terms of semiconductor device revenues; the industry grew a robust 10 percent to total $336 billion, according to the WSTS. The strong momentum of the device market was enough to drive positive growth for both the equipment and materials markets. After two successive years of revenue decline, both the equipment and materials markets grew 18 percent and 3 percent, respectively last year, according to SEMI (www.semi.org). Even though the semiconductor materials market did not enjoy the same magnitude of recovery as the equipment market last year, the materials market has been larger than the equipment for the past seven years.

Just like last year, the weakened Yen negatively impacted total revenues for semiconductor materials and equipment (refer to Dan Tracy’s March 2014 article for more detail). The Table (below) shows the impact of the weakened Yen on Semiconductor Equipment Association of Japan’s (SEAJ) book-to-bill data. SEMI reveals that if the data was kept in Yen, the 2014 market for Japan-based suppliers would be up 37 percent. However, when the Yen are converted to dollars the 2014 equipment market for Japan-based suppliers only increased 26 percent. When silicon semiconductor shipment volumes are compared year-over-year, shipments were up 11 percent. By comparison, silicon revenues only increased one percent. SEMI also tracks leadframe unit shipments. In 2014, leadframe shipments were up 9 percent year-over-year; however, leadframe revenues increased only 4 percent. Silicon and leadframe revenues were adversely impacted by intense price down pressure exasperated by the weakened Yen. Given that Japan-headquartered suppliers represent a significant portion of the equipment and materials markets; this has the effect of muting the growth of the global equipment and materials markets as well.

Semiconductor Equipment

Worldwide sales of semiconductor manufacturing equipment totaled $37.5 billion in 2014, representing a year-over-year increase of 18 percent and placing spending on par with 2004 levels. According to SEMI, looking at equipment sales by major equipment category, 2014 saw expansions in all major categories — Wafer Processing equipment increased 15 percent, while the Assembly and Packaging and Test equipment segments grew 32 and 31 percent, respectively. The Other Front-end segment (Other Front End includes Wafer Manufacturing, Mask/Reticle, and Fab Facilities equipment) increased 15 percent.

Taiwan retained its number one ranking last year at $8.2 billion, even though it was the only region to experience a year-over-year contraction in spending. The equipment market in North America maintained second place at $8.2 billion for the second year as its market grew a robust 55 percent due to investments in excess of a billion dollars each from Intel, GLOBALFOUNDRIES, and Samsung.  Spending levels of $6.8 billion in South Korea remain significantly below their market high set in 2012 resulting in South Korea maintaining the third spot for the second year in a row. China moved up in the rankings to hit a market high and displacing Japan to claim the fourth position in the market. Strong investments by Samsung, SK Hynix, SMIC, and back-end companies are driving the equipment market in China. Equipment sales to Europe and Rest of world increased 24 and 4 percent, respectively in 2014. Rest of World region aggregates Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.

Semiconductor Materials
SEMI reports that the global semiconductor materials market, which includes both fab and packaging materials, increased 3 percent in 2014 totaling $44.3 billion. Looking at the materials market by wafer fab and packaging materials, the wafer fab materials segment increased 6 percent, while the packaging materials segment was flat.  However if bonding wire were excluded from the packaging materials segment, the segment increased more than 4 percent last year. The continuing transition to copper-based bonding wire from gold is negatively impacting overall packaging materials revenues.

Taiwan maintained the top spot for the fifth year in a row, followed by Japan, South Korea, Rest of World, and China. Driving the materials market in Taiwan are advanced packaging operations and foundries. Japan still claims a significant installed fab base and has a tradition in domestic-based packaging, although many companies in Japan have rapidly adopted a fab lite strategy and have consolidated their fab and packaging plants. South Korea passed Rest of World (primarily SE Asia) as the third largest market for semiconductor materials given the dramatic increase in advanced fab capacity in the region in recent years.

Outlook

Most analysts predict mid- to high single-digit growth for the semiconductor device market for 2015. Initial monthly data for silicon shipments and semiconductor equipment are proving to be encouraging. In light of growth expectations for the device market, SEMI projects that the semiconductor materials market will increase 4 percent this year. Given current CapEx announcements, the outlook for semiconductor equipment is optimistic as well, with current projections of the equipment market showing another year of growth, which would place the equipment market on par with the last market high set in 2011.

2014 was a much welcomed year for equipment and materials suppliers as device manufacturers easily exceeded revenues of $300 billion. Even with the weakened Yen, both the semiconductor and equipment segments experienced growth. 2015 is promising to be another growth year for the entire market with device, materials and equipment suppliers poised to experience increases for the year.

Portions of this article were derived from the SEMI Worldwide Semiconductor Equipment Market Statistics (WWSEMS), the Material Market Data Subscription (MMDS) and the World Fab Watch database. These reports are essential business tools for any company keeping track of the semiconductor equipment and material market. Additional information regarding this report and other market research reports is available at www.semi.org/marketinfo

Common pulsed measurement challenges are defined.

In case you missed it, Part 1 is available here.

BY DAVID WYBAN, Keithley Instruments, a Tektronix Company, Solon, Ohio

For SMU and PMU users, an issue that sometimes arises when making transient pulse measurements is the presence of “humps” (FIGURE 1) in the captured current waveform at the rising and falling edges of the voltage pulse. These humps are caused by capacitances in the system originating from the cabling, the test fixture, the instrument, and even the device itself. When the voltage being output is changed, the stray capacitances in the system must be either charged or discharged and the charge current for this either flows out of or back into the instrument. SMUs and PMUs measure current at the instrument, not at the DUT, so the instrument measures these current flows while a scope probe at the device does not.

FIGURE 1. Humps in the captured current (red) waveform at the rising and falling edges of the voltage pulse.

FIGURE 1. Humps in the captured current (red) waveform at the rising and falling edges of the voltage pulse.

This phenomenon is seen most often when the change in voltage is large or happens rapidly and the current through the device itself is low. The higher the voltage of the pulse or the faster the rising and falling edges, the larger the current humps will be. For SMUs with rise times in the tens of microseconds, these humps are usually only seen when the voltages are hundreds or even thousands of volts and the current through the device is only tens of microamps or less. However, for PMUs where the rise times are often less than 1μs, these humps can become noticeable on pulses of only a couple of volts, even when the current through the device is as high as several milliamps.
Although these humps in the current waveform may seem like a big problem, they are easy to eliminate. The humps are the result of the current being measured at the high side of the device where the voltage is changing. Adding a second SMU or PMU at the low side of the device to measure current will make these humps go away because at the low side of the device the voltage does not change so there’s no charge or discharge currents flowing and the current measured at the instrument will match the current at the device. If this isn’t an option, this problem can be minimized by reducing the stray capacitance in the system by reducing the length of the cables. Shorter cables equal less stray capacitance, which reduces the size of the humps in the current waveform.

The next common pulse measurement issue is test lead resistance. As test currents get higher, the impact of this resistance becomes increasingly significant. FIGURE 2 shows an SMU that is performing a pulse I-V measurement at 2V across a 50mΩ load. Based on Ohm’s Law, one might expect to measure a current through the device of 40A, but when the test is actually performed, the level of current measured is only 20A. That “missing” 20A is the result of test lead resis- tance. In fact, we were not pulsing 2V into 50mΩ but into 100mΩ instead, with 25mΩper test lead. With 50mΩ of lead resistance, half of the output voltage sourced was dropped in the test leads and only half of it ever reached the device.

FIGURE 2. Impact of test lead resistance.

FIGURE 2. Impact of test lead resistance.

To characterize the device correctly, it’s essential to know not only the current through the device but the actual voltage at the device. On SMUs this is done by using remote voltage sensing. Using a second set of test leads allows the instrument to sense the voltage directly at the device; because almost no current flows through these leads, the voltage fed back to the instrument will match the voltage at the device. Also, because these leads feed the voltage at the device directly back into the SMU’s feedback loop, the SMU can compensate for the voltage drop across the test leads by outputting a higher voltage at its output terminals.

Although SMUs can use remote sensing to compensate for voltage drops in the test leads, there is a limit to how much drop it can compensate for. For most SMUs, this maximum drop is about 3V/lead. If the voltage drop per lead reaches or exceeds this limit, strange things can start happening. The first thing is that the rise and fall times of the voltage pulse slow down, significantly increasing the time required to make a settled measurement. Given enough time for the pulse to settle, the voltage measurements may come back as the expected value, but the measured current will be lower than expected because the SMU is actually sourcing a lower voltage at the DUT than the level that it is programmed to source.

If you exceed the source-sense lead drop while sourcing current, a slightly different set of strange behaviors may occur. The current measurement will come back as the expected value and will be correct because current is measured internally and this measurement is not affected by lead drop, but the voltage reading will be higher than expected. In transient pulse measurements, you may even see the point at which the source-sense lead drop limit was exceeded as the measured voltage suddenly starts increasing again after it appeared to be settling.

These strange behaviors can be difficult to detect in the measured data if you do not know what voltage to expect from your device. Therefore, inspecting your pulse waveforms fully when validating your test system is essential.

Minimizing test lead resistance is essential to ensuring quality pulse measurements. There are two ways to do this:

Minimize the length of the test leads. Wire resistance increases at a rate that’s directly proportional to the length of the wire. Doubling the wire’s length doubles the resis- tance. Keeping leads lengths no greater than 3 meters is highly recommended for high current pulse applications.

Use wire of the appropriate diameter or gauge for the current being delivered. The resistance of a wire is also directly proportional to the cross sectional area of the wire. Increasing the diameter, or reducing the gauge, of the wire increases this area and reduces the resistance. For pulse applications up to 50A, a wire gauge of no greater than 12 AWG is recommended; for applications up to 100A, it’s best to use no greater than 10 gauge.

Excessive test lead inductance is another common issue. In DC measurements, test lead inductance is rarely considered because it has little effect on the measurements. However, in pulse measurements, lead inductance has a huge effect and can play havoc with a system’s ability to take quality measurements.

FIGURE 3. Humps in the voltage waveform of transient pulse measurements due to test system inductance.

FIGURE 3. Humps in the voltage waveform of transient pulse measurements due to test system inductance.

Humps in the voltage waveform of transient pulse measurements (FIGURE 3) are a common problem when generating current pulses. Just as with humps in the current waveforms, these humps can be seen in the data from the instrument but are nowhere to be seen when measured at the device with an oscilloscope. These humps are the result of the additional voltage seen at the instrument due to inductance in the cabling between the instrument and th

Equation 1

Equation 1

Equation 1 describes the relation between inductance and voltage. With this equation, we can see that for a given change in current over change in time (di over dt), the larger the inductance L is, the larger the resulting voltage will be. This equation also tells us that for a fixed inductance L, the larger the change in current or the smaller the change in time, the larger the resulting voltage will be. This means that the larger the pulse and or the faster the rise and falls times, the bigger the voltage humps will be.

To remedy this problem, instruments like SMUs offer remote voltage sensing, allowing them to measure around this lead inductance and measure the voltage directly at the device. However, as with excessive lead resistance, excessive lead inductance can also cause a problem for SMUs. If the inductance is large enough and causes the source-sense lead drop to exceed the SMU’s limit, transient pulse measurement data will have voltage measurement errors on the rising and falling edges similar to the ones seen when lead resistance is too large. Pulse I-V measurements are generally unaffected by lead inductance because the measurements are taken during the flat portion of the pulse where the current is not changing. However, excessive lead inductance will slow the rising and falling edges of voltage pulses and may cause ringing on current pulses, thereby requiring larger pulse widths to make a good settled pulse I-V measurement.

The Anatomy of a Pulse The amplitude and base describe the height of the pulse in the pulse waveform. Base describes the DC offset of the waveform from 0. This is the level the waveform will be both before and after the pulse. Amplitude is the level of the waveform relative to the base level and has an absolute value that is equal to the base plus amplitude. For example, a pulse waveform with a base of 1Vand an amplitude of 2V would have a low level of 1V and a high level of 3V. Pulse width is the time that the pulse signal is applied. It is commonly defined as the width in time of the pulse at half maximum also known as Full Width at Half Maximum (FWHM). This industry standard definition means the pulse width is measured where the pulse height is 50% of the amplitude. Pulse period is the length in time of the entire pulse waveform before it is repeated and can easily be measured by measuring the time from the start of one pulse to the next. The ratio of pulse width over pulse period is the duty cycle of the pulse waveform. A pulse’s rise time and fall time are the times it takes for the waveform to transition from the low level to the high level and from the high level back down to the low level. The industry standard way to measure the rise time is to measure the time it takes the pulse waveform to go from 10% amplitude to 90% amplitude on the rising edge. Fall time is defined as the time it takes for the waveform to go from 90% amplitude to 10% amplitude on the falling edge.

The Anatomy of a Pulse
The amplitude and base describe the height of the pulse in the pulse waveform. Base describes the DC offset of the waveform from 0. This is the level the waveform will be both before and after the pulse. Amplitude is the level of the waveform relative to the base level and has an absolute value that is equal to the base plus amplitude. For example, a pulse waveform with a base of 1Vand an amplitude of 2V would have a low level of 1V and a high level of 3V.
Pulse width is the time that the pulse signal is applied. It is commonly defined as the width in time of the pulse at half maximum also known as Full Width at Half Maximum (FWHM). This industry standard definition means the pulse width is measured where the pulse height is 50% of the amplitude.
Pulse period is the length in time of the entire pulse waveform before it is repeated and can easily be measured by measuring the time from the start of one pulse to the next.
The ratio of pulse width over pulse period is the duty cycle of the pulse waveform.
A pulse’s rise time and fall time are the times it takes for the waveform to transition from the low level to the high level and from the high level back down to the low level. The industry standard way to measure the rise time is to measure the time it takes the pulse waveform to go from 10% amplitude to 90% amplitude on the rising edge. Fall time is defined as the time it takes for the waveform to go from 90% amplitude to 10% amplitude on the falling edge.

Although SMUs are able to compensate for some lead inductance, PMUs have no compensation features, so the effects of inductance must be dealt with directly, such as by:

  • Reducing the size of the change in current by reducing the magnitude of the pulse.
  • Increasing the length of the transition times by increasing the rise and fall times.
  • Reducing the inductance in the test leads

Depending on the application or even the instrument, the first two measures are usually infeasible, which leaves reducing the inductance in the test leads. The amount of inductance in a set of test leads is proportionate to the loop area between the HI and LO leads. So, in order to reduce the inductance in the leads and therefore reduce the size of the humps, we must reduce the loop area, which is easily done by simply twisting the leads together to create a twisted pair or by using coaxial cable. Loop area can be reduced further by simply reducing the length of the cable.

BY JOE CESTARI, Total Facility Solutions, Plano, Texas

When the commercial semiconductor manufacturing industry decides to move to the next wafer size of 450mm, it will be time to re-consider equipment and facilities strategies. Arguably, there is reason to implement new strategies for any new fab to be built regardless of the substrate size. In the case of 450mm, if we merely scale up today’s 300mm layouts and operating modes, the costs of construction would more than double. Our models show that up to 25 percent of the cost of new fab construction could be saved through modular design and point-of-use (POU) facilities, and an additional 5-10 percent could be saved by designing for “lean” manufacturing.

In addition to cost-savings, these approaches will likely be needed to meet the requirements for much greater flexibility in fab process capabilities. New materials will be processed to form new devices, and changes in needed process-flows and OEM tools will have to be accommodated by facilities. In fact, tighter physical and data integration between OEM tools and the fab may result in substantially reduced time to first silicon, ongoing operating costs and overall site footprint.

POU utilities with controls close to the process chambers, rather than in the sub-fab, have been modeled as providing a 25-30 percent savings on instrumentation and control systems throughout the fab. Also, with OEM process chamber specifications for vacuum-control and fluid-purity levels expected to increase, POU utilities provide a flexible way to meet future requirements.

Reduction of fluid purity specifications on central supply systems in harmony with increases in localized purification systems for OEM tools can also help control costs, improve flexibility, and enhance operating reliability. There are two main reasons why our future fabs will need much greater flexibility and intelligence in facilities: high-mix production, and 1-12 wafer lots.

High-mix production

Though microprocessors and memory chips will continue to increase in value and manufacturing volumes, major portions of future demand for ICs will be SoCs for mobile applications. The recently announced “ITRS 2.0”—the next roadmap for the semicon- ductor fab industry after the “2013” edition published early in 2014—will be based on applications solutions and less on simple shrinks of technology. Quoting Gartner Dataquest”s assessment:

“System-on-chip (SoC) is the most important trend to hit the semiconductor industry since the invention of microprocessors. SoC is the key technology driving smaller, faster, cheaper electronic systems, and is highly valued by users of semiconductors as they strive to add value to their products.”

1-12 Wafer Lots

The 24-wafer lot may remain the most cost-effective batch size for low-mix fabs, but for high-mix lines 12-wafer lots are now anticipated even for 300mm wafers. For 450mm wafers, the industry needs to re-consider “the wafer is the batch” as a manufacturing strategy. The 2013 ITRS chapter on Factory mentions in Table 5 that by the year 2019 “Single Wafer Lot Manufacturing System as an option” will likely be needed by some fabs. Perhaps a 1-5 wafer carrier and interface would be a way for an Automated Material Handling System (AMHS) to link discrete OEM tools as an evolution of current 300mm FOUP designs.

However, a true single-wafer fab line would be the realization of a revolution started over twenty years ago when the MMST Program was a $100M+ 5-year R&D effort funded by DARPA, the U.S. Air Force, and Texas Instruments, which developed a 0.35μm double-level-metal CMOS fab technology (with a three-day cycle time). In the last decade BlueShift Technologies was started and stopped to provide such revolutionary technology for vacuum-robot-lines to connect single-wafer chambers all with a common physical interface.

Lean manufacturing approaches should work well with high-mix product fabs, in addition to providing more efficient consumption of consumables in general. In specific, when lean manufacturing is combined with small batch sizes—minimally the single wafer—there is tremendous improvement in cycle-time.

Achieving precise registration accuracy is a factor of two related variables: web tension and transport velocity.

BY BIPIN SEN, Bosch Rexroth, Hoffman Estates, IL

One of the brightest developments in electronics is Organic Light Emitting Diode (OLED) TVs, which are attracting consumers with their eye-popping colors and super- thin designs. Unlike the components found in traditional flat-screen display technology, OLEDs use thin, flexible sheets of material that emit their own light and are produced using a technique similar to inkjet or sheet-feed printing.

Introduced to the consumer market only a few years ago, OLEDs are still relatively costly to manufacture in large sizes due to limitations in both shadow-mask deposition methods, and in newer laser annealing and inkjet printing techniques. To scale up large area display production economically, printed electronics manufacturers are seeing the benefits of another production method — namely, digital roll-to-roll web processing.

Like an inkjet printer deposits ink on sheets of paper, a digital roll-to-roll press patterns thin-film transistors and other devices directly onto large organic, flexible substrates. But unlike slower sheet-fed digital printing, the substrate in a roll-to-roll press is supplied from an infeed reel through the printing section onto an outfeed reel in one continuous inline web. An array of piezo- electric printheads deposit the ink — comprised of a conductive organic solution — on the substrate at precise locations. In roll-to-roll web processing, electroluminescent materials or other microcrys- talline layers are deposited on substrate at slower speeds, on the order of 10 to 100 feet (3 to 30 meters) per minute.

The speed of the roll-to-roll process reduces the cost of fabrication dramatically—but several challenges must be overcome to make it pay off.

Fast speeds create big challenges

Similar to how Sunday newspaper comics require precise color registration to keep images from blurring, printed electronics require far tighter registration. Tolerances for applications such as Thin-Film Transistors (TFTs) or OLEDs require registration smaller than 10 microns. High-speed, high-resolution cameras measure registration accuracy and provide input to the control system. To ensure that degree of accuracy, precise web tension control is required.

Achieving precise registration accuracy is a factor of two related variables: web tension and transport velocity.

Web transport control ensures proper uniform tension on the substrate web as it travels through the process. Because the substrate changes properties in response to force loading, changes in tension affect the stability of deposited materials. Substrate expansion causes cracks, broken traces, short circuiting and layer delamination. Changes in web velocity in the print zone affect registration, thickness and resolution of fine lines.

As the web travels downstream, constant tension must be maintained in each tension zone, which
is defined as an isolated area in a machine where constant tension must be maintained appropriate to the process being performed in that area. A roll- to-roll press has several tension zones. Problems occur when a change is made in one tension zone and no change is needed in other areas. When tension control is coupled between all zones, a change in one creates a cascade of changes in others, impacting the stability of the entire web.

FIGURE 1 shows how instability affects a web traveling at five meters per second with two successive tension controllers for two tension zones. A command for a step change tension reduction is sent to the green zone controllers.

FIGURE 1. Tension instability.

FIGURE 1. Tension instability.

No change is required in the upstream blue zone. But because the web is continuous, the tension disturbance is carried back to the blue zone, which causes the blue controller to compensate. In turn, this change affects the downstream green zone, sending jitter back to the blue zone. This back and forth jitter takes about 85 seconds to settle down. The web tension finally stabilizes in about 90 seconds. During that time, the machine is yielding waste product.

The challenge of tension adjustment

In an ideal world, web instability would never occur because tension adjustment would never be needed. But tension adjustment is necessary due to several mechanical factors:

  • Oscillations caused by mechanical misalignments
  • Differing inertial response (lag) of mechanical elements during web acceleration
  • Out-of-round unwind and tension rolls
  • Slipping through nip rolls
  • Over aggressive web-guide correction

Several technical process and control issues also affect tension: tension set point changes, phase offset on driven rolls, tension bleed from one zone to another, and, of course, thermal effect (contraction/expansion) as the substrate passes through various processes.

The factors requiring tension adjustment cannot all be eliminated. Variance in any one factor in a zone necessitates changes in tension control and web speed. Consequently, with coupled tension zone control, jitter is inevitable in a continuous web where the controllers cause a feedback loop.

The benefits of decoupled controllers

There is a solution: Decouple each tension zone, allowing each controller to operate independently.
This has been accomplished in digital printing applications using Bosch Rexroth controllers incor- porating a unique tension decoupling function block. As the name implies, the function block allows tension control for each zone to operate independently. As a result, tension changes can be isolated in one zone without affecting tension change in other areas.

The result can be seen in FIGURE 2. In this example, the press uses two successive controllers. But now the step change signaled by the green section controller doesn’t create a cascade effect upstream. Along with decoupling to prevent feedback, the Rexroth controller initiates a response to step reduction in tension control in one-fourth the time compared to typical controllers.

FIGURE 2. Improved tension control.

FIGURE 2. Improved tension control.

With the Rexroth solution, tension can be controlled for up to eight axes. One or multiple points can be selected to be left uncontrolled. At the selected axis, line speed is held constant. At a standstill, web tension can be maintained. In fact, Rexroth multi-axis tension control increases stand-still web tension accuracy by a factor of two to four. Achieving the desired standstill web tension is also much faster. Without decoupling, a setpoint can be achieved in 13-14 seconds; with decoupling, it takes three to four seconds.

During acceleration, tension control decoupling ensures the web is stable as soon as full production speed is reached, compared to a delay of five seconds or longer with coupled control. And when tension setpoint changes occur during runtime, the transient response with decoupling takes about one second, compared to about four seconds with coupled control.

Not unlike digital printing, the adoption of roll-to-roll web printing will accelerate as the technology demonstrates its ability to provide high accuracy at high speeds.

The global semiconductor materials market increased 3 percent in 2014 compared to 2013 while worldwide semiconductor revenues increased 10 percent. Revenues of $44.3 billion mark the first increase in the semiconductor materials market since 2011.

Total wafer fabrication materials and packaging materials were $24.0 billion and $20.4 billion, respectively. Comparable revenues for these segments in 2013 were $22.7 billion for wafer fabrication materials and $20.4 billion for packaging materials. The wafer fabrication materials segment increased 6 percent year-over-year, while the packaging materials segment remained flat. However, if bonding wire were excluded from the packaging materials segment, the segment increased more than 4 percent last year. The continuing transition to copper-based bonding wire from gold is negatively impacting overall packaging materials revenues.

For the fifth consecutive year, Taiwan was the largest consumer of semiconductor materials due to its large foundry and advanced packaging base, totaling $9.8 billion. Japan claimed the second spot during the same time. Annual revenue growth was the strongest in the Taiwan market. The materials market in North America had the second largest increase at 5 percent, followed by China, South Korea and Europe. The materials markets in Japan and Rest of World were flat relative to 2013 levels. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.)

Region 2013 2014 % Change
Taiwan

8.91

9.58

8%
Japan

7.17

7.19

0%
South Korea

6.87

7.03

2%
Rest of World

6.64

6.66

0%
China

5.66

5.83

3%
North America

4.76

4.98

5%
Europe

3.04

3.08

1%
Total

43.05

44.35

3%

Source: SEMI, April 2015
Note: Figures may not add due to rounding.

The Material Market Data Subscription (MMDS) from SEMI provides current revenue data along with seven years of historical data and a two-year forecast.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced worldwide sales of semiconductors reached $27.8 billion for the month of February 2015, an increase of 6.7 percent from February 2014 when sales were $26.0 billion. Global sales from February 2015 were 2.7 percent lower than the January 2015 total of $28.5 billion, reflecting seasonal trends. Regionally, sales in the Americas increased by 17.1 percent compared to last February to lead all regional markets. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry maintained momentum in February, posting its 22nd straight month of year-to-year growth despite macroeconomic headwinds,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales of DRAM and Analog products were particularly strong, notching double-digit growth over last February, and the Americas market achieved its largest year-to-year sales increase in 12 months.”

Regionally, year-to-year sales increased in the Americas (17.1 percent) and Asia Pacific (7.6 percent), but decreased in Europe (-2.0 percent) and Japan (-8.8 percent). Sales decreased compared to the previous month in Europe (-1.6 percent), Asia Pacific (-2.2 percent), Japan (-2.3 percent), and the Americas (-4.4 percent).

“While we are encouraged by the semiconductor market’s sustained growth over the last two years, a key driver of our industry’s continued success is free trade,” Neuffer continued. “A legislative initiative called Trade Promotion Authority (TPA) has paved the way for opening markets to American goods and services for decades, helping to give life to nearly every U.S. free trade agreement in existence, but it expired in 2007. With several important free trade agreements currently under negotiation, Congress should swiftly re-enact TPA.”

February 2015
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 6.51 6.23 -4.4%
Europe 2.95 2.90 -1.6%
Japan 2.62 2.56 -2.3%
Asia Pacific 16.47 16.10 -2.2%
Total 28.55 27.79 -2.7%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 5.32 6.23 17.1%
Europe 2.96 2.90 -2.0%
Japan 2.81 2.56 -8.8%
Asia Pacific 14.96 16.10 7.6%
Total 26.04 27.79 6.7%
Three-Month-Moving Average Sales
Market Sep/Oct/Nov Dec/Jan/Feb % Change
Americas 6.53 6.23 -4.6%
Europe 3.19 2.90 -9.2%
Japan 2.93 2.56 -12.7%
Asia Pacific 17.12 16.10 -6.0%
Total 29.77 27.79 -6.7%

Consider these eight issues where the packaging team should be closely involved with the circuit design team.

BY JOHN T. MACKAY, Semi-Pac, Inc., Sunnyvale, CA

Today’s integrated circuit designs are driven by size, performance, cost, reliability, and time- to-market. In order to optimize these design drivers, the requirements of the entire system should be considered at the beginning of the design cycle—from the end system product down to the chips and their packages. Failure to include packaging in this holistic view can result in missing market windows or getting to market with a product that is more costly and problematic to build than an optimized product.

Chip design

As a starting consideration, chip packaging strategies should be developed prior to chip design completion. System timing budgets, power management, and thermal behavior can be defined at the beginning of the design cycle, eliminating the sometimes impossible constraints that are given to the package engineering team at the end of the design. In many instances chip designs end up being unnecessarily difficult to manufacture, have higher than necessary assembly costs and have reduced manufacturing yields because the chip design team used minimum design rules when looser rules could have been used.

Examples of these are using minimum pad-to-pad spacing when the pads could have been spread out or using unnecessary minimum metal to pad clearance (FIGURE 1). These hard taught lessons are well understood by the large chip manufacturers, yet often resurface with newer companies and design teams that have not experienced these lessons. Using design rule minimums puts unnecessary pressure on the manufacturing process resulting in lower overall manufacturing yields.

Packaging 1

FIGURE 1. In this image, the bonding pads are grouped in tight clusters rather than evenly distributed across the edge of the chip. This makes it harder to bond to the pads and requires more-precise equipment to do the bonding, thus unnecessarily increasing the assembly cost and potentially impacting device reliability.

Packaging

Semiconductor packaging has often been seen as a necessary evil, with most chip designers relying on existing packages rather than package customization for optimal performance. Wafer level and chipscale packaging methods have further perpetuated the belief that the package is less important and can be eliminated, saving cost and improving performance. The real fact is that the semiconductor package provides six essential functions: power in, heat out, signal I/O, environmental protection, fan-out/compatibility to surface mounting (SMD), and managing reliability. These functions do not disappear with the implementation of chipscale packaging, they only transfer over to the printed circuit board (PCB) designer. Passing the buck does not solve the problem since the PCB designers and their tools are not usually expected to provide optimal consideration to the essential semiconductor die requirements.

Packages

Packaging technology has considerably evolved over the past 40 years. The evolution has kept pace with Moore’s Law increasing density while at the same time reducing cost and size. Hermetic pin grid arrays (PGAs) and side-brazed packages have mostly been replaced by the lead-frame-based plastic quad flat packs (QFP). Following those developments, laminate based ball grid arrays (BGA), quad flat pack no leads (QFN), chip scale and flip-chip direct attach became the dominate choice for packages.

The next generation of packages will employ through-silicon vias to allow 3D packaging with chip-on-chip or chip-on-interposer stacking. Such approaches promise to solve many of the packaging problems and usher in a new era. The reality is that each package type has its benefits and drawbacks and no package type ever seems to be completely extinct. The designer needs to have an in-depth understand of all of the packaging options to determine how each die design might benefit or suffer drawbacks from the use of any particular package type. If the designer does not have this expertise, it is wise to call in a packaging team that possesses this expertise.

Miniaturization

The push to put more and more electronics into a smaller space can inadvertently lead to unnec- essary packaging complications. The ever increasing push to produce thinner packages is a compromise against reliability and manufacturability. Putting unpackaged die on the board definitely saves space and can produce thinner assemblies such as smart card applications. This chip-on-board (COB) approach often has problems since the die are difficult to bond because of their tight proximity to other components or have unnecessarily long bond wires or wires at acute angles that can cause shorts as PCB designers attempt to accommodate both board manufacturing line and space realities with wire bond requirements.

Additionally, the use of minimum PCB design rules can complicate the assembly process since the PCB etch-process variations must be accommodated. Picking the right PCB manufacturer is important too as laminate substrate manufacturers and standard PCB shops are most often seen as equals by many users. Often, designers will use material selections and metal systems that were designed for surface mounting but turn out to be difficult to wire bond. Picking a supplier that makes the right metallization tradeoffs and process disciplines is important in order to maximize manufacturing yields

Power

Power distribution, including decoupling capaci- tance and copper ground and power planes have been mostly a job for the PCB designer. This is a wonder to most users as to why decoupling is rarely embedded into the package as a complete unit. Cost or package size limitations are typically the reasons cited as to why this isn’t done. The reality is that semiconductor component suppliers usually don’t know the system requirements, power fluctuation tolerance and switching noise mitigation in any particular installation. Therefore power management is left to the system designer at the board level.

Thermal Management

Miniaturization results in less volume and heat spreading to dissipate heat. Often, there is no room or project funds available for heat sinks. Managing junction temperature has always been the job of the packaging engineer who must balance operating and ambient temperatures and packaging heat flow.

Once again, it is important to develop a thermal strategy early in the design cycle that includes die specifics, die attachment material specification, heat spreading die attachment pad, thermal balls on BGA and direct thermal pad attachment during surface mount.

Signal input/output

Managing signal integrity has always been the primary concern of the packaging engineer. Minimizing parasitics, crosstalk, impedance mismatch, transmission line effects and signal atten- uation are all challenges that must be addressed. The package must handle the input/output signal requirements at the desired operating frequencies without a significant decrease in signal integrity. All packages have signal characteristics specific to the materials and package designs.

Performance

There are a number of factors that impact perfor- mance including: on-chip drivers, impedance matching, crosstalk, power supply shielding, noise and PCB materials to name a few. The performance goals must be defined at the beginning of the design cycle and tradeoffs made throughout the design process.

Environmental protection

The designer must also be aware that packaging choices have an impact on protecting the die from environmental contamination and/or damage. Next- generation chip-scale packaging (CSP) and flip chip technologies can expose the die to contami- nation. While the fab, packaging and manufacturing engineers are responsible for coming up with solutions that protect the die, the design engineer needs to understand the impact that these packaging technologies have on manufacturing yields and long-term reliability.

Involve your packaging team

Hopefully, these points have provided some insights on how packaging impacts many aspects of design and should not be relegated to just picking the right package at the end of the chip design. It is important that your packaging team be involved in the design process from initial specification through the final design review.

In today’s fast moving markets, market windows are shrinking so time to market is often the important differentiator between success and failure. Not involving your packaging team early in the design cycle can result in costly rework cycles at the end of the project, having manufacturing issues that delay the product introduction or, even worse, having impossible problems to solve that could have been eliminated had packaging been considered at the beginning of the design cycle.

System design incorporates many different design disciplines. Most designers are proficient in their domain specialty and not all domains. An important byproduct of these cross-functional teams is the spreading of design knowledge throughout the teams, resulting in more robust and cost effective designs.