Category Archives: Packaging Materials

U.S. semiconductor chemical suppliers lost market share to Japanese and European competitors in every major segment over the past decade, according to the report entitled “Chemicals and Materials for Sub-100 nm IC Manufacturing,” recently published by The Information Network (www.theinformationnet.com), a New Tripoli, PA-based market research company.

“Despite a shift in semiconductor manufacturing from the U.S. to Japan, to Korea, and then to China, the chemical supply chain is still dominated by U.S., Japanese, and European chemical companies,” noted Dr. Robert Castellano, president of The Information Network.

Within this supply chain, U.S. chemical manufacturers lost market share in every major chemical sector over the past decade, according to The Information Network’s report. Specific details for the top three suppliers in each of the sectors are listed in the table below:

chemicals

 

The first sector is one of the more interesting, because GlobalWafers, a Taiwanese company, acquired SunEdison in late 2016 making it the first company to break into the top three that wasn’t from headquartered in the U.S., Japan, or Europe,” added Dr. Castellano.

According to the report, the company held a 13.5% share in 2004 (when it was called MEMC) but it dropped to 10.1% in 2016 (when it was called SunEdison).

In each of the other sectors, the U.S. company dropped in market share. In the liquid chemicals sector, KMG Chemicals dropped from first place to third place, but gained market share because of its acquisition of OM Chemicals in 2014.

Worldwide silicon wafer area shipments increased during the third quarter 2017 when compared to second quarter 2017 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,997 million square inches during the most recent quarter, a 0.7 percent increase from the record 2,978 million square inches shipped during the previous quarter. New quarterly total area shipments are 9.8 percent higher than third quarter 2016 shipments and continue to ship at their highest recorded quarterly level.

“Global silicon wafer shipment volumes surpassed record levels for the sixth quarter in a row, resulting in a new historical high,” said Chungwei (C.W.) Lee (李崇偉), chairman of SEMI SMG and spokesman, VP, Corporate Development and chief auditor of GlobalWafers (環球晶圓).  “While silicon demand is strong, silicon pricing remains well below pre-downturn levels.”

Silicon* Area Shipment Trends

Source: SEMI (www.semi.org), November 2017
Millions of Square Inches
2Q2016
3Q2016
4Q2016
1Q2017
2Q2017
3Q2017
Total
2,706
2,730
2,764
2,858
2,978
2,997

*Semiconductor applications only

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

 

The RC delay issues started a few nodes ago, and the problems are becoming worse.

BY ZSOLT TOKEI, imec, Leuven, Belgium

With the 7nm technology node in the development phase and the 5nm node moving into development, transistor scaling gets ever more complex. On top of that, the performance benefits gained at the front-end-of-line (i.e., the transistors) can easily be undone if the back-end-of-line can’t come along. BEOL processing involves the creation of stacked layers of Cu wires that electrically interconnect the transistors in the chip. Today, high-end logic chips easily have 12 to 15 levels of Cu wires. With each technology node, this Cu wiring scheme becomes more complex, mainly because there are more transistors to connect with an ever tighter pitch. Shrinking dimensions also means the wires have a reduced cross-sectional area, which drives up the resistance-capacitance product (RC) of the interconnect system. And this results in strongly increasing signal delay. The RC delay issues started a few nodes ago, and the problems are becoming worse. For example, a delay of more than 30% is expected when moving from the 10nm to the 7nm node.

The current BEOL flow

Cu-based dual damascene has been the workhorse process flow for interconnects since its introduction in the mid 1990s. A simple dual damascene flow starts with the deposition of a low-k dielectric material on a structure. These low-k films are designed to reduce the capacitance and the delay in the ICs. In a next step, this dielectric layer is covered with an oxide and a resist, and vias and trenches are formed using lithography and etch steps. These vias connect one metal layer with the layer above or below. Then, a metallic barrier layer is added to prevent Cu atoms from migrating into the low-k materials (FIGURE 1). The barrier layers are deposited with physical vapor deposition, using materials such as tantalum and tantalum nitride, and subsequently coated by a Cu seed barrier. In a final step, this structure is electroplated by Cu in a chemical mechanical polishing (CMP) step.

Screen Shot 2017-11-07 at 11.49.49 AM

A 5nm technology full dual damascene module

The semiconductor industry is hugely in favor of extending the current dual damascene technology as long as possible before moving to a new process. And this starts with incremental changes to the current technology, which should suffice for further scaling to at least the 5nm technology node. Researchers at imec have demonstrated a full dual damascene module for the 5nm technology node. At this node, the BEOL process becomes extremely complex, and interconnects are designed at very tight pitches. For example, a 50% area scaling in logic and 60% scaling of an SRAM cell from 7nm to 5nm results in a gate pitch at around 42nm and an intermediate first routing metal at 32nm pitch (or 16nm half pitch, which is half the distance between identical features). In these BEOL layers, trenches are created which are then filled with metal in a final metallization step. In order to create electrically functional lines, perpendicular block layers to the trenches are added, where metal traces are not formed. One of the many challenges to scaling the interconnects relates to the patterning options. Patterning these tight pitch layers is no longer possible by using single immersion lithography and direct etch steps. Only multi-patterning – which is known to be very costly and complex – is possible either by immersion or by EUV or by a combination of immersion and EUV exposures to form a single metal layer. At IITC, imec showed a full integration flow using multi-patterning, which enables the patterning of tight-pitch metal-cut (the blocks), and effectively scaling the trench critical dimension to 12nm at 16nm half pitch. The researchers also looked at the reliability, for example at electromigration issues caused by the movement of atoms in the interconnect wires. They demonstrated the ability of imec’s Cu metallization scheme at 16nm critical dimension with extendibility to 12nm width, and investigated full ruthenium (Ru) metallization as copper replacement.

Scaling the BEOL beyond the 5nm node

For the technology nodes below the 5nm, the team of imec is investigating a plethora of options and comparing their merits. Options include new materials for conductors and dielectrics, barrier layers, vias, and new ways to deposit them; innovative BEOL architectures for making 2.5D/3D structures; new patterning schemes; co-optimization of system and technology, etc.

For example, to achieve manufacturable processes and at the same time control the RC delay, scaling boosters, such as fully self-aligned vias, are increasingly being used. Via alignment is a critical step in the BEOL process, as it defines the contact area between subsequent interconnect levels. Any misalignment impacts both resistance and reliability. Imec’s team has shown the necessity of using a fully self-aligned via to achieve overlay specifications, and proposed a process flow for 12nm half pitch structures.

Also, self-assembled monolayers (SAMs) open routes to new dielectric and conductor schemes. SAMs composed of sub-1nm organic chains and terminated with desired functional groups can help engineering thin-film dielectric and metal interfaces, and can strongly inhibit interfacial diffusion. The use of SAMs has been a topic of research for the past ten years. Imec has now moved this promising concept from lab to fab, and combined SAMs with a barrier/liner/metallization scheme on a full wafer. The researchers investigated the implica- tions on the performance and scaling ability of this process flow, and demonstrated a ~18% reduction in the RC of 22nm half-pitch dual damascene intercon- nects, due to a better interface and thinner barrier.

For conventional BEOL metallization, a barrier layer is coated by a Cu seed barrier, and this structure is electroplated with low-resistive Cu, which acts as the conductor. But when moving to sub-10nm interconnects, the resistivity of Cu continues to increase. At the same time, the diffusion barrier – which is highly resistive and difficult to scale – is taking up more space, thereby increasing the overall resistance of the barrier/Cu structure. Therefore, alternative metals are being investigated that could possibly serve as a replacement for Cu and do not require a diffusion barrier. Among the potential candidates, such as Co, Ni, Mo, etc., platinum-group metals, especially ruthenium (Ru), have shown great promise due to their low bulk resistivity and resistance to oxidation. They also have a high melting point which can result in better electromigration behavior (FIGURE 2). Imec has realized Ru nanowires with 58nm2 cross section area. The nanowires exhibit low resistivity and robust wafer-level reliability. For example, a very high current carrying capacity with fusing currents as high as 720MA/cm2 was demonstrated.

Screen Shot 2017-11-07 at 11.50.00 AM

At the 2017 IITC conference, this author was invited to take part in a panel discussion, organized by Applied Materials, to discuss the latest developments in metallization at single-digit nodes, the challenges and bottlenecks arising at these very small dimensions, and new application-driven requirements. Distinguished speakers from the technical field reviewed viable solutions for extending the current technology and alternative options were discussed. From the discussion it is clear that the biggest immediate benefit can be found in the area of conductors – both from the material side as well as design. Indeed, it is driving the replacement of copper at specific metallization levels. Other avenues – such as dielectric innovations, functionality in the BEOL or 2D materials – remain interesting options for the R&D pipeline.

As an option that is further out, spin wave propagation in conductors is an alternative signaling to traditional electron based propagation.

Adding additional functionality in the BEOL

In the future, more and more technology options may get dictated by the requirements of systems or even applications. This could result in a separate technology for e.g. high-performance computing, low-power mobile communication, chips for use in medical applications, or dedicated chips for IoT sensors. Along the same lines, imec is investigating the benefits of introducing additional functionality in the BEOL.

More specifically, imec is evaluating the possibility of integrating thin-film organic transistors – with typically low-leakage level – into the BEOL interconnect circuitry of Si FinFETs. The potential advantages of fabricating them together are mainly a reduced power consumption and improved area saving. A variety of circuits can fully utilize the benefits of this hybrid processing, including portable applications, eDRAM, displays and FPGA applications. As a concrete example, imec researchers are currently merging imec’s expertise in BEOL technologies and in thin-film-based flat panel displays, thereby opening opportunities for new applications…

A mineral discovered in Russia in the 1830s known as a perovskite holds a key to the next step in ultra-high-speed communications and computing.

Researchers from the University of Utah’s departments of electrical and computer engineering and physics and astronomy have discovered that a special kind of perovskite, a combination of an organic and inorganic compound that has the same structure as the original mineral, can be layered on a silicon wafer to create a vital component for the communications system of the future. That system would use the terahertz spectrum, the next generation of communications bandwidth that uses light instead of electricity to shuttle data, allowing cellphone and internet users to transfer information a thousand times faster than today.

The new research, led by University of Utah electrical and computer engineering professor Ajay Nahata and physics and astronomy Distinguished Professor Valy Vardeny, was published Monday, Nov. 6 in the latest edition of Nature Communications.

The terahertz range is a band between infrared light and radio waves and utilizes frequencies that cover the range from 100 gigahertz to 10,000 gigahertz (a typical cellphone operates at just 2.4 gigahertz). Scientists are studying how to use these light frequencies to transmit data because of its tremendous potential for boosting the speeds of devices such as internet modems or cell phones.

Nahata and Vardeny uncovered an important piece of that puzzle: By depositing a special form of multilayer perovskite onto a silicon wafer, they can modulate terahertz waves passing through it using a simple halogen lamp. Modulating the amplitude of terahertz radiation is important because it is how data in such a communications system would be transmitted.

Previous attempts to do this have usually required the use of an expensive, high-power laser. What makes this demonstration different is that it is not only the lamp power that allows for this modulation but also the specific color of the light. Consequently, they can put different perovskites on the same silicon substrate, where each region could be controlled by different colors from the lamp. This is not easily possible when using conventional semiconductors like silicon.

“Think of it as the difference between something that is binary versus something that has 10 steps,” Nahata explains about what this new structure can do. “Silicon responds only to the power in the optical beam but not to the color. It gives you more capabilities to actually do something, say for information processing or whatever the case may be.”

Not only does this open the door to turning terahertz technologies into a reality — resulting in next-generation communications systems and computing that is a thousand times faster — but the process of layering perovskites on silicon is simple and inexpensive by using a method called “spin casting,” in which the material is deposited on the silicon wafer by spinning the wafer and allowing centrifugal force to spread the perovskite evenly.

Vardeny says what’s unique about the type of perovskite they are using is that it is both an inorganic material like rock but also organic like a plastic, making it easy to deposit on silicon while also having the optical properties necessary to make this process possible.

“It’s a mismatch,” he said. “What we call a ‘hybrid.'”

Nahata says it’s probably at least another 10 years before terahertz technology for communications and computing is used in commercial products, but this new research is a significant milestone to getting there.

“This basic capability is an important step towards getting a full-fledged communications system,” Nahata says. “If you want to go from what you’re doing today using a modem and standard wireless communications, and then go to a thousand times faster, you’re going to have to change the technology dramatically.”

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $107.9 billion for the third quarter of 2017, marking the industry’s highest-ever quarterly sales and an increase of 10.2 percent compared to the previous quarter. Sales for the month of September 2017 were $36.0 billion, an increase of 22.2 percent over the September 2016 total of $29.4 billion and 2.8 percent more than the previous month’s total of $35.0 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

highest ever sales

“Global semiconductor sales increased sharply year-to-year in September, and year-to-date sales through September are more than 20 percent higher than at the same point last year,” said John Neuffer, SIA president and CEO. “The industry posted its highest-ever quarterly sales in Q3, and the global market is poised to reach its highest-ever annual revenue in 2017.”

Regionally, year-to-year and month-to-month sales increased in September across all markets: the Americas (40.7 percent year-to-year/5.9 percent month-to-month), China (19.9 percent/2.5 percent), Europe (19.0 percent/1.8 percent), Asia Pacific/All Other (16.8 percent/1.9 percent), and Japan (11.9 percent/0.5 percent).

“The Americas market continued to stand out, notching its largest year-to-year sales increase in more than seven years,” Neuffer said. “Standouts among semiconductor product categories included memory products like DRAM and NAND flash, both of which posted major year-to-year growth in September, as well as Logic products, which enjoyed double-digit growth year-to-year.”

Scientists at the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) reported significant advances in the thermoelectric performance of organic semiconductors based on carbon nanotube thin films that could be integrated into fabrics to convert waste heat into electricity or serve as a small power source.

The research demonstrates significant potential for semiconducting single-walled carbon nanotubes (SWCNTs) as the primary material for efficient thermoelectric generators, rather than being used as a component in a “composite” thermoelectric material containing, for example, carbon nanotubes and a polymer. The discovery is outlined in the new Energy & Environmental Science paper, Large n- and p-type thermoelectric power factors from doped semiconducting single-walled carbon nanotube thin films.

“There are some inherent advantages to doing things this way,” said Jeffrey Blackburn, a senior scientist in NREL’s Chemical and Materials Science and Technology center and co-lead author of the paper with Andrew Ferguson. These advantages include the promise of solution-processed semiconductors that are lightweight and flexible and inexpensive to manufacture. Other NREL authors are Bradley MacLeod, Rachelle Ihly, Zbyslaw Owczarczyk, and Katherine Hurst. The NREL authors also teamed with collaborators from the University of Denver and partners at International Thermodyne, Inc., based in Charlotte, N.C.

Ferguson, also a senior scientist in the Chemical and Materials Science and Technology center, said the introduction of SWCNT into fabrics could serve an important function for “wearable” personal electronics. By capturing body heat and converting it into electricity, the semiconductor could power portable electronics or sensors embedded in clothing.

Blackburn and Ferguson published two papers last year on SWCNTs, and the new research builds on their earlier work. The first paper, in Nature Energy, showed the potential that SWCNTs have for thermoelectric applications, but the films prepared in this study retained a large amount of insulating polymer. The second paper, in ACS Energy Letters, demonstrated that removing this “sorting” polymer from an exemplary SWNCT thin film improved thermoelectric properties.

The newest paper revealed that removing polymers from all SWCNT starting materials served to boost the thermoelectric performance and lead to improvements in how charge carriers move through the semiconductor. The paper also demonstrated that the same SWCNT thin film achieved identical performance when doped with either positive or negative charge carriers. These two types of material–called the p-type and the n-type legs, respectively–are needed to generate sufficient power in a thermoelectric device. Semiconducting polymers, another heavily studied organic thermoelectric material, typically produce n-type materials that perform much worse than their p-type counterparts. The fact that SWCNT thin films can make p-type and n-type legs out of the same material with identical performance means that the electrical current in each leg is inherently balanced, which should simplify the fabrication of a device. The highest performing materials had performance metrics that exceed current state-of-the-art solution-processed semiconducting polymer organic thermoelectrics materials.

“We could actually fabricate the device from a single material,” Ferguson said. “In traditional thermoelectric materials you have to take one piece that’s p-type and one piece that’s n-type and then assemble those into a device.”

Silicon has provided enormous benefits to the power electronics industry. But performance of silicon-based power electronics is nearing maximum capacity.

Enter wide bandgap (WBG) semiconductors. Seen as significantly more energy-efficient, they have emerged as leading contenders in developing field-effect transistors (FETs) for next-generation power electronics. Such FET technology would benefit everything from power-grid distribution of renewable-energy sources to car and train engines.

Diamond is largely recognized as the most ideal material in WBG development, owing to its superior physical properties, which allow devices to operate at much higher temperatures, voltages and frequencies, with reduced semiconductor losses.

A main challenge, however, in realizing the full potential of diamond in an important type of FET — namely, metal-oxide-semiconductor field-effect transistors (MOSFETs) — is the ability to increase the hole channel carrier mobility. This mobility, related to the ease with which current flows, is essential for the on-state current of MOSFETs.

Researchers from France, the United Kingdom and Japan incorporate a new approach to solve this problem by using the deep-depletion regime of bulk-boron-doped diamond MOSFETs. The new proof of concept enables the production of simple diamond MOSFET structures from single boron-doped epilayer stacks. This new method, specific to WBG semiconductors, increases the mobility by an order of magnitude. The results are published this week in Applied Physics Letters, from AIP Publishing.

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

In a typical MOSFET structure, an oxide layer and then a metal gate are formed on top of a semiconductor, which in this case is diamond. By applying a voltage to the metal gate, the carrier density, and hence the conductivity, of the diamond region just under the gate, the channel, can be changed dramatically. The ability to use this electric “field-effect” to control the channel conductivity and switch MOSFETS from conducting (on-state) to highly insulating (off-state) drives their use in power control applications. Many of the diamond MOSFETs demonstrated to date rely on a hydrogen-terminated diamond surface to transfer positively charged carriers, known as holes, into the channel. More recently, operation of oxygen terminated diamond MOS structures in an inversion regime, similar to the common mode of operation of silicon MOSFETS, has been demonstrated. The on-state current of a MOSFET is strongly dependent on the channel mobility and in many of these MOSFET designs, the mobility is sensitive to roughness and defect states at the oxide diamond interface where unwanted carrier scattering occurs.

To address this issue, the researchers explored a different mode of operation, the deep-depletion concept. To build their MOSFET, the researchers deposited a layer of aluminum oxide (Al2O3) at 380 degrees Celsius over an oxygen-terminated thick diamond epitaxial layer. They created holes in the diamond layer by incorporating boron atoms into the layer. Boron has one less valence electron than carbon, so including it leaves a missing electron which acts like the addition of a positive charge, or hole. The bulk epilayer functioned as a thick conducting hole channel. The transistor was switched from the on-state to the off-state by application of a voltage which repelled and depleted the holes — the deep depletion region. In silicon-based transistors, this voltage would have also resulted in formation of an inversion layer and the transistor would not have turned off. The authors were able to demonstrate that the unique properties of diamond, and in particular the large band gap, suppressed formation of the inversion layer allowing operation in the deep depletion regime.

“We fabricated a transistor in which the on-state is ensured by the bulk channel conduction through the boron-doped diamond epilayer,” said Julien Pernot, a researcher at the NEEL Institute in France and an author of the paper. “The off-state is ensured by the thick insulating layer induced by the deep-depletion regime. Our proof of concept paves the way in fully exploiting the potential of diamond for MOSFET applications.” The researchers plan to produce these structures through their new startup called DiamFab.

Pernot observed that similar principles of this work could apply to other WBG semiconductors. “Boron is the doping solution for diamond,” Pernot said, “but other dopant impurities would likely be suitable to enable other wide bandgap semiconductors to reach a stable deep-depletion regime.”

Fibers made of carbon nanotubes configured as wireless antennas can be as good as copper antennas but 20 times lighter, according to Rice University researchers. The antennas may offer practical advantages for aerospace applications and wearable electronics where weight and flexibility are factors.

The research appears in Applied Physics Letters.

The discovery offers more potential applications for the strong, lightweight nanotube fibers developed by the Rice lab of chemist and chemical engineer Matteo Pasquali. The lab introduced the first practical method for making high-conductivity carbon nanotube fibers in 2013 and has since tested them for use as brain implants and in heart surgeries, among other applications.

The research could help engineers who seek to streamline materials for airplanes and spacecraft where weight equals cost. Increased interest in wearables like wrist-worn health monitors and clothing with embedded electronics could benefit from strong, flexible and conductive fiber antennas that send and receive signals, Pasquali said.

The Rice team and colleagues at the National Institute of Standards and Technology (NIST) developed a metric they called “specific radiation efficiency” to judge how well nanotube fibers radiated signals at the common wireless communication frequencies of 1 and 2.4 gigahertz and compared their results with standard copper antennas. They made thread comprising from eight to 128 fibers that are about as thin as a human hair and cut to the same length to test on a custom rig that made straightforward comparisons with copper practical.

“Antennas typically have a specific shape, and you have to design them very carefully,” said Rice graduate student Amram Bengio, the paper’s lead author. “Once they’re in that shape, you want them to stay that way. So one of the first experimental challenges was getting our flexible material to stay put.”

Contrary to earlier results by other labs (which used different carbon nanotube fiber sources), the Rice researchers found the fiber antennas matched copper for radiation efficiency at the same frequencies and diameters. Their results support theories that predicted the performance of nanotube antennas would scale with the density and conductivity of the fiber.

“Not only did we find that we got the same performance as copper for the same diameter and cross-sectional area, but once we took the weight into account, we found we’re basically doing this for 1/20th the weight of copper wire,” Bengio said.

“Applications for this material are a big selling point, but from a scientific perspective, at these frequencies carbon nanotube macro-materials behave like a typical conductor,” he said. Even fibers considered “moderately conductive” showed superior performance, he said. Although manufacturers could simply use thinner copper wires instead of the 30-gauge wires they currently use, those wires would be very fragile and difficult to handle, Pasquali said.

“Amram showed that if you do three things right — make the right fibers, fabricate the antenna correctly and design the antenna according to telecommunication protocols — then you get antennas that work fine,” he said. “As you go to very thin antennas at high frequencies, you get less of a disadvantage compared with copper because copper becomes difficult to handle at thin gauges, whereas nanotubes, with their textile-like behavior, hold up pretty well.”

An oversupply of polysilicon will double in 2018 despite strong demand in solar and semiconductor markets, according to a report Opportunities in The Solar Cell Market For Thin Film Technology, recently published by The Information Network (www.theinformationnet.com), a New Tripoli, PA-based market research company.

Consumption of polysilicon is booming as the semiconductor industry, particularly DRAM and NAND, is reaching record revenue and shipment growth. Solar installations are also growing strongly, increasing 35.5% in 2016.

Nevertheless, increased capacity put in place by polysilicon incumbents and capacity growth of Chinese manufactures pegged to increase 35% in 2017 is giving rise to an oversupply that will grow from 7.1% in 2016 to 15.0% in 2018.

As shown in the Table below, the industry will see an oversupply of 76,000 metric tonnes in 2018.

  2016 2018 2020
       
New PV (MW) 78,260 86,909 101,361
Inventory Requirement (MW) 3,913 4,345 5,068
Inventory % of demand 5% 5% 5%
Total PV Module Shipments (MW) 82,173 91,254 106,429
Efficiency loss 3% 3% 3%
Total PV Cell Shipments (MW) 84,638 93,992 109,622
Thin Film Supply (MW) 4,696 4,606 4,460
Polysilicon Consumed (Tonne/MW) 5 5 5
Total Solar Poly Required (MT) 423,696 464,804 546,845
Poly demand from Semis (MT) 34,180 40,119 39,044
Total Poly Demand (MT) 457,876 504,923 585,889
Poly Supply (MT) 490,250 580,910 640,453
Over Supply (MT) 32,374 75,987 54,564
% Over Supply 7.1% 15.0% 9.3%
Source: The Information Network (www.theinformationnet.com)

“In addition to polysilicon capacity increases, the transition from slurry wire slicing to diamond wire is creating more silicon wafers by reducing kerf loss, adding to the oversupply noted Dr. Robert Castellano, President of The Information Network.

The Information Network is a consulting and market research company addressing the semiconductor, LCD, HDD, and solar industries.

To make continuous, strong and conductive carbon nanotube fibers, it’s best to start with long nanotubes, according to scientists at Rice University.

The Rice lab of chemist and chemical engineer Matteo Pasquali, which demonstrated its pioneering method to spin carbon nanotube into fibers in 2013, has advanced the art of making nanotube-based materials with two new papers in the American Chemical Society’s ACS Applied Materials and Interfaces.

The first paper characterized 19 batches of nanotubes produced by as many manufacturers to determine which nanotube characteristics yield the most conductive and strongest fibers for use in large-scale aerospace, consumer electronics and textile applications.

The researchers determined the nanotubes’ aspect ratio — length versus width — is a critical factor, as is the overall purity of the batch. They found the tubes’ diameters, number of walls and crystalline quality are not as important to the product properties.

Pasquali said that while the aspect ratio of nanotubes was known to have an influence on fiber properties, this is the first systematic work to establish the relationship across a broad range of nanotube samples. Researchers found that longer nanotubes could be processed as well as shorter ones, and that mechanical strength and electrical conductivity increased in lockstep.

The best fibers had an average tensile strength of 2.4 gigapascals (GPa) and electrical conductivity of 8.5 megasiemens per meter, about 15 percent of the conductivity of copper. Increasing nanotube length during synthesis will provide a path toward further property improvements, Pasquali said.

The second paper focused on purifying fibers produced by the floating catalyst method for use in films and aerogels. This process is fast, efficient and cost-effective on a medium scale and can yield the direct spinning of high-quality nanotube fibers; however, it leaves behind impurities, including metallic catalyst particles and bits of leftover carbon, allows less control of fiber structure and limits opportunities to scale up, Pasquali said.

“That’s where these two papers converge,” he said. “There are basically two ways to make nanotube fibers. In one, you make the nanotubes and then you spin them into fibers, which is what we’ve developed at Rice. In the other, developed at the University of Cambridge, you make nanotubes in a reactor and tune the reactor such that, at the end, you can pull the nanotubes out directly as fibers.

“It’s clear those direct-spun fibers include longer nanotubes, so there’s an interest in getting the tubes included in those fibers as a source of material for our spinning method,” Pasquali said. “This work is a first step toward that goal.”

The reactor process developed a decade ago by materials scientist Alan Windle at the University of Cambridge produces the requisite long nanotubes and fibers in one step, but the fibers must be purified, Pasquali said. Researchers at Rice and the National University of Singapore (NUS) have developed a simple oxidative method to clean the fibers and make them usable for a broader range of applications.

The labs purified fiber samples in an oven, first burning out carbon impurities in air at 500 degrees Celsius (932 degrees Fahrenheit) and then immersing them in hydrochloric acid to dissolve iron catalyst impurities.

Impurities in the resulting fibers were reduced to 5 percent of the material, which made them soluble in acids. The researchers then used the nanotube solution to make conductive, transparent thin films.

“There is great potential for these disparate techniques to be combined to produce superior fibers and the technology scaled up for industrial use,” said co-author Hai Minh Duong, an NUS assistant professor of mechanical engineering. “The floating catalyst method can produce various types of nanotubes with good morphology control fairly quickly. The nanotube filaments can be collected directly from their aerogel formed in the reactor. These nanotube filaments can then be purified and twisted into fibers using the wetting technique developed by the Pasquali group.”

Pasquali noted the collaboration between Rice and Singapore represents convergence of another kind. “This may well be the first time someone from the Cambridge fiber spinning line (Duong was a postdoctoral researcher in Windle’s lab) and the Rice fiber spinning line have converged,” he said. “We’re working together to try out materials made in the Cambridge process and adapting them to the Rice process.”