Category Archives: Packaging Materials

Researchers at North Carolina State University have developed a new approach for manipulating the behavior of cells on semiconductor materials, using light to alter the conductivity of the material itself.

“There’s a great deal of interest in being able to control cell behavior in relation to semiconductors – that’s the underlying idea behind bioelectronics,” says Albena Ivanisevic, a professor of materials science and engineering at NC State and corresponding author of a paper on the work. “Our work here effectively adds another tool to the toolbox for the development of new bioelectronic devices.”

The new approach makes use of a phenomenon called persistent photoconductivity. Materials that exhibit persistent photoconductivity become much more conductive when you shine a light on them. When the light is removed, it takes the material a long time to return to its original conductivity.

When conductivity is elevated, the charge at the surface of the material increases. And that increased surface charge can be used to direct cells to adhere to the surface.

“This is only one way to control the adhesion of cells to the surface of a material,” Ivanisevic says. “But it can be used in conjunction with others, such as engineering the roughness of the material’s surface or chemically modifying the material.”

For this study, the researchers demonstrated that all three characteristics can be used together, working with a gallium nitride substrate and PC12 cells – a line of model cells used widely in bioelectronics testing.

The researchers tested two groups of gallium nitride substrates that were identical, except that one group was exposed to UV light – triggering its persistent photoconductivity properties – while the second group was not.

“There was a clear, quantitative difference between the two groups – more cells adhered to the materials that had been exposed to light,” Ivanisevic says.

“This is a proof-of-concept paper,” Ivanisevic says. “We now need to explore how to engineer the topography and thickness of the semiconductor material in order to influence the persistent photoconductivity and roughness of the material. Ultimately, we want to provide better control of cell adhesion and behavior.”

A case study is presented based on the use of high throughput experimentation (HTE) for the discovery of new memory materials.

BY LARRY CHEN, MARK CLARK, CHARLENE CHEN, SUSAN CHENG and MILIND WELING, IMI Inc., San Jose, CA

The ever increasing demands for data translate into more sophisticated and specific thin film requirements for semiconductor materials. Each film layer has to not only demonstrate desired film properties, but also show good interfacial behavior with neighboring layers to contribute to the performance of the whole film stack or device. As a result, modern thin film material systems are including more elements from the periodic table with more complex compositions. The demand for short time to market has also increased, making the development of new materials even more difficult. In this paper, we present a case study of using high throughput experimentation (HTE) for the discovery of new memory materials. By using a combinatorial approach of sputtering technology, HTE can be applied to PVD chalcogenides and other materials targeted at memory semiconductors.
PVD background

Ever since the deposition of materials by magnetron sputtering was introduced by F. M. Penning, the technology has become a major method for industrial thin film deposition, which typically generates dense, hard, and robust thin film materials at relatively low production cost. The technology has been applied to major industries such as semiconductors, photovoltaics, optical coatings, displays, hard mechanical coatings, and so on. However, optimizing the magnetron sputtering processes has always been challenging to process and hardware design engineers, since material properties like density, crystalline structure, grain size, optical indices of a deposited film strongly depend on various process parameters, such as power, pressure, substrate temperature, sputter gas type, plasma type, sputter source to substrate distance, substrate bias, and pumping throughput. Additionally, the material properties heavily depend on the underlying layers, including the chosen substrate, below a film stack due to a texture effect in film structure and a formation of interfacial layers which comes from the intermixing of both materials. All the above parameters contribute to increasing the level of complexity of the development.

The semiconductor industry is constantly searching for new materials with unprecedented physical, optical, electrical, and mechanical properties, not only as a single film but also as a component of complex featured film stacks or functioning devices. This requires exploration of new materials not limited to pure or binary systems, but to ternary, quaternary systems and beyond. A very efficient solution to cope with the increasing complexity of development and the demand for short development time is a combinatorial approach.

The combinatorial approach can be defined as a process that couples the capability for parallel production of large arrays of diverse materials together with different high-throughput measurement techniques for various intrinsic and performance properties supported by data analytics for identifying lead materials [3]. For magnetron sputtering technology, the optimization of process param- eters has to be included as a major component of combinatorial approach. Considering all the multi-dimensional space of the development mentioned above, the combinatorial approach can be an excellent and efficient way of developing new materials in magnetron sputtering in terms of cost and time.

HTE methodology for PVD materials discovery

Platform Considerations As all process parameters in magnetron sputtering are somewhat correlated, it has been challenging for process engineers to come up with fully optimized process parameters for thin film production. In addition, semiconductor production facilities are typically optimized for consistent, efficient, high volume production of a single product at a time, and not for a wide range of simultaneous experiments. These factors make it challenging for memory manufacturers to test multiple materials, conditions and devices in an efficient manner, and without compromising either data quality or production throughput.

IMI’s high throughput experimentation (HTE) platform is set up for accelerated experimentation. Its combina- torial PVD tool typically has four sputter guns and one additional port at the center. All sputter guns can be equipped with various types of target materials including chalcogenides, puremetals, oxides, and nitrides, and each sputter source can be operated by different plasma modes independently, such as direct current (DC), pulsed direct current (PDC), and radio frequency (RF) with the ability to co-sputter with all four guns. The additional port at the center can be equipped with an ion beam source for ion beam assisted deposition, or ion beam cleaning, or an additional sputter gun which enables five gun co-sputtering operation. Process parameter windows can cover larger regimes than most production tool process parameters (Table 1).

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FIGURE 1 shows an example of a multi-target sputter chamber capable of controllably forming a variety of compounds in an array across a 300 mm substrate and an example substrate shown at right. The materials can also be deposited on a die-to-die basis (not shown) over a 300mm wafer test vehicle for direct device testing without the need for patterning. The effectiveness of the combinatorial screening can be increased by guiding the selection of material compositions using both semi-phenomenological and DFT-based modeling, as well as relating the experimental data to the results obtained from simulated annealing using ab-initio molecular dynamics and further DFT analysis of the simulated quasi-amorphous structures.

Deposition methodology

Two different methods can be used to deposit the combinatorial films of interest: site isolated spot and gradient approaches. For the site isolated spot approach, multiple numbers of spots were deposited on a substrate. Each individual spot represents a split condition from a design of experiment (DOE). Film composition can be controlled through the co-sputter of guns, which are equipped with targets consisting of different materials. Also, the process condition of each spot can be varied through the process parameter settings. All deposition conditions and procedures are fully automated.

In the gradient approach, non-uniform film in terms of composition and thickness is intentionally generated on top of a substrate by co-sputtering through an open large area aperture. A semi-empirical model is used for the control of non-uniformity. The modeling also helps in controlling the film composition throughout a target’s lifetime. In this approach, composition gradients and the thickness gradients can be generated by a single film deposition on a substrate. Theoretically, an infinite number of variations can be analyzed within a film, which is only limited by the spatial resolution of metrologies.

Characterization and device performance

Once films have been deposited via PVD, characterization can be carried out, including testing of physical, optical and electrical parameters. These can range from general film characteristics including composition, thickness and crystallinity, to device-specific electrical parameters such as leakage, threshold voltage, and On/ Off ratio.

Measuring and analyzing large numbers of data generated from HTE methodology can be time- consuming. By using the automated metrology tools and a unified database system, measurements and analysis steps can be expedited to limit bottlenecks and deliver data most efficiently. A multi-stage approach can also help to prioritize and focus experimental resources on the most promising candidates.

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HTE vs traditional methods

Key benefits of the HTE approach include the expedited learning cycle, cost reduction, and improved data quality. For semiconductor applications, a single 200mm or 300mm wafer can hold more than 30 splits, which can lead to a reduction in cycle of learning time (one device wafer instead of more than 30). Additionally, as all spots on a single wafer go through the same follow-up device fabrication steps together, data can be free from unexpected fluctuations of subsequent steps. Overall, the HTE approach can expedite the learning cycle by 5 ~ 10 times compared to single substrate based approach. A comparison of both HTE with traditional methods is summarized in Table 2.

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A case study in NVM

New materials for memory elements such as non-volatile memory (NVM) selectors must meet a wide range of performance parameters (FIGURE 3 shows a typical memory cell with the selector element called out), in order to reduce sneak currents and manage variability in memory arrays.

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Table 3 lists some of the key parameters desired in a memory selector material.

Of course, optimizing all of these parameters simultaneously in a single element or compound (and one that is practical for high volume memory manufacturing) is challenging. IMI’s HTE methodology enables rapid and simultaneous optimization of key trade-offs between performance, reliability and integration, in the quest for an ideal selector.

HTE for NVM selector materials

Use of a HTE methodology allows rapid screening of NVM selector candidate material compounds, compo- sitions and stacks. IMI has conducted multiple customer engagements in memory selector materials screening, and a typical experimental workflow is outlined in FIGURE 4, showing progression from PVD deposition, through physical and electrical characterizations of films and devices.

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This experimental process can be carried out multiple times, through subsequently more advanced stages on a fewer number of samples, as promising candidates are narrowed down and further optimized. FIGURE 5 shows a possible strategy for testing a series of candi- dates through three different stages. In the earlier stages, a wide range of options could be screened quickly, but the more extensive (and time consuming) characterization and analysis can be saved for later stages, when only the best performing candidates are already selected. This enables the best use of deposition and testing resources, leading to optimal results in an efficient timeframe.

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Fast and high-quality experimental results

IMI has extensive experience in working both on dynamic random access memory (DRAM) as well as NVM materials. In DRAM, the company has worked on development of dielectric, electrode and interface layer materials. IMI’s process engineers, materials scientists and electrical engineers work upfront with a customer on the design of experiments to ensure the delivery of rapid cycles of learning with the most efficient use of resources.

A typical customer project might range between a few months up to a year or more, encompassing hundreds or even thousands of different experiments. In NVM selectors alone, IMI has conducted:
• 2500+experiments on Metal Chalcogenides
• 2000+ experiments on MIEC
• 1000+experiments on Transition Metal Oxides

Conclusion

High throughput experimentation can offer rapid, high quality materials data when effectively applied to PVD memory selector development. However it does require an advanced platform, and a facility and team experienced in efficient deposition and testing of the materials and devices. Materials and device expertise is also helpful in managing and optimizing the experimental workflow for maximum efficiency and high quality data.

Conax Technologies announced the acquisition of Quartz Engineering, a manufacturer of quartz sheaths for temperature sensors headquartered in Tempe, AZ. S. K. Choi, former President of Quartz engineering, will stay on and help with the integration of Quartz Engineering and Conax. Choi has 40 years of experience in the semiconductor segment of the quartz industry and 20 years of experience in the fabrication of the specific type of sheaths primarily used by Conax.

This acquisition represents a commitment to improving the company’s responsiveness and the quality of products the company can provide to customers in the semiconductor industry.

Conax Business Unit Manager Michael Ferraro stated, “We’re expanding our focus in the growing Semiconductor industry. Many of the temperature sensors used inside process chambers need a semiconductor-grade quartz sheath to protect them from the chemicals and temperatures present. With the acquisition of Quartz Engineering, we now have in-house capabilities to design and manufacture quartz sheaths for temperature sensors.”

Ferraro explained, “By producing the sheaths in-house, we maintain greater control over quality and supply; and we can provide our customers with the solutions they need faster.”

Manufacturing operations will remain at the Tempe, AZ facility. Headquartered in Buffalo, NY, Conax Technologies is a designer and manufacturer of standard and custom engineered temperature sensors, compression seal fittings and feedthroughs, probes, sensors, wires, electrodes and fiber optic cables. The company has locations on the US west coast, as well as in Canada, Europe and Asia.

Avantor Performance Materials, LLC, announced today the acquisition of Puritan Products, Inc., a supplier of cGMP buffers and solutions for Biopharma customers, and high-purity chemistries for Research and Electronic Materials customers.

Avantor is a global supplier of ultra-high-purity materials for the life sciences and advanced technology markets. The company provides performance materials and solutions for the production and research needs of approximately 7,900 customers across the biotechnology, pharmaceutical, medical device, diagnostics, aerospace & defense, and semiconductor industries.

“The addition of Puritan is a key next step in our growth plans, as it provides access to new customers in the U.S. and Europe, a broader portfolio of high-purity products for the Biopharma, Research and Electronic Materials industries, and access to additional capabilities, including new cGMP operations and talented new colleagues,” said Michael Stubblefield, CEO of Avantor. “The addition of Puritan’s operations, equipment and sourcing of raw materials offer our customers an additional layer of supply chain security, a key element of the Avantor value proposition.”

Avantor will begin the process of integrating Puritan into the company immediately. Customers will now have access to the J.T.Baker, Macron Fine Chemicals and Puritan brands of high-purity products, as well as Avantor’s other portfolio of brands, including NuSil brand high-purity biomaterials and silicone.

“The Puritan business complements Avantor’s platform very well, particularly the focus on quality manufacturing and regulatory compliance – two areas that are critical in the life science industry,” continued Stubblefield.

The first fully functional microprocessor logic devices based on few-atom-thick layered materials have been demonstrated by researchers from the Graphene Flagship, working at TU Vienna in Austria. The processor chip consists of 115 integrated transistors and is a first step toward ultra-thin, flexible logic devices. Using transistors made from layers of molybdenum disulphide (MoS2), the microprocessors are capable of 1-bit logic operations and the design is scalable to multi-bit operations.

With the drive towards smart objects and the Internet of Things, the microprocessors hold promise for integrating computational power into everyday objects and surfaces. The research is published this week in Nature Communications.

The Graphene Flagship is developing novel technologies based on graphene and related materials (GRMs) such as transition metal dichalcogenides (TMDs) like MoS2, semiconductor materials that can be separated into ultra-thin sheets just a few atoms thick. GRMs are promising for compact and flexible electronic devices due to their thinness and excellent electrical properties.

The ultra-thin MoS2 transistors are inherently flexible and compact, so this result could be directly translated into microprocessors for fully flexible electronic devices, for example, wearable phones or computers, or for wider use in the Internet of Things. The MoS2 transistors are highly responsive, and could enable low-powered computers to be integrated into everyday objects without adding bulk. “In principle, it’s an advantage to have a thin material for a transistor. The thinner the material, the better the electrostatic control of the transistor channel, and the smaller the power consumption,” said Thomas Mueller (TU Vienna), who led the work.

Mueller added “In general, being a flexible material there are new opportunities for novel applications. One could combine these processor circuits with light emitters that could also be made with MoS2 to make flexible displays and e-paper, or integrate them for logic circuits in smart sensors. Our goal is to realise significantly larger circuits that can do much more in terms of useful operations. We want to make a full 8-bit design – or even more bits – on a single chip with smaller feature sizes.”

Talking about increasing the computing power, Stefan Wachter (TU Vienna), first author of the work, said “Adding additional bits of course makes everything much more complicated. For example, adding just one bit will roughly double the complexity of the circuit.”

Compared to modern processors, which can have billions of transistors in a single chip, the 115-transistor devices are very simple. However, it is a very early stage for a new technology, and the team have concrete plans for the next steps: “Our approach is to improve the processing to a point where we can reliably make chips with a few tens of thousands of transistors. For example, growing directly onto the chip would avoid the transfer process, which would give higher yield so that we can go to more complex circuits,” said Dmitry Polyushkin (TU Vienna), an author of the work.

Carbon nanotubes can be used to make very small electronic devices, but they are difficult to handle. University of Groningen scientists, together with colleagues from the University of Wuppertal and IBM Zurich, have developed a method to select semiconducting nanotubes from a solution and make them self-assemble on a circuit of gold electrodes. The results were published in the journal Advanced Materials on 5 April.

The results look deceptively simple: a self-assembled transistor with nearly 100 percent purity and very high electron mobility. But it took ten years to get there. University of Groningen Professor of Photophysics and Optoelectronics Maria Antonietta Loi designed polymers which wrap themselves around specific carbon nanotubes in a solution of mixed tubes. Thiol side chains on the polymer bind the tubes to the gold electrodes, creating the resultant transistor.

This is an artist's impression of carbon nanotubes wrapped in polymers with thiol side chains (yellow spheres) and assembled on gold electrodes. Credit: Arjen Kamp

This is an artist’s impression of carbon nanotubes wrapped in polymers with thiol side chains (yellow spheres) and assembled on gold electrodes. Credit: Arjen Kamp

Patent

‘In our previous work, we learned a lot about how polymers attach to specific carbon nanotubes’, Loi explains. These nanotubes can be depicted as a rolled sheet of graphene, the two-dimensional form of carbon. ‘Depending on the way the sheets are rolled up, they have properties ranging from semiconductor to semi-metallic to metallic.’ Only the semiconductor tubes can be used to fabricate transistors, but the production process always results in a mixture.

‘We had the idea of using polymers with thiol side chains some time ago’, says Loi. The idea was that as sulphur binds to metals, it will direct polymer-wrapped nanotubes towards gold electrodes. While Loi was working on the problem, IBM even patented the concept. ‘But there was a big problem in the IBM work: the polymers with thiols also attached to metallic nanotubes and included them in the transistors, which ruined them.’

Solution

Loi’s solution was to reduce the thiol content of the polymers, with the assistance of polymer chemists from the University of Wuppertal. ‘What we have now shown is that this concept of bottom-up assembly works: by using polymers with a low concentration of thiols, we can selectively bring semiconducting nanotubes from a solution onto a circuit.’ The sulphur-gold bond is strong, so the nanotubes are firmly fixed: enough even to stay there after sonication of the transistor in organic solvents.

The production process is simple: metallic patterns are deposited on a carrier , which is then dipped into a solution of carbon nanotubes. The electrodes are spaced to achieve proper alignment: ‘The tubes are some 500 nanometres long, and we placed the electrodes for the transistors at intervals of 300 nanometres. The next transistor is over 500 nanometres away.’ The spacing limits the density of the transistors, but Loi is confident that this could be increased with clever engineering.

‘Over the last years, we have created a library of polymers that select semiconducting nanotubes and developed a better understanding of how the structure and composition of the polymers influences which carbon nanotubes they select’, says Loi. The result is a cheap and scalable production method for nanotube electronics. So what is the future for this technology? Loi: ‘It is difficult to predict whether the industry will develop this idea, but we are working on improvements, and this will eventually bring the idea closer to the market.’

It would be difficult to overestimate the importance of silicon when it comes to computing, solar energy, and other technological applications. (Not to mention the fact that it makes up an awful lot of the Earth’s crust.) Yet there is still so much to learn about how to harness the capabilities of element number fourteen.

The most-common form of silicon crystallizes in the same structure as diamond. But other forms can be created using different processing techniques. New work led by Carnegie’s Tim Strobel and published in Physical Review Letters shows that one form of silicon, called Si-III (or sometimes BC8), which is synthesized using a high-pressure process, is what’s called a narrow band gap semiconductor.

What does this mean and why does it matter?

Metals are compounds that are capable of conducting the flow of electrons that makes up an electric current, and insulators are compounds that conduct no current at all. Semiconductors, which are used extensively in electronic circuitry, can have their electrical conductivity turned on and off–an obviously useful capability. This ability to switch conductivity is possible because some of their electrons can move from lower-energy insulating states to higher-energy conducting states when subjected to an input of energy. The energy required to initiate this leap is called a band gap.

The diamond-like form of silicon is a semiconductor and other known forms are metals, but the true properties of Si-III remained unknown until now. Previous experimental and theoretical research suggested that Si-III was a poorly conducting metal without a band gap, but no research team had been able to produce a pure and large enough sample to be sure.

By synthesizing pure, bulk samples of Si-III, Strobel and his team were able to determine that Si-III is actually a semiconductor with an extremely narrow band gap, narrower than the band gap of diamond-like silicon crystals, which is the most-commonly utilized kind. This means that Si-III could have uses beyond the already full slate of applications for which silicon is currently used. With the availability of pure samples, the team was able to fully characterize the electronic, optical, and thermal transport properties of Si-III for the first time.

“Historically, the correct recognition of germanium as a semiconductor instead of the metal it was once widely believed to be truly helped to start the modern semiconductor era; similarly, the discovery of semiconducting properties of Si-III might lead to unpredictable technological advancement,” remarked lead author, Carnegie’s Haidong Zhang. “For example, the optical properties of Si-III in the infrared region are particularly interesting for future plasmonic applications.”

SEMI, the global industry association representing the electronics manufacturing supply chain, today announced that the global semiconductor materials market increased 2.4 percent in 2016 compared to 2015 while worldwide semiconductor revenues increased 1.1 percent.

According to the SEMI Material Market Data Subscription, total wafer fabrication materials and packaging materials were $24.7 billion and $19.6 billion, respectively. Comparable revenues for these segments in 2015 were $24.0 billion for wafer fabrication materials and $19.3 billion for packaging materials. The wafer fabrication materials segment increased 3.1 percent year-over-year, while the packaging materials segment increased 1.4 percent.

For the seventh consecutive year, Taiwan was the largest consumer of semiconductor materials due to its large foundry and advanced packaging base, totaling $9.8 billion. Korea and Japan maintained the second and third places, respectively, while China rose in the rankings to claim the fourth spot during the same time. Annual revenue growth was the strongest in the China, Taiwan, and Japan markets. The materials market in Europe, Rest of World (ROW) and South Korea experienced nominal growth, while the materials market in North America contracted. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.)

2015 and 2016 Regional Semiconductor Materials Markets (US$ Billions)

Region 2015* 2016 % Change
Taiwan

9.42

9.79

3.9%
South Korea

7.09

7.11

0.2%
Japan

6.56

6.74

2.8%
China

6.08

6.53

7.3%
Rest of World

6.09

6.12

0.6%
North America

4.97

4.90

-1.4%
Europe

3.07

3.12

1.5%
Total

43.29

44.32

2.4%

Source: SEMI, April 2017 Note: Figures may not add due to rounding.
* 2015 data have been updated based on SEMI’s data collection programs

A new way to grow narrow ribbons of graphene, a lightweight and strong structure of single-atom-thick carbon atoms linked into hexagons, may address a shortcoming that has prevented the material from achieving its full potential in electronic applications. Graphene nanoribbons, mere billionths of a meter wide, exhibit different electronic properties than two-dimensional sheets of the material.

This graphene nanoribbon was made bottom-up from a molecular precursor. Nanoribbon width and edge effects influence electronic behavior. Credit: Oak Ridge National Laboratory, U.S. Dept. of Energy; scanning tunneling microscopy by Chuanxu Ma and An-Ping Li

This graphene nanoribbon was made bottom-up from a molecular precursor. Nanoribbon width and edge effects influence electronic behavior. Credit: Oak Ridge National Laboratory, U.S. Dept. of Energy; scanning tunneling microscopy by Chuanxu Ma and An-Ping Li

“Confinement changes graphene’s behavior,” said An-Ping Li, a physicist at the Department of Energy’s Oak Ridge National Laboratory. Graphene in sheets is an excellent electrical conductor, but narrowing graphene can turn the material into a semiconductor if the ribbons are made with a specific edge shape.

Previous efforts to make graphene nanoribbons employed a metal substrate that hindered the ribbons’ useful electronic properties.

Now, scientists at ORNL and North Carolina State University report in the journal Nature Communications that they are the first to grow graphene nanoribbons without a metal substrate. Instead, they injected charge carriers that promote a chemical reaction that converts a polymer precursor into a graphene nanoribbon. At selected sites, this new technique can create interfaces between materials with different electronic properties. Such interfaces are the basis of semiconductor electronic devices from integrated circuits and transistors to light-emitting diodes and solar cells.

“Graphene is wonderful, but it has limits,” said Li. “In wide sheets, it doesn’t have an energy gap–an energy range in a solid where no electronic states can exist. That means you cannot turn it on or off.”

When a voltage is applied to a sheet of graphene in a device, electrons flow freely as they do in metals, severely limiting graphene’s application in digital electronics.

“When graphene becomes very narrow, it creates an energy gap,” Li said. “The narrower the ribbon is, the wider is the energy gap.”

In very narrow graphene nanoribbons, with a width of a nanometer or even less, how structures terminate at the edge of the ribbon is important too. For example, cutting graphene along the side of a hexagon creates an edge that resembles an armchair; this material can act like a semiconductor. Excising triangles from graphene creates a zigzag edge–and a material with metallic behavior.

To grow graphene nanoribbons with controlled width and edge structure from polymer precursors, previous researchers had used a metal substrate to catalyze a chemical reaction. However, the metal substrate suppresses useful edge states and shrinks the desired band gap.

Li and colleagues set out to get rid of this troublesome metal substrate. At the Center for Nanophase Materials Sciences, a DOE Office of Science User Facility at ORNL, they used the tip of a scanning tunneling microscope to inject either negative charge carriers (electrons) or positive charge carriers (“holes”) to try to trigger the key chemical reaction. They discovered that only holes triggered it. They were subsequently able to make a ribbon that was only seven carbon atoms wide–less than one nanometer wide–with edges in the armchair conformation.

“We figured out the fundamental mechanism, that is, how charge injection can lower the reaction barrier to promote this chemical reaction,” Li said. Moving the tip along the polymer chain, the researchers could select where they triggered this reaction and convert one hexagon of the graphene lattice at a time.

Next, the researchers will make heterojunctions with different precursor molecules and explore functionalities. They are also eager to see how long electrons can travel in these ribbons before scattering, and will compare it with a graphene nanoribbon made another way and known to conduct electrons extremely well. Using electrons like photons could provide the basis for a new electronic device that could carry current with virtually no resistance, even at room temperature.

“It’s a way to tailor physical properties for energy applications,” Li said. “This is an excellent example of direct writing. You can direct the transformation process at the molecular or atomic level.” Plus, the process could be scaled up and automated.

Researchers at North Carolina State University have developed a technique for converting positively charged (p-type) reduced graphene oxide (rGO) into negatively charged (n-type) rGO, creating a layered material that can be used to develop rGO-based transistors for use in electronic devices.

“Graphene is extremely conductive, but is not a semiconductor; graphene oxide has a bandgap like a semiconductor, but does not conduct well at all — so we created rGO,” says Jay Narayan, the John C. Fan Distinguished Chair Professor of Materials Science and Engineering at NC State and corresponding author of a paper describing the work. “But rGO is p-type, and we needed to find a way to make n-type rGO. And now we have it for next-generation, two-dimensional electronic devices.”

Specifically, Narayan and Anagh Bhaumik — a Ph.D. student in his lab — demonstrated two things in this study. First, they were able to integrate rGO onto sapphire and silicon wafers — across the entire wafer.

Second, the researchers used high-powered laser pulses to disrupt chemical groups at regular intervals across the wafer. This disruption moved electrons from one group to another, effectively converting p-type rGO to n-type rGO. The entire process is done at room temperature and pressure using high-power nanosecond laser pulses, and is completed in less than one-fifth of a microsecond. The laser radiation annealing provides a high degree of spatial and depth control for creating the n-type regions needed to create p-n junction-based two-dimensional electronic devices.

The end result is a wafer with a layer of n-type rGO on the surface and a layer of p-type rGO underneath.

This is critical, because the p-n junction, where the two types meet, is what makes the material useful for transistor applications.