Category Archives: Materials

Rice University integrated circuit (IC) designers are at Silicon Valley’s premier chip-design conference to unveil technology that is 10 times more reliable than current methods of producing unclonable digital fingerprints for Internet of Things (IoT) devices.

Rice’s Kaiyuan Yang and Dai Li will present their physically unclonable function (PUF) technology today at the 2019 International Solid-State Circuits Conference (ISSCC), a prestigious scientific conference known informally as the “Chip Olympics.” PUF uses a microchip’s physical imperfections to produce unique security keys that can be used to authenticate devices linked to the Internet of Things.

Considering that some experts expect Earth to pass the threshold of 1 trillion internet-connected sensors within five years, there is growing pressure to improve the security of IoT devices.

Yang and Li’s PUF provides a leap in reliability by generating two unique fingerprints for each PUF. This “zero-overhead” method uses the same PUF components to make both keys and does not require extra area and latency because of an innovative design feature that also allows their PUF to be about 15 times more energy efficient than previously published versions.

“Basically each PUF unit can work in two modes,” said Yang, assistant professor of electrical and computer engineering. “In the first mode, it creates one fingerprint, and in the other mode it gives a second fingerprint. Each one is a unique identifier, and dual keys are much better for reliability. On the off chance the device fails in the first mode, it can use the second key. The probability that it will fail in both modes is extremely small.”

As a means of authentication, PUF fingerprints have several of the same advantages as human fingerprints, he said.

“First, they are unique,” Yang said. “You don’t have to worry about two people having the same fingerprint. Second, they are bonded to the individual. You cannot change your fingerprint or copy it to someone else’s finger. And finally, a fingerprint is unclonable. There’s no way to create a new person who has the same fingerprint as someone else.”

PUF-derived encryption keys are also unique, bonded and unclonable. To understand why, it helps to understand that each transistor on a computer chip is incredibly small. More than a billion of them can be crammed onto a chip half the size of a credit card. But for all their precision, microchips are not perfect. The difference between transistors can amount to a few more atoms in one or a few less in another, but those miniscule differences are enough to produce the electronic fingerprints used to make PUF keys.

For a 128-bit key, a PUF device would send request signals to an array of PUF cells comprising several hundred transistors, allocating a one or zero to each bit based on the responses from the PUF cells. Unlike a numeric key that’s stored in a traditional digital format, PUF keys are actively created each time they’re requested, and different keys can be used by activating a different set of transistors.

Adopting PUF would allow chipmakers to inexpensively and securely generate secret keys for encryption as a standard feature on next-generation computer chips for IoT devices like “smart home” thermostats, security cameras and lightbulbs.

Encrypted lightbulbs? If that sounds like overkill, consider that unsecured IoT devices are what three young computer savants assembled by the hundreds of thousands to mount the October 2016 distributed denial-of-service attack that crippled the internet on the East Coast for most of a day.

“The general concept for IoT is to connect physical objects to the internet in order to integrate the physical and cyber worlds,” Yang said. “In most consumer IoT today, the concept isn’t fully realized because many of the devices are powered and almost all use existing IC feature sets that were developed for the mobile market.”

In contrast, the devices coming out of research labs like Yang’s are designed for IoT from the ground up. Measuring just a few millimeters in size, the latest IoT prototypes can pack a processor, flash memory, wireless transmitter, antenna, one or more sensors, batteries and more into an area the size of a grain of rice.

PUF is not a new idea for IoT security, but Yang and Li’s version of PUF is unique in terms of reliability, energy efficiency and the amount of area it would take to implement on a chip. For starters, Yang said the performance gains were measured in tests at military-grade temperatures ranging from 125 degrees Celsius to minus 55 degrees Celsius and when supply voltage dropped by up to 50 percent.

“If even one transistor behaves abnormally under varying environmental conditions, the device will produce the wrong key, and it will look like an inauthentic device,” Yang said. “For that reason, reliability, or stability, is the most important measure for PUF.”

Energy efficiency also is important for IoT, where devices can be expected to run for a decade on a single battery charge. In Yang and Li’s PUF, keys are created using a static voltage rather than by actively powering up the transistor. It’s counterintuitive that the static approach would be more energy efficient because it’s the equivalent of leaving the lights on 24/7 rather than flicking the switch to get a quick glance of the room.

“Normally, people have sleep mode activated, and when they want to create a key, they activate the transistor, switch it once and then put it to sleep again,” Yang said. “In our design, the PUF module is always on, but it takes very little power, even less than a conventional system in sleep mode.”

On-chip area — the amount of space and expense manufacturers would have to allocate to put the PUF device on a production chip — is the third metric where they outperform previously reported work. Their design occupied 2.37 square micrometers to generate one bit on prototypes produced using 65-nanometer complementary metal-oxide-semiconductor (CMOS) technology.

The research was funded by Rice University.

Switching magnetic domains in magnetic memories requires normally magnetic fields which are generated by electrical currents, hence requiring large amounts of electrical power. Now, teams from France, Spain and Germany have demonstrated the feasibility of another approach at the nanoscale: “We can induce magnetic order on a small region of our sample by employing a small electric field instead of using magnetic fields”, Dr. Sergio Valencia, HZB, points out.

The cones represents the magnetization of the nanoparticles. In the absence of electric field (strain-free state) the size and separation between particles leads to a random orientation of their magnetization, known as superparamagnetism. Credit: HZB

The samples consist of a wedge-shaped polycrystalline iron thin film deposited on top of a BaTiO3 substrate. BaTiO3 is a well-known ferroelectric and ferroelastic material: An electric field is able to distort the BaTiO3 lattice and induce mechanical strain. Analysis by electron microscopy revealed that the iron film consists of tiny nanograins (diameter 2,5 nm). At its thin end, the iron film is less than 0,5 nm thick, allowing for “low dimensionality” of the nanograins. Given their small size, the magnetic moments of the iron nanograins are disordered with respect to each other, this state is known as superparamagnetism.

At the X-PEEM-Beamline at BESSY II, the scientists analysed what happens with the magnetic order of this nanograins under a small electric field. “With X-PEEM we can map the magnetic order of the iron grains on a microscopic level and observe how their orientation changes while in-situ applying an electric field”, Dr. Ashima Arora explains, who did most of the experiments during her PhD Thesis. Their results show: the electrical field induced a strain on BaTiO3, this strain was transmitted to the iron nanograins on top of it and formerly superparamagnetic regions of the sample switched to a new state. In this new state the magnetic moments of the iron grains are all aligned along the same direction, i.e. a collective long-range ferromagnetic order known as superferromagnetism.

The experiments were performed at a temperature slightly above room temperature. “This lets us hope that the phenomenon can be used for the design of new composite materials (consisting of ferroelectric and magnetic nanoparticles) for low-power spin-based storage and logic architectures operating at ambient conditions”, Valencia says.

Controlling nanoscale magnetic bits in magnetic random access memory devices by electric field induced strain alone, is known also as straintronics. It could offer a new, scalable, fast and energy efficient alternative to nowadays magnetic memories.

Organic semiconductors are lightweight, flexible and easy to manufacture. But they often fail to meet expectations regarding efficiency and stability. Researchers at the Technical University of Munich (TUM) are now deploying data mining approaches to identify promising organic compounds for the electronics of the future.

Producing traditional solar cells made of silicon is very energy intensive. On top of that, they are rigid and brittle. Organic semiconductor materials, on the other hand, are flexible and lightweight. They would be a promising alternative, if only their efficiency and stability were on par with traditional cells.

Together with his team, Karsten Reuter, Professor of Theoretical Chemistry at the Technical University of Munich, is looking for novel substances for photovoltaics applications, as well as for displays and light-emitting diodes – OLEDs. The researchers have set their sights on organic compounds that build on frameworks of carbon atoms.

Contenders for the electronics of tomorrow

Depending on their structure and composition, these molecules, and the materials formed from them, display a wide variety of physical properties, providing a host of promising candidates for the electronics of the future.

“To date, a major problem has been tracking them down: It takes weeks to months to synthesize, test and optimize new materials in the laboratory,” says Reuter. “Using computational screening, we can accelerate this process immensely.”

Computers instead of test tubes

The researcher needs neither test tubes nor Bunsen burners to search for promising organic semiconductors. Using a powerful computer, he and his team analyze existing databases. This virtual search for relationships and patterns is known as data mining.

“Knowing what you are looking for is crucial in data mining,” says PD Dr. Harald Oberhofer, who heads the project. “In our case, it is electrical conductivity. High conductivity ensures, for example, that a lot of current flows in photovoltaic cells when sunlight excites the molecules.”

Algorithms identify key parameters

Using his algorithms, he can search for very specific physical parameters: An important one is, for example, the “coupling parameter.” The larger it is, the faster electrons move from one molecule to the next.

A further parameter is the “reorganization energy”: It defines how costly it is for a molecule to adapt its structure to the new charge following a charge transfer – the less energy required, the better the conductivity.

The research team analyzed the structural data of 64,000 organic compounds using the algorithms and grouped them into clusters. The result: Both the carbon-based molecular frameworks and the “functional groups”, i.e. the compounds attached laterally to the central framework, decisively influence the conductivity.

Identifying molecules using artificial intelligence

The clusters highlight structural frameworks and functional groups that facilitate favorable charge transport, making them particularly suitable for the development of electronic components.

“We can now use this to not only predict the properties of a molecule, but using artificial intelligence we can also design new compounds in which both the structural framework and the functional groups promise very good conductivity,” explains Reuter.

Publication:

Finding the Right Bricks for Molecular Lego: A Data Mining Approach to Organic Semiconductor Design
Christian Kunkel, Christoph Schober, Johannes T. Margraf, Karsten Reuter, Harald Oberhofer
Chem. Mater. 2019, 31, 3, 969-978 – DOI: 10.1021/acs.chemmater.8b04436
https://pubs.acs.org/doi/10.1021/acs.chemmater.8b04436

Silicon Catalyst, the world’s only incubator focused exclusively on accelerating solutions in silicon, today announced Soitec (Euronext Paris), a designer and manufacturer of semiconductor materials, as its first European Strategic Partner. This agreement provides Soitec access to early-stage silicon technology innovation targeting consumer, IoT and automotive segments and applications.

Silicon Catalyst is a Silicon Valley-based incubator providing silicon-focused start-ups access to a world-class network of advisors, design tools, silicon devices, networking, access to funding and marketing acumen needed to successfully launch their businesses. Soitec will engage in this start-up ecosystem to gain insight into the newest technologies and applications across high-growth markets, and to guide nascent technologies to successful market penetration.

“As a Strategic Partner of Silicon Catalyst, Soitec has a unique opportunity to grow our visibility among early-stage semiconductor companies,” said Thomas Piliszczuk, Executive VP of Global Strategy for Soitec. “Engineered substrates give semiconductor related start-ups a competitive edge in developing new high-performance, energy-efficient solutions. We are looking forward to supporting emerging trends and technology advancements with Silicon Catalyst’s distinguished portfolio of semiconductor entrepreneurs.”

“We are pleased to welcome Soitec as our first European Strategic Partner. Soitec is creating technical advances that are enabling the next generation of products across many market segments. Their SOI technology is a key ingredient to meet the diverse challenges for breakthrough differentiated semiconductor products, combining ultra-low power with excellent analog / mixed-signal performance,” stated Pete Rodriguez, CEO of Silicon Catalyst. “Joining our other Strategic Partners, Texas Instruments and ON Semiconductor, Soitec will participate in the selection of applicants to our incubator and provide guidance for our Portfolio Companies, contributing to the growth of startups that are creating the next generations of semiconductor innovation.”

Soitec’s substrate solutions, most notably silicon-on-insulator (SOI), address the full range of applications for electronics. SOI substrates are designed to support ultra-low power signal processing, wireless connectivity, power, image sensors and silicon photonics applications. Radio-frequency silicon-on-insulator (RF-SOI) substrates are the foundation of the RF incumbent technology for RF Front-End modules used in all smart phones manufactured today. RF-SOI and fully depleted SOI (FD-SOI) material enable ultra-low power connectivity, mobility, distributed AI and edge computing. Adding our new compound and piezo-electric on insulator substrates, Soitec offers a wide range of engineered substrates addressing numerous and fast growing segments like automotive, AI-IoT (AIoT) and 5G.

By Mike Russo

For public policy lovers, civic-minded, engaged U.S. citizens, and people around the world interested in the U.S. President’s positions and priorities, the annual State of the Union address (SOTU) is “must-see TV.” This year, the anticipation and expectations were different than with past presidents. Trump is the first U.S. president who has used social media to the extreme that he has. Indeed, his Twitter feed is the most followed in history.

President Trump’s prolific Twitter feed has had an interesting impact on the SOTU. U.S. citizens and people from around the world already know President Trump’s positions on issues, his policy priorities and what gets him excited. There is an ongoing, direct line to the President’s thoughts throughout each and every day. In the past we looked to the SOTU for insights into what the sitting president is really thinking and his future policy priorities. Now, there isn’t much we don’t already know.

One looming question this year was whether President Trump would reach out in a conciliatory manner to help bridge the political divide and lay the groundwork to enable some public policy wins and avoid another government shutdown. While there were moments of conciliation, the President made it clear he would not move on areas that are most contentious with the other side of the aisle.

For example, the President unequivocally reiterated his intent to build “the wall.” While the message plays well to his base, it is, in effect, a frontal assault and challenge to Democrats. It’s hard to image that his staunch stance will help move the two parties to work together on substantive policy issues. It may also mean that the “wall” issue will occupy lawmakers time for the foreseeable future, sidelining debate on other important issues.

The best hope is that a bipartisan bill finds its way to the President’s desk that he can sign and use to “declare victory.” However, many political observers believe the likelihood of the President declaring a national security emergency is rising as a maneuver to ensure funding for “the wall” and avoid a shutdown. While such a declaration would most likely face a court challenge, the President could claim that his decision was a move of last resort and leverage the moment to position Democrats as obstructionists to his base. The scenario does not bode well for the bipartisan support necessary to address other issues.

What does this mean for our industry? Were there any points raised in the SOTU that would signal a change in what we are facing regarding trade, tariffs, export controls and immigration? Were any new issues or ideas raised that could help lift the global economy? In short, no. On one hand, the President cited his good relationship with the president of China, but on the other doubled down on his attacks on China, seeming to stand firm to bolster his position at the table as the U.S. and China trade talks continue.

What do these dynamics mean for SEMI Global Advocacy? In 2018 we were heavily engaged in efforts to prevent regulations that would inhibit our members’ ability to develop and deploy technologies and maintain global market access. We advanced our global advocacy model, leveraging our regional presence around the world. Many of the potential issues we faced emanated from the U.S., including those focused on controlling technology development, limiting trade and enhancing export controls. We also intensified our efforts to address industry talent pipeline issues.

In 2019, our public policy focus will be to continue to push back on tariffs, engage members to inform the rule-making process for export controls and to attempt to influence the immigration debate as it pertains to access to talent. In addition, while the U.S. R&D tax credit was made permanent through the tax cut in 2017, some of the provisions may have unintended consequences and will need to be modified. How the law is enacted will affect how businesses can deduct qualified research and development and other expenses from their taxable income, so we anticipate activity on the tax front as well.

It will also be a big year for SEMI on the workforce developmentfront. SEMI will continue to grow its existing High Tech U (HTU), university and mentor programs. In addition, SEMI will be positioning itself as the global leader in addressing issues related to the talent pipeline by approaching the problem with a full-spectrum, holistic approach that is intended to better address more immediate needs in attracting, training and retaining qualified talent. We’ll also focus on improving the industry image and exciting students at a younger age by providing experiential learning activities throughout a defined educational pathway. Stay tuned on this front as the full program unfolds.

In general, we will continue to build our relationships and stature as a leading voice for our members and the end-to-end semiconductor supply chain in the areas of “Talent, Trade, Tax and Technology” (SEMI’s “4 Ts”) and to ensure free and fair trade, access to markets, supply chain growth, IP protections and enhanced efforts to improve cybersecurity.

Mike Russo is VP of Global Industry Advocacy at SEMI. 

Source: SEMI Blog

Two-dimensional transition metal dichalcogenides (2D-TMDs) such as monolayer molybdenum disulphide (MoS2) are atomically thin semiconductors in which a layer of transition metal atom is sandwiched between two layers of chalcogen atoms, in the form MX2. They can exist in both a semiconducting 1H-phase and a quasi-metallic 1T’-phase, with each having a different crystal structure. The 1T’-phase is particularly interesting as theoretical predictions show that it has potential to be used in less conventional applications, such as super capacitor electrodes and hydrogen evolution reaction catalysts. However, the quantity of 1T’-phase 2D-TMDs that can be obtained by converting them from the 1H-phase through a phase transition process is low. This potentially limits the use of such novel materials for a wide range of applications.

Molecules of monolayer molybdenum disulphide (MoS2) and tungsten diselenide (WSe2) on top of a metal substrate. Credit: National University of Singapore

A research team led by Professor Andrew Wee from the Department of Physics at the National University of Singapore’s (NUS) Faculty of Science has discovered that while different 2D-TMD materials have their own intrinsic energy barriers when transiting from the 1H to the 1T’ structural phase, the use of a metallic substrate with higher chemical reactivity can significantly increase the 1H- to 1T’- phase transition yield. This is a convenient and high-yielding method to obtain 2D-TMD materials in their 1T’ metallic phase. When the 2D-TMD material is placed in contact with the metal substrate, such as gold, silver and copper, electric charges are transferred from the metal substrate to the 2D-TMD material. Furthermore, it weakens the bond strength of the 2D-TMD structure significantly, and increases the magnitude of the interfacial binding energy. This in turn increases the susceptibility of the 1H-1T’ structural phase transition. As a result, this enhanced interfacial hybridisation at the interface of the two materials makes the 1H-1T’ structural phase transition much easier to achieve.

The NUS research team combined multiple experimental techniques and first-principles calculations in their research work. These includes optical spectroscopies, high resolution transmission electron microscopy and density functional theory based first-principles calculations to identify the phase changes – both 1H- and 1T’-phases – of the 2D-TMDs in the samples.

This study provides new insights on the influence of interfacial hybridisation affecting the phase transition dynamics of 2D-TMDs. The findings can potentially be used in a model system for the controlled growth of 2D-TMDs on metallic substrates, creating possibilities for new 2D-TMDs-based device applications.

Prof Wee said, “The controllability of the semiconductor to metal phase transition at the 2D-TMD and metal interfaces can enable new device applications such as low contact resistance electrodes.”

Optical circuits are set to revolutionize the performance of many devices. Not only are they 10-100 times faster than electronic circuits, but they also consume a lot less power. Within these circuits, light waves are controlled by extremely thin surfaces called metasurfaces that concentrate the waves and guide them as needed. The metasurfaces contain regularly spaced nanoparticles that can modulate electromagnetic waves over sub-micrometer wavelength scales.

The new method employs a natural process already used in fluid mechanics: dewetting. CREDIT © Vytautas Navikas / 2019 EPFL

Metasurfaces could enable engineers to make flexible photonic circuits and ultra-thin optics for a host of applications, ranging from flexible tablet computers to solar panels with enhanced light-absorption characteristics. They could also be used to create flexible sensors to be placed directly on a patient’s skin, for example, in order to measure things like pulse and blood pressure or to detect specific chemical compounds.

The catch is that creating metasurfaces using the conventional method, lithography, is a fastidious, several-hour-long process that must be done in a clean room. But EPFL engineers from the Laboratory of Photonic Materials and Fiber Devices (FIMAP) have now developed a simple method for making them in just a few minutes at low temperatures – or sometimes even at room temperature – with no need for a clean room. The EPFL’s School of Engineering method produces dielectric glass metasurfaces that can be either rigid or flexible. The results of their research appear in Nature Nanotechnology.

Turning a weakness into a strength

The new method employs a natural process already used in fluid mechanics: dewetting. This occurs when a thin film of material is deposited on a substrate and then heated. The heat causes the film to retract and break apart into tiny nanoparticles. “Dewetting is seen as a problem in manufacturing – but we decided to use it to our advantage,” says Fabien Sorin, the study’s lead author and the head of FIMAP.

With their method, the engineers were able to create dielectric glass metasurfaces – rather than metallic metasurfaces – for the first time. The advantage of dielectric metasurfaces is that they absorb very little light and have a high refractive index, making it possible to effectively modulate the light that propagates through them.

To construct these metasurfaces, the engineers first created a substrate textured with the desired architecture. Then they deposited a material – in this case, chalcogenide glass – in thin films just tens of nanometers thick. The substrate was subsequently heated for a couple of minutes until the glass became more fluid and nanoparticles began to form in the sizes and positions dictated by the substrate’s texture.

The engineers’ method is so efficient that it can produce highly sophisticated metasurfaces with several levels of nanoparticles or with arrays of nanoparticles spaced 10 nm apart. That makes the metasurfaces highly sensitive to changes in ambient conditions – such as to detect the presence of even very low concentrations of bioparticles. “This is the first time dewetting has been used to create glass metasurfaces. The advantage is that our metasurfaces are smooth and regular, and can be easily produced on large surfaces and flexible substrates,” says Sorin.

Germanene is a 2D material that derives from germanium and is related to graphene. As it is not stable outside the vacuum chambers in which is it produced, no real measurements of its electronic properties have been made. Scientists led by Prof. Justin Ye of the University of Groningen have now managed to produce devices with stable germanene. The material is an insulator, and it becomes a semiconductor after moderate heating and a very good metallic conductor after stronger heating. The results were published in the journal Nano Letters.

Germanane is converted into germanene by thermal annealing, which removes the hydrogen (red). Credit: Ye Lab / University of Groningen

Materials of just one atomic layer are of interest in the construction of new types of microelectronics. The best known of these, graphene, is an excellent conductor. Materials like silicon and germanium could be interesting as well, as they are fully compatible with well-established protocols for device fabrication, and could be seamlessly integrated into the present semiconductor technology.

Unstable

‘But the 2D version of germanium, germanene, is very unstable’, explains University of Groningen Associate Professor of Device Physics Justin Ye. Germanene is made from germanium by adding calcium. The calcium ions create 2D layers from a 3D crystal and are then replaced by hydrogen. These 2D layers of germanium and hydrogen are called germanane. But once the hydrogen is removed to form germanene, the material becomes unstable.

Ye and his colleagues solved this in a remarkably simple way. They made devices with the stable germanane, and then heated the material to remove the hydrogen. This resulted in stable devices with germanene, which allowed the scientists to study its electronic properties.

Hydrogen

‘The initial material was an insulator’, says Ye. A Ph.D. student from his group heated these devices, which is a tried and tested method to increase conductivity. He noted that the material became very conductive, and its resistance was just one order of magnitude above that of graphene. ‘So it became an excellent metallic conductor.’ Further experiments showed that moderate heating (up to 200°C) produced semiconducting germanane.

Germanene can, therefore, be an insulator, a semiconductor or a metallic conductor, depending on the heat treatment with which it is processed. It remains stable after being cooled to room temperature. The heating causes multilayer flakes of germanene to become thinner – confirmation that the change in conductivity is most likely caused by the disappearance of hydrogen.

Spintronic device

Germanene could be of interest in the construction of spintronic devices. These devices use a current of electron spins. This is a quantum mechanical property of electrons, which can best be imagined as electrons spinning around their own axis, causing them to behave like small compass needles. Graphene is an excellent conductor of electron spins, but it is hard to control spins in this material because of their weak interaction with the carbon atoms (spin-orbit coupling).

‘The germanium atoms are heavier, which means there is a stronger spin-orbit coupling’, says Ye. This would provide better control of spins. Being able to construct metallic germanene with both excellent conductivity and strong spin-orbit coupling should therefore pave the way to spintronic devices.

Mentor, a Siemens business, today announced that artificial intelligence (AI) semiconductor innovator Graphcore (Bristol, U.K.) successfully met its silicon test requirements and achieved rapid test bring-up on its Colossus Intelligence Processing Unit (IPU) by using Mentor’s Tessent™ product family.

Graphcore’s recently announced Colossus IPU targets machine intelligence training and inference in datacenters. The first-of-its-kind device lowers the cost of accelerating AI applications in cloud and enterprise datacenters, while increasing the performance of both training and inference by up to 100x compared to the fastest systems today.

Graphcore required a DFT solution that could reduce the cost and time challenges associated with testing the Colossus IPU’s novel architecture and exceptionally large design. Integrating 23.6 billion transistors and more than a thousand IPU cores, Colossus is one of the largest processors ever fabricated.

Mentor’s Tessent is the market leading DFT solution, helping companies achieve higher test quality, lower test cost and faster yield ramps. The register-transfer level (RTL)-based hierarchical DFT foundation in Tessent features an array of technologies specifically suited to address the implementation and pattern generation challenges of AI chip architectures.

Graphcore leveraged these capabilities and the Tessent SiliconInsight integrated silicon bring-up environment on Graphcore’s Colossus IPU to meet its test requirements, while minimizing cycle time for DFT implementation, pattern generation, verification and silicon validation.

“We used Mentor’s fully automated Tessent platform for our series of initial silicon parts, together with an all-Mentor DFT flow, allowing us to ship fully tested and validated parts within the first week,” said Phil Horsfield, vice president of Silicon at Graphcore. “We were able to have Logic BIST, ATPG and Memory BIST up and running in under three days. This was way ahead of schedule.”

Research firm IBS, Inc. estimates that AI-related applications consumed $65 billion (USD) of processing technology last year, growing at an 11.5 percent annual rate and significantly outpacing other segments. This processing demand has until now been supplied by microprocessors not fully optimized for high AI workloads. To meet this growing demand while significantly lowering computational cost, more than 70 companies have announced plans to create new processing architectures based on massive parallelism and specialized for AI workloads.

“Hardware acceleration for AI is now a very competitive and rapidly evolving market. As a result, fast time to market is a leading concern for this segment,” said Brady Benware, senior marketing director for the Tessent product family at Mentor, a Siemens business. “Companies participating in this market are choosing Tessent because its RTL-based hierarchical DFT approach provides extremely efficient test implementation for massively parallel architectures, and Tessent’s SiliconInsight debug and characterization capabilities eliminate costly delays during silicon bring-up.”

Researchers from the University of Houston have reported significant advances in stretchable electronics, moving the field closer to commercialization.

Researchers from the University of Houston have reported significant advances in the field of stretchable, rubbery electronics. Credit: University of Houston

In a paper published Friday, Feb. 1, in Science Advances, they outlined advances in creating stretchable rubbery semiconductors, including rubbery integrated electronics, logic circuits and arrayed sensory skins fully based on rubber materials.

Cunjiang Yu, Bill D. Cook Assistant Professor of mechanical engineering at the University of Houston and corresponding author on the paper, said the work could lead to important advances in smart devices such as robotic skins, implantable bioelectronics and human-machine interfaces.

Yu previously reported a breakthrough in semiconductors with instilled mechanical stretchability, much like a rubber band, in 2017.

This work, he said, takes the concept further with improved carrier mobility and integrated electronics.

“We report fully rubbery integrated electronics from a rubbery semiconductor with a high effective mobility … obtained by introducing metallic carbon nanotubes into a rubbery semiconductor with organic semiconductor nanofibrils percolated,” the researchers wrote. “This enhancement in carrier mobility is enabled by providing fast paths and, therefore, a shortened carrier transport distance.”

Carrier mobility, or the speed at which electrons can move through a material, is critical for an electronic device to work successfully, because it governs the ability of the semiconductor transistors to amplify the current.

Previous stretchable semiconductors have been hampered by low carrier mobility, along with complex fabrication requirements. For this work, the researchers discovered that adding minute amounts of metallic carbon nanotubes to the rubbery semiconductor of P3HT – polydimethylsiloxane composite – leads to improved carrier mobility by providing what Yu described as “a highway” to speed up the carrier transport across the semiconductor.