Category Archives: Materials

 The 2018 Critical Materials Council (CMC) Conference—held April 26-27 at the Hilton Chandler in Arizona— was a great gathering with presentations from Everspin, Intel, GlobalFoundries, and NXP discussing current fab challenges, and the relationships to near-term materials solutions. Held immediately following private CMC face-to-face meeting, this public event enabled targeted discussions on problems, opportunities, and issues in the present and future materials market.

Session 1 presentations from Keller&Heckman, KPMG, Semico, VLSI Research, and the United States’ Environmental Protection Agency reminded attendees of the many environmental, financial, and political factors impacting global fab supply-chains. Jeff Morris, the US EPA’s Director of the Office of Pollution Prevention and Toxics, reviewed the status of enforcement of the Toxic Substances Control Act (TSCA) with a focus on N-Methylpyrrolidone (NMP), per- and poly-fluorinated Substances (PFAS, PFOS, PFOA), and Photo-Acid Generators (PAG) used in semiconductor manufacturing.

Session 2 covering materials issues in fabs today explored the evolving specifications needed in silicon wafers, ion-implantation, noble gases, and metal depositions including atomic-layer (ALD) chemical-vapor (CVD) physical-vapor (PVD) and electro-chemical (ECD). The Figure shows 200mm-diameter silicon wafer global supply and manufacturing demand from 2015 to 2020, as modeled by TECHCET President and CEO Lita Shon-Roy in her presentation on materials markets. TECHCET expects that this year will see a balancing and then an excess of supply in this wafer size used for manufacturing Opto-electronics, Sensors, and Discretes (OSD) along with Radio Frequency (RF) communications chips.

The presentations on cobalt processing from Air Liquide, Applied Materials, Fraunhofer, and Fujimi—mostly in Session 3—provided fantastic perspectives on solutions to inherent integration challenges with this metal. Cobalt has been used as a barrier or a liner for on-chip copper interconnect lines for many years, but the material is now being integrated as the entire interconnect material for the smallest metal lines in the most aggressively scaled IC structures. Nicolas Blasco of Air Liquide discussed the complex path to discovering novel ALD precursors, while Michelle Garza of Fujimi discussed ways to manage the complexity of developing new Chemical-Mechanical Planarization (CMP) slurries for application-specific cobalt integration.

Senior Analyst with TECHCET Ed Korczynski presented an update on the latest lithography materials to enable patterning the smallest possible commercial IC devices, including recently disclosed Self-Aligned Multi-Patterning (SAMP) technology options to improve IC yields. Cost models for different multi-patterning process flows were recently presented at the 2018 SPIE Advanced Lithography conference showing how Extreme Ultra-Violet (EUV) lithography can be cost-effective despite double the tool costs. Key to cost-effective use of EUV will be control of stochastic yield losses which are colloquially termed “Black Swans”.

The Wednesday night reception and the Thursday night break-out roundtable discussions gave everyone time to make new connections and have discrete discussions on metrology, specifications, and technology integration. Block your calendar in 2019 for the 4th annual CMC Conference, tentatively scheduled for April 25-26 in the US. www.cmcfabs.org www.techcet.com

ABOUT CMC: The Critical Materials Council (CMC) of Semiconductor Fabricators (CMCFabs.org) is a membership-based organization that works to anticipate and solve critical materials issues in a pre-competitive environment. The CMC is a unit of TECHCET.

ABOUT TECHCET: TECHCET CA LLC is an advisory service firm focused on process materials supply chains, electronic materials technology, and materials market analysis for the semiconductor, display, solar/PV, and LED industries. Since 2000, the company has been responsible for producing the SEMATECH Critical Material Reports, covering silicon wafers, semiconductor gases, wet chemicals, CMP consumables, Photoresists, and ALD/CVD Precursors. For additional information about these reports or about CMC Fabs membership or associate-membership for suppliers please contact Diane Scott at [email protected]  +1-480-332-8336, or go to www.techcet.com or www.cmcfabs.org.

Researchers at Duke University and North Carolina State University have demonstrated the first custom semiconductor microparticles that can be steered into various configurations repeatedly while suspended in water.

With an initial six custom particles that predictably interact with one another in the presence of alternating current (AC) electric fields of varying frequencies, the study presents the first steps toward realizing advanced applications such as artificial muscles and reconfigurable computer systems.

The study appears online on May 3 in the journal Nature Communications.

“We’ve engineered and encoded multiple dynamic responses in different microparticles to create a reconfigurable silicon toolbox,” said Ugonna Ohiri, a recently graduated electrical engineering doctoral student from Duke and first author of the paper. “By providing a means of controllably assembling and disassembling these particles, we’re bringing a new tool to the field of active matter.”

While previous researchers have worked to define self-assembling systems, few have worked with semiconductor particles, and none have explored the wide range of custom shapes, sizes and coatings that are available to the micro- and nanofabrication industry. Engineering particles from silicon presents the opportunity to physically realize electronic devices that can self-assemble and disassemble on demand. Customizing their shapes and sizes presents opportunities to explore a wide-ranging design space of new motile behaviors.

“Most previous work performed using self-assembling particles has been done with shapes such as spheres and other off-the-shelf materials,” said Nan Jokerst, the J. A. Jones Professor of Electrical and Computer Engineering at Duke. “Now that we can customize whatever arbitrary shapes, electrical characteristics and patterned coatings we want with silicon, a whole new world is opening up.”

In the study, Jokerst and Ohiri fabricated silicon particles of various shapes, sizes and electrical properties. In collaboration with Orlin Velev, the INVISTA Professor of Chemical and Biomolecular Engineering at NC State, they characterized how these particles responded to different magnitudes and frequencies of electric fields while submerged in water.

Based on these observations, the researchers then fabricated new batches of customized particles that were likely to exhibit the behaviors they were looking for, resulting in six different engineered silicon microparticle compositions that could move through water, synchronize their motions, and reversibly assemble and disassemble on demand.

The thin film particles are 10-micron by 20-micron rectangles that are 3.5 microns thick. They’re fabricated using Silicon-on-Insulator (SOI) technology. Since they can be made using the same fabrication technology that produces integrated circuits, millions of identical particles could be produced at a time.

“The idea is that eventually we’re going to be able to make silicon computational systems that assemble, disassemble and then reassemble in a different format,” said Jokerst. “That’s a long way off in the future, but this work provides a sense of the capabilities that are out there and is the first demonstration of how we might achieve those sorts of devices.”

That is, however, only the tip of the proverbial iceberg. Some of the particles were fabricated with both p-type and n-type regions to create p-n junctions — common electrical components that allow electricity to pass in only one direction. Tiny metal patterns were also placed on the particles’ surfaces to create p-n junction diodes with contacts. In the future, researchers could even engineer particles with patterns using other electrically conductive or insulating materials, complex integrated circuits, or microprocessors on or within the silicon.

“This work is just a small snapshot of the tools we have to control particle dynamics,” said Ohiri. “We haven’t even scratched the surface of all of the behaviors that we can engineer, but we hope that this multidisciplinary study can pioneer future studies to design artificial active materials.”

A simple method that uses hydrogen chloride can better control the crystal structure of a common semiconductor and shows promise for novel high-powered electronic applications.

The electronic components used in computers and mobile devices operate at relatively lower power. But high-power applications, such as controlling electrical power grids, require alternative materials that can cope with much higher voltages. For example, an insulating material begins to conduct electricity when the field is high enough, an effect known as electrical breakdown. For this reason, power electronics often use nitride-based semiconductors, such as gallium nitride, which have a very high breakdown field and can be epitaxially grown to create multilayered semiconductors.

However, ever-increasing energy demands and the desire to make electricity distribution more efficient requires even more electrically robust materials. Gallium oxide (Ga2O3) has a theoretical breakdown field more than twice that of gallium-nitride alloys and so has emerged as an exciting candidate for this function. The latest challenge however is a simple way to deposit high-quality gallium oxide on the substrates commonly used for power electronics, such as sapphire.

Haiding Sun, Xiaohang Li, and co-workers from KAUST worked with industry partners Structured Materials Industries, Inc. in the U.S. to demonstrate a relatively simple method to control the crystal structure of gallium oxides on a sapphire substrate using a technology known as metalorganic chemical vapor deposition (MOCVD). “We were able to control the growth by changing just one parameter: the flow rate of hydrogen chloride in the chamber,” explains Sun. “This is the first time that hydrogen chloride has been used during oxide growth in an MOCVD reactor.”

Working in a clean suit in the lab, Dr. Sun holds up a gallium-oxide template. Credit: © 2018 KAUST

Working in a clean suit in the lab, Dr. Sun holds up a gallium-oxide template. Credit: © 2018 KAUST

The atoms in gallium oxide can be arranged in a number of different forms known as polymorphs. β­­­?Ga2O3 is the most stable polymorph but is difficult to grow on substrates of other materials. ε?Ga2O3 has been grown on sapphire but its growth rate has been difficult to control.

Different polymorphs of gallium oxide can be grown in a MOCVD chamber by controlling the flow of hydrogen chloride.

Different polymorphs of gallium oxide can be grown in a MOCVD chamber by controlling the flow of hydrogen chloride.

To meet growing market demand for high-density 2.5D and 3D stacked semiconductor solutions, Silicon Valley-based ALLVIA, Inc. has expanded its in-house capabilities to include the formation of through-quartz vias (TQV) ranging from 15 microns in diameter and 100 microns deep to 50 microns in diameter and 250 microns deep. ALLVIA’s new TQV solution significantly improves the performance of 3D-ICs by creating IC interconnects with lower parasitic capacitance than can be achieved with the earlier generation of through-silicon via (TSV) technology.

he company had been outsourcing the production of via holes in the fused silica (quartz) that it uses, but its newly added capability brings all via-drilling operations in-house, expanding ALLVIA’s intellectual property and reducing the cost of production. The company will continue to apply its proprietary technology to fill the high-aspect-ratio via holes with copper plating to fabricate finished interposer products.

Sergey Savastiouk, CEO of ALLVIA, said, “Performing our own via drilling in fused silica allows us to improve turnaround times and production volumes for our customers while also delivering better quality using our state-of-the-art technology for copper plating, chemical mechanical polishing and deep via thin-film deposition.”

In addition to providing via foundry services, ALLVIA applies its technology in manufacturing and selling ultra-thin quartz interposers that form the electrical connections between a silicon chip and a printed circuit board.

Engineers at the University of California, Riverside, have demonstrated prototype devices made of an exotic material that can conduct a current density 50 times greater than conventional copper interconnect technology.

Current density is the amount of electrical current per cross-sectional area at a given point. As transistors in integrated circuits become smaller and smaller, they need higher and higher current densities to perform at the desired level. Most conventional electrical conductors, such as copper, tend to break due to overheating or other factors at high current densities, presenting a barrier to creating increasingly small components.

Microscopy image of an electronic device made with 1D ZrTe3 nanoribbons. The nanoribbon channel is indicated in green color. The metal contacts are shown in yellow color. Note than owing to the nanometer scale thickness the yellow metal contacts appear to be under the green channel while in reality they are on top. Credit: Balandin lab, UC Riverside

Microscopy image of an electronic device made with 1D ZrTe3 nanoribbons. The nanoribbon channel is indicated in green color. The metal contacts are shown in yellow color. Note than owing to the nanometer scale thickness the yellow metal contacts appear to be under the green channel while in reality they are on top. Credit: Balandin lab, UC Riverside

The electronics industry needs alternatives to silicon and copper that can sustain extremely high current densities at sizes of just a few nanometers.

The advent of graphene resulted in a massive, worldwide effort directed at investigation of other two-dimensional, or 2D, layered materials that would meet the need for nanoscale electronic components that can sustain a high current density. While 2D materials consist of a single layer of atoms, 1D materials consist of individual chains of atoms weakly bound to one another, but their potential for electronics has not been as widely studied.

One can think of 2D materials as thin slices of bread while 1D materials are like spaghetti. Compared to 1D materials, 2D materials seem huge.

A group of researchers led by Alexander A. Balandin, a distinguished professor of electrical and computer engineering in the Marlan and Rosemary Bourns College of Engineering at UC Riverside, discovered that zirconium tritelluride, or ZrTe3, nanoribbons have an exceptionally high current density that far exceeds that of any conventional metals like copper.

The new strategy undertaken by the UC Riverside team pushes research from two-dimensional to one-dimensional materials­­– an important advance for the future generation of electronics.

“Conventional metals are polycrystalline. They have grain boundaries and surface roughness, which scatter electrons,” Balandin said. “Quasi-one-dimensional materials such as ZrTe3consist of single-crystal atomic chains in one direction. They do not have grain boundaries and often have atomically smooth surfaces after exfoliation. We attributed the exceptionally high current density in ZrTe3 to the single-crystal nature of quasi-1D materials.”

In principle, such quasi-1D materials could be grown directly into nanowires with a cross-section that corresponds to an individual atomic thread, or chain. In the present study the level of the current sustained by the ZrTe3 quantum wires was higher than reported for any metals or other 1D materials. It almost reaches the current density in carbon nanotubes and graphene.

Electronic devices depend on special wiring to carry information between different parts of a circuit or system. As developers miniaturize devices, their internal parts also must become smaller, and the interconnects that carry information between parts must become smallest of all. Depending on how they are configured, the ZrTe3 nanoribbons could be made into either nanometer-scale local interconnects or device channels for components of the tiniest devices.

The UC Riverside group’s experiments were conducted with nanoribbons that had been sliced from a pre-made sheet of material. Industrial applications need to grow nanoribbon directly on the wafer. This manufacturing process is already under development, and Balandin believes 1D nanomaterials hold possibilities for applications in future electronics.

“The most exciting thing about the quasi-1D materials is that they can be truly synthesized into the channels or interconnects with the ultimately small cross-section of one atomic thread– approximately one nanometer by one nanometer,” Balandin said.

Research appearing today in Nature Communications finds useful new information-handling potential in samples of tin(II) sulfide (SnS), a candidate “valleytronics” transistor material that might one day enable chipmakers to pack more computing power onto microchips.

Valleytronics utilizes different local energy extrema (valleys) with selection rules to store 0s and 1s. In SnS, these extrema have different shapes and responses to different polarizations of light, allowing the 0s and 1s to be directly recognized. This schematic illustrates the variation of electron energy in different states, represented by curved surfaces in space. The two valleys of the curved surface are shown. Credit: Berkeley Lab

Valleytronics utilizes different local energy extrema (valleys) with selection rules to store 0s and 1s. In SnS, these extrema have different shapes and responses to different polarizations of light, allowing the 0s and 1s to be directly recognized. This schematic illustrates the variation of electron energy in different states, represented by curved surfaces in space. The two valleys of the curved surface are shown. Credit: Berkeley Lab

The research was led by Jie Yao of the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and Shuren Lin of UC Berkeley’s Department of Materials Science and Engineering and included scientists from Singapore and China. Berkeley Lab’s Molecular Foundry, a DOE Office of Science user facility, contributed to the work.

For several decades, improvements in conventional transistor materials have been sufficient to sustain Moore’s Law – the historical pattern of microchip manufacturers packing more transistors (and thus more information storage and handling capacity) into a given volume of silicon. Today, however, chipmakers are concerned that they might soon reach the fundamental limits of conventional materials. If they can’t continue to pack more transistors into smaller spaces, they worry that Moore’s Law would break down, preventing future circuits from becoming smaller and more powerful than their predecessors.

That’s why researchers worldwide are on the hunt for new materials that can compute in smaller spaces, primarily by taking advantage of the additional degrees of freedom that the materials offer – in other words, using a material’s unique properties to compute more 0s and 1s in the same space. Spintronics, for example, is a concept for transistors that harnesses the up and down spins of electrons in materials as the on/off transistor states.

Valleytronics, another emerging approach, utilizes the highly selective response of candidate crystalline materials under specific illumination conditions to denote their on/off states – that is, using the materials’ band structures so that the information of 0s and 1s is stored in separate energy valleys of electrons, which are dependent on the crystal structures of the materials.

In this new study, the research team has shown that tin(II) sulfide (SnS) is able to absorb different polarizations of light and then selectively reemit light of different colors at different polarizations. This is useful for concurrently accessing both the usual electronic – and the material’s valleytronic – degrees of freedom, which would substantially increase the computing power and data storage density of circuits made with the material.

“We show a new material with distinctive energy valleys that can be directly identified and separately controlled,” said Yao. “This is important because it provides us a platform to understand how valley signatures are carried by electrons and how information can be easily stored and processed between the valleys, which are of both scientific and engineering significance.”

Lin, the first author of the paper, said the material is different from previously investigated candidate valleytronics materials because it possesses such selectivity at room temperature without additional biases apart from the excitation light source, which alleviates the previously stringent requirements in controlling the valleys. Compared to its predecessor materials, SnS is also much easier to process.

With this finding, researchers will be able to develop operational valleytronic devices, which may one day be integrated into electronic circuits. The unique coupling between light and valleys in this new material may also pave the way toward future hybrid electronic/photonic chips.

Berkeley Lab’s “Beyond Moore’s Law” initiative leverages the basic science capabilities and unique user facilities of Berkeley Lab and UC Berkeley to evaluate promising candidates for next-generation electronics and computing technologies. Its objective is to build close partnerships with industry to accelerate the time it typically takes to move from the discovery of a technology to its scale-up and commercialization.

Spin Transfer Technologies, Inc., the developer of advanced STT-MRAM for embedded SRAM and stand-alone DRAM applications, today announced results of its unique Precessional Spin Current (PSC™) structure. The results from advanced testing of the PSC structure confirm that it will increase the spin-torque efficiency of any MRAM device by 40-70 percent — enabling dramatically higher data retention while consuming less power. This gain translates to retention times lengthening by a factor of over 10,000 (e.g., 1 hour retention becomes more than 1 year retention) while reducing write current. Improved efficiency is critical for enabling MRAM to replace SRAM and DRAM in mobile, datacenter and AI applications, as well as for improving retention and performance in high-temperature automotive applications. The company reported these results at the prestigious Intermag 2018 Conference.

Spin-torque efficiency is one of the core performance metrics of the pMTJ (perpendicular magnetic tunnel junction — the “bit” that stores the memory state in an MRAM memory) and is defined by the ratio between the thermal retention barrier, measuring how long data can be reliably stored in the memory, and the switching current necessary to change the value of the bit. In previous MRAM implementations, increasing the energy barrier to increase retention would require a proportional increase in write current — leading to higher power consumption and much faster wear-out of the pMTJ devices (lower endurance). The PSC structure is a breakthrough because it effectively decouples the static energy barrier that determines retention from the dynamic switching processes that govern the switching current. As a result, when the PSC structure is added to any pMTJ, benefits include:

  • A higher energy barrier when the pMTJ does not have current flowing through it, which is ideal for retaining data for long periods
  • An increased spin polarization when current is flowing and the device is writing a new state, which is ideal for minimizing switching current and extending the life of the device by many orders of magnitude

The PSC structure was designed from the outset to be modular and fabricated with any pMTJ — either the company’s own pMTJs, or a pMTJ from other sources. The PSC structure is fabricated during the pMTJ deposition process and adds approximately 4nm to the height of the pMTJ stack. The structure is compatible with a wide range of standard MRAM manufacturing processes, materials and tool sets — enabling any foundry to readily incorporate the PSC structure into existing pMTJ stacks without adding significant complexity or manufacturing costs.

“MRAM is attracting a lot of attention as an embedded memory for ASICs and MCUs, but issues of write current and data retention have caused concern,” said Jim Handy, general director of Objective Analysis. “Spin Transfer Technologies’ new PSC structure shows a lot of promise to solve a number of those issues and pave the path for MRAM to take a significant share of the embedded memory market.”

Spin Transfer Technologies’ testing of the PSC structure involved comparing the performance of the same pMTJ devices with and without PSC for a large number of devices within CMOS test chip arrays at various temperatures and device diameters. The tests exhibited a robust performance advantage due to the PSC structure, both during writing of the low-resistance (“0”) and the high-resistance (“1”) memory states. Some specific examples of the advantages that the data have shown are as follows:

  • Increase of the spin-torque efficiency by up to 70 percent
  • Demonstration of the efficiency gain across a range of sizes (40-60nm) and temperatures (30°C to 125°C)
  • Increase of the thermal energy barriers by 50 percent corresponding to an increase in data retention time of greater than four orders of magnitude while reducing the switching current
  • Reduction of read disturb error rate up to five orders of magnitude

These advantages have come without degradation to other performance parameters. The data for the PSC structure indicate significant potential for enabling high-speed applications as well as high-temperature automotive and other applications. Furthermore, since the data shows that the PSC structure’s efficiency gains actually increase as the pMTJ get smaller, the PSC structure opens new pathways to achieving embedded SRAMs in the latest 7nm and 5nm generations.

“There is a huge demand for a memory with the endurance of SRAM, but with higher density, lower operating power and with non-volatility. We believe the improvements the PSC structure brings to STT-MRAM technology will make it a highly attractive alternative to SRAM for these reasons,” said Mustafa Pinarbasi, CTO and SVP of Magnetics Technology at Spin Transfer Technologies. “We are excited to enable the next generation of STT-MRAM and to shake up the status quo of the memory industry through our innovation.”

In even the most fuel-efficient cars, about 60 percent of the total energy of gasoline is lost through heat in the exhaust pipe and radiator. To combat this, researchers are developing new thermoelectic materials that can convert heat into electricity. These semiconducting materials could recirculate electricity back into the vehicle and improve fuel efficiency by up to 5 percent.

The challenge is, current thermoelectric materials for waste heat recovery are very expensive and time consuming to develop. One of the state of the art materials, made from a combination of hafnium and zirconium (elements most commonly used in nuclear reactors), took 15 years from its initial discovery to optimized performance.

Now, researchers from the Harvard John A. Paulson School of Engineering and Applied Sciences (SEAS) have developed an algorithm that can discover and optimize these materials in a matter of months, relying on solving quantum mechanical equations, without any experimental input.

“These thermoelectric systems are very complicated,” said Boris Kozinsky, a recently appointed Associate Professor of Computational Materials Science at SEAS and senior author of the paper. “Semiconducting materials need to have very specific properties to work in this system, including high electrical conductivity, high thermopower, and low thermal conductivity, so that all that heat gets converted into electricity. Our goal was to find a new material that satisfies all the important properties for thermoelectric conversion while at the same time being stable and cheap.”

Kozinsky co-authored the research with Georgy Samsonidze, a research engineer at the Robert Bosch Research and Technology Center in Cambridge, MA, where both authors conducted most of the research.

In order to find such a material, the team developed an algorithm that can predict electronic transport properties of a material based only on the chemical elements used in the crystalline crystal. The key was to simplify the computational approach for electron-phonon scattering and to speed it up by about 10,000 times, compared to existing algorithms.

The new method and computational screening results are published in Advanced Energy Materials.

Using the improved algorithm, the researchers screened many possible crystal structures, including structures that had never been synthesized before. From those, Kozinsky and Samsonidze whittled the list down to several interesting candidates. Of those candidates, the researchers did further computational optimization and sent the top performers to the experimental team.

In an earlier effort experimentalists synthesized the top candidates suggested by these computations and found a material that was as efficient and as stable as previous thermoelectric materials but 10 times cheaper. The total time from initial screening to working devices: 15 months.

“We did in 15 months of computation and experimentation what took 15 years for previous materials to be optimized,” said Kozinsky. “What’s really exciting is that we’re probably not fully understanding the extent of the simplification yet. We could potentially make this method even faster and cheaper.”

Kozinsky said he hopes to improve the new methodology and use it to explore electronic transport in a wider class of new exotic materials such as topological insulators.

Graphene has many properties; it is e.g. an extremely good conductor. But it does not absorb light very well. To remedy this limiting aspect of what is an otherwise amazing material, physicists resort to embedding a sheet of graphene in a flat photonic crystal, which is excellent for controlling the flow of light. The combination endows graphene with substantially enhanced light-absorbing capabilities. In a new study published in EPJ B, Arezou Rashidi and Abdolrahman Namdar from the University of Tabriz, Iran demonstrate that, by altering the temperature in such a hybrid cavity structure, they can tune its capacity for optical absorption. They explain that it is the thermal expansion and thermo-optical effects which give the graphene these optical characteristics. Potential applications include light sensors, ultra-fast lasers, and systems capable of modulating incoming optical beams.

The authors study the light absorption of the material as a function of temperature, the chemical energy potential, the light polarisation and its incidence angles. To do so, they use a modelling method called the transfer matrix method. They find that for normal light incidence, there is enhanced absorption at room temperature, while the absorption peak is shifted toward the red as the temperature increases.

Absorption on the plane of incident angle and wavelength. Credit: Springer

Absorption on the plane of incident angle and wavelength. Credit: Springer

As light comes in at an angle, the authors show that the absorption peaks are sensitive to the incident angles as well as the polarisation state of the light. They also find that by increasing the incident angle, the peak wavelength is shifted toward the blue.

They conclude that the peak wavelength can be controlled by varying either the temperature or incident angle, as well as the chemical energy potential of graphene. This shows that there are a number of tunable features that could be exploited for the design of graphene-based nano-devices, such as temperature-sensitive absorbers and sensors.

Japanese researchers have developed a new method to build large areas of semiconductive material that is just two molecules thick and a total of 4.4 nanometers tall. The films function as thin film transistors, and have potential future applications in flexible electronics or chemical detectors. These thin film transistors are the first example of semiconductive single molecular bilayers created with liquid solution processing, a standard manufacturing process that minimizes costs.

Top surface view of 3-D computer model (left) and Atomic Force Microscopy image (right) of the new film made by University of Tokyo scientists. The well-organized structure of the molecules is visible in both the 3-D computer model and microscope image as a herringbone or cross-hair pattern. The color differences in the microscopy image are a result of the different lengths of the molecules' tails; the length differences cause the geometric frustration that prevents layers from stacking. pm = picometers, nm = nanometers. Credit: Shunto Arai and Tatsuo Hasegawa

Top surface view of 3-D computer model (left) and Atomic Force Microscopy image (right) of the new film made by University of Tokyo scientists. The well-organized structure of the molecules is visible in both the 3-D computer model and microscope image as a herringbone or cross-hair pattern. The color differences in the microscopy image are a result of the different lengths of the molecules’ tails; the length differences cause the geometric frustration that prevents layers from stacking. pm = picometers, nm = nanometers. Credit: Shunto Arai and Tatsuo Hasegawa

“We want to give electronic devices the features of real cell membranes: flexible, strong, sensitive, and super thin. We found a novel way to design semiconductive single molecular bilayers that allows us to manufacture large surface areas, up to 100 square centimeters (39 square inches). They can function as high performance thin film transistors and could have many applications in the future,” said Assistant Professor Shunto Arai, the first author on the recent research publication.

Professor Tatsuo Hasegawa of the University of Tokyo Department of Applied Physics led the team that built the new film. The breakthrough responsible for their success is a concept called geometric frustration, which uses a molecular shape that makes it difficult for molecules to settle in multiple layers on top of each other.

The film is transparent, but the forces of attraction and repulsion between the molecules create an organized, repeated herringbone pattern when the film is viewed from above through a microscope. The overall molecular structure of the bilayer is highly stable. Researchers believe it should be possible to build the same structure out of different molecules with different functionalities.

The individual molecules used in the current film are divided into two regions: a head and a tail. The head of one molecule stacks on top of another, with their tails pointing in opposite directions so the molecules form a vertical line. These two molecules are surrounded by identical head-to-head pairs of molecules, which all together form a sandwich called a molecular bilayer.

Researchers discovered they could prevent additional bilayers from stacking on top by building the bilayer out of molecules with different length tails, so the surfaces of the bilayer are rough and naturally discourage stacking. This effect of different lengths is referred to as geometric frustration.

Standard methods of creating semiconductive molecular bilayers cannot control the thickness without causing cracks or an irregular surface. The geometric frustration of different length tails has allowed researchers to avoid these pitfalls and build a 10cm by 10cm (3.9 inches by 3.9 inches) square of their film using the common industrial method of solution processing.

The semiconductive properties of the bilayer may give the films applications in flexible electronics or chemical detection.

Semiconductors are able to switch between states that allow electricity to flow (conductors) and states that prevent electricity from flowing (insulators). This on-off switching is what allows transistors to quickly change displayed images, such as a picture on an LCD screen. The single molecular bilayer created by the UTokyo team is much faster than amorphous silicon thin film transistors, a common type of semiconductor currently used in electronics.

The team will continue to investigate the properties of geometrically frustrated single molecular bilayers and potential applications for chemical detection. Collaborators based at the National Institute of Advanced Industrial Science and Technology, the Nippon Kayaku Company Limited, Condensed Matter Research Center, and High Energy Accelerator Research Organization also contributed to the research.