Category Archives: Process Materials

By Cherry Sun

Storage and memory chipmaker and SEMI China member Tsinghua Unigroup is gearing up to meet burgeoning product demand with huge investments in its manufacturing plants. But the high-tech enterprise under Tsinghua University is eyeing a much bigger prize – growth of the region’s semiconductor industry and the realization of its ambition to become a more prominent force on the global stage.

Inspired by the national strategy, the Tsinghua Unigroup’s big spends include USD 24 billion in Wuhan (Yangtze Memory Technologies Co., Ltd.,) USD 30 billion in Chengdu, USD 30 billion in Nanjing and USD 100 billion in Chongqing, said Liu Hongyu, senior vice president of Tsinghua Unigroup, speaking at the SEMI China Equipment and Materials Committee meeting last month.

Advanced packaging is another rich vein of opportunity the region is tapping for expansion, said Liu Hongjun, vice president of China Wafer Level CSP Co., Ltd., another SEMI China member attending the event, hosted by NAURA in Beijing. Hongjun sees strong growth for Fan-in, Fan-out, FCBGA, 2.5D and 3DIC, with Fan-out out front.

Liang Sheng, administrative commission director at BDA, a business advisory firm supporting high-technology manufacturing in the E-Town economic development zone, pointed to 5G chips and smart, networked electric automobiles as drivers of the next growth phase of Beijing’s integrated circuit (IC) industry.

Global tailwinds are lifting China’s semiconductor industry and the region’s hopes, with SEMI and major industry analysts raising their semiconductor industry growth projects for 2018 to between 9 percent and 16 percent. According to SEMI’s latest market report, global semiconductor industry manufacturing equipment revenue reached USD 17 billion in the first quarter of 2018, logging all-time highs after jumping 12 percent from the previous quarter and 30 percent year-over-year. Korea was the top-performing region at USD 6.26 billion, followed by China at USD 2.64 billion.

Tighter integration with the rest of the global semiconductor industry is critical to the growth of China’s chip sector, and SEMI China is squarely focused on this assimilation, said SEMI China president Lung Chu. The spearhead of this effort is the SEMI Innovation Investment Platform (SIIP) China, established by SEMI China last year to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions.

To strengthen ties with other regions, SIIP China will stage a number of innovation and investment forums this year including Chinese Night at SEMICON West (July 10-12) and a SIIP China Forum in Silicon Valley (July 15). In August, representatives from the Korea chip industry will visit counterparts in China (August), and a China delegation will travel to Japan for meetings (October). SIIP China is also strengthening the region’s links with Germany and Israel as SEMI serves as a crucial bridge between China’s semiconductor sector and the global industry.

At the invitation of Shanghai authorities and the Ministry of Commerce of the People’s Republic of China, SEMI China in November will join the China International Export & Import Exposition in Shanghai, an event that will underscore China’s commitment to the openness and cooperation of its semiconductor industry with the international chip community. As part of the exposition, SEMI will work with the Ministry of Commerce and domestic chip manufacturers to begin development of a special integrated circuit (IC) zone. SEMI China members are welcome to participate.

With workforce development no less vital to the future of China’s semiconductor industry, the Equipment & Materials Committee offered potential solutions to the industry’s talent gap. Measures included targeting university students and engineers with industry lectures and courses in key cities, campus recruiting, talent training that members said they are willing to help SEMI coordinate and stage and, much like the push to better integrate China with the global semiconductor industry, mobilizing member resources around a campaign to polish the image of the industry to make it more attractive to students and young workers.

Storage and memory chipmaker and SEMI China member Tsinghua Unigroup is gearing up to meet burgeoning product demand with huge investments in its manufacturing plants.

Cherry Sun is a marketing manager at SEMI China. 

Originally published on the SEMI blog.

Rahul Goyal of Intel has been elected to a one-year term as board chair of Silicon Integration Initiative, a research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations.

Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science, Pilani, India, and a master’s degree in computer engineering from Syracuse University, Syracuse, N.Y.

Taking a multiband approach explains ‘electron-hole reverse drag’ and exciton formation

Mystifying experimental results obtained independently by two research groups in the USA seemed to show coupled holes and electrons moving in the opposite direction to theory.

Now, a new theoretical study has explained the previously mysterious result, by showing that this apparently contradictory phenomenon is associated with the bandgap in dual-layer graphene structures, a bandgap which is very much smaller than in conventional semiconductors.

The study authors, which included FLEET collaborator David Neilson at the University of Camerino and FLEET CI Alex Hamilton at the University of New South Wales, found that the new multiband theory fully explained the previously inexplicable experimental results.

Excitons travel across an ultra-low energy transistor without wasted dissipation of energy. Credit: FLEET: ARC Centre of Excellence in Future Low Energy Electronics Technologies

Exciton transport

Exciton transport offers great promise to researchers, including the potential for ultra-low dissipation future electronics.

An exciton is a composite particle: an electron and a ‘hole’ (a positively charged ‘quasiparticle’ caused by the absence of an electron) bound together by their opposite electrical charges.

In an indirect exciton, free electrons in one 2D sheet can be electrostatically bound to holes that are free to travel in the neighbouring 2D sheet.

Because the electrons and holes are each confined to their own 2D sheets, they cannot recombine, but they can electrically bind together if the two 2D sheets are very close (a few nanometres).

If electrons in the top (‘drive’) sheet are accelerated by an applied voltage, then each partnering hole in the lower (‘drag’) sheet can be ‘dragged’ by its electron.

This ‘drag’ on the hole can be measured as an induced voltage across the drag sheet, and is referred to as Coulomb drag.

A goal in such a mechanism is for the exciton to remain bound, and to travel as a superfluid, a quantum state with zero viscosity, and thus without wasted dissipation of energy.

To achieve this superfluid state, precisely engineered 2D materials must be kept only a few nanometres apart, such that the bound electron and hole are much closer to each other than they are to their neighbours in the same sheet.

In the device studied, a sheet of hexagonal-boron-nitride (hBN) separates two sheets of atomically-thin (2D) bilayer graphene, with the insulating hBN preventing recombination of electrons and holes.

Passing a current through one sheet and measuring the drag signal in the other sheet allows experimenters to measure the interactions between electrons in one sheet and holes in the other, and to ultimately detect a clear signature of superfluid formation.

Only recently, new, 2D heterostructures with sufficiently thin insulating barriers have been developed that allow us to observe features brought by strong electron-hole interactions.

Explaining the inexplicable: negative drag

However, experiments published in 2016 showed extremely puzzling results. Under certain experimental conditions, the Coulomb drag was found to be negative – i.e. moving an electron in one direction caused the hole in the other sheet to move in the opposite direction!

These results could not be explained by existing theories.

In this new study, these puzzling results are explained using crucial multi-band processes that had not previously been considered in theoretical models.

Previous experimental studies of Coulomb drag had been performed in conventional semiconductor systems, which have much larger bandgaps.

However bilayer graphene has a very small bandgap, and it can be changed by the perpendicular electric fields from the metal gates positioned above and below the sample.

The calculation of transport in both conduction and valence bands in each of the graphene bilayers was the ‘missing link’ that marries theory to experimental results. The strange negative drag happens when the thermal energy approaches the bandgap energy.

The strong multiband effects also affect the formation of exciton superfluids in bilayer graphene, so this work opens up new possibilities for exploration in exciton superfluids.

The study Multiband Mechanism for the Sign Reversal of Coulomb Drag Observed in Double Bilayer Graphene Heterostructures by M. Zarenia, A.R. Hamilton, F.M. Peeters and D. Neilson was published in Physical Review Letters in July 2018.

Acknowledgement: The study was led by David Neilson, and by Mohammad Zarenia while at the University of Antwerp, Belgium. The authors of the theoretical study worked with data provided by experimentalists from the two US groups: Cory Dean (Columbia University) and Emanuel Tutuc (University of Texas at Austin) who discovered the original puzzling results. The research was supported by the Flemish government (Belgium), the University of New South Wales, the University of Camerino and by the Australian Research Council via FLEET.

Superfluids and FLEET

Exciton superfluids are studied within FLEET’s Research theme 2 for their potential to carry zero-dissipation electronic current, and thus allow the design of ultra-low energy exciton transistors.

The use of twin atomically-thin (2D) sheets to carry the excitons will allow for room-temperature superfluid flow, which is key if the new technology is to become a viable ‘beyond CMOS’ technology. A bilayer-exciton transistor would be a dissipationless switch for information processing.

In a superfluid, scattering is prohibited by quantum statistics, which means that electrons and holes can flow without resistance.

In this single, pure quantum state, all particles flow with the same momentum, so that no energy can be lost through dissipation.

FLEET (the Australian Research Council Centre of Excellence in Future Low-Energy Electronics Technologies) brings together over a hundred Australian and international experts, with the shared mission to develop a new generation of ultra-low energy electronics.

The impetus behind such work is the increasing challenge of energy used in computation, which uses 5-8% of global electricity and is doubling every decade.

A key challenge of such ultra-miniature devices is overheating – their ultra-small surfaces seriously limit the ways for the heat from electrical currents to escape.

Working to address “hotspots” in computer chips that degrade their performance, UCLA engineers have developed a new semiconductor material, defect-free boron arsenide, that is more effective at drawing and dissipating waste heat than any other known semiconductor or metal materials.

This could potentially revolutionize thermal management designs for computer processors and other electronics, or for light-based devices like LEDs.

Illustration showing a schematic of a computer chip with a hotspot (bottom); an electron microscope image of defect-free boron arsenide (middle); and an image showing electron diffraction patterns in boron arsenide. Credit: Hu Research Lab / UCLA Samueli

The study was recently published in Science and was led by Yongjie Hu, UCLA assistant professor of mechanical and aerospace engineering.

Computer processors have continued to shrink down to nanometer sizes where today there can be billions of transistors on a single chip. This phenomenon is described under Moore’s Law, which predicts that the number of transistors on a chip will double about every two years. Each smaller generation of chips helps make computers faster, more powerful and able to do more work. But doing more work also means they’re generating more heat.

Managing heat in electronics has increasingly become one of the biggest challenges in optimizing performance. High heat is an issue for two reasons. First, as transistors shrink in size, more heat is generated within the same footprint. This high heat slows down processor speeds, in particular at “hotspots” on chips where heat concentrates and temperatures soar. Second, a lot of energy is used to keep those processors cool. If CPUs did not get as hot in the first place, then they could work faster and much less energy would be needed to keep them cool.

The UCLA study was the culmination of several years of research by Hu and his students that included designing and making the materials, predictive modeling, and precision measurements of temperatures.

The defect-free boron arsenide, which was made for the first time by the UCLA team, has a record-high thermal conductivity, more than three-times faster at conducting heat than currently used materials, such as silicon carbide and copper, so that heat that would otherwise concentrate in hotspots is quickly flushed away.

“This material could help greatly improve performance and reduce energy demand in all kinds of electronics, from small devices to the most advanced computer data center equipment,” Hu said. “It has excellent potential to be integrated into current manufacturing processes because of its semiconductor properties and the demonstrated capability to scale-up this technology. It could replace current state-of-the-art semiconductor materials for computers and revolutionize the electronics industry.”

The study’s other authors are UCLA graduate students in Hu’s research group: Joonsang Kang, Man Li, Huan Wu, and Huuduy Nguyen.

In addition to the impact for electronic and photonics devices, the study also revealed new fundamental insights into the physics of how heat flows through a material.

“This success exemplifies the power of combining experiments and theory in new materials discovery, and I believe this approach will continue to push the scientific frontiers in many areas, including energy, electronics, and photonics applications,” Hu said.

The international team of scientist of Peter the Great St. Petersburg Polytechnic University (SPbPU), Leibniz University Hannover (Leibniz Universität Hannover) and the Ioffe Institute found a way to improve nanocomposite material which opens a new opportunities to use it in hydrogen economy and other industries. The obtained results are explained in the academic article “The mechanism of charge carrier generation at the TiO2–n-Si heterojunction activated by gold nanoparticles” published in journal Semiconductor Science and Technology.

The study is dedicated to the composite material, a semiconductor based on titanium dioxide. Its applications are widely studied by the researchers all over the world. But the processes which take place in this material are very complex. Therefore, to use the semiconductor more effectively, it is necessary to ensure that the energy enclosed between its layers can be released and transmitted.

In framework of the experiments the researchers of SPbPU, Leibniz University Hannover and Ioffe Institute propose a qualitative model to explain the complex processes.

The scientific group used a composite material consisting of a silicon wafer (standard silicon wafer used in electronic devices), gold nanoparticles and a thin layer of titanium dioxide. In the framework of the experiment to transfer the energy inside the material, the researchers intended to isolate nanoparticles from silicon. If nanoparticles are not isolated from the silicon wafer, then the energy can’t be transmitted neither to the silicon nor to the titanium dioxide. It leads to the energy loss.

“The obtained material was a silicon wafer with pillar-like structures grown on its surface. It was used as a substrate for the sample. Gold nanoparticles were situated on top of these pillars and the whole structure was coated with titanium oxide. Thus, nanoparticles contacted only titanium dioxide, and simultaneously were isolated from silicon. The number of boundaries between the layers decreased, we tried to describe the processes in the material. In addition, we assumed that this structure would increase the efficiency of using the energy of light illuminating the surface of our material”, says Dr. Maxim Mishin, professor of Physics, Chemistry, and Technology of Microsystems Equipment Department of SPbPU.

In St. Petersburg, an international scientific group established a model of a new structure, then the main part of the structure was created in Hannover: a silicon wafer with pillars and gold nanoparticles situated on top of it.

The experiment was performed as follows. At first, the wafer was oxidized, i.e. it was covered with a layer of the substrate, and gold nanoparticles were put on top of it.

“After that, we faced the next task: to create pillars and to perform the etching of the substrate so that it is remained under the particles and not and in between them. Considering that we are dealing with nanosizes, the diameter of gold nanoparticles is about 10 nanometers, and the height of the pillar is 80 nanometers, this is not a trivial task. The development of modern nanoelectronics makes it possible to use the so-called “dry” etching methods such as reactive ion etching”, adds Dr. Marc Christopher Wurz from the Institute of Micro Production Technology at Leibniz University Hannover.

According to scientists, the process of technology development had not been rapid: at the first stages of the experiment, while using the ion etching, all gold nanoparticles were simply demolished from the oxidized wafer. In the course of one week, the researchers were selecting the parameters for etching plasma system, so that the gold nanoparticles remained on the surface. The whole experiment was conducted within 10 days.

This scientific project is ongoing. The researchers mention that this nanocomposite material can be used in optical devices operating in the visible light spectrum. In addition, it can be used as a catalyst to produce hydrogen from water, or, for example, to purify water by stimulating the decomposition of complex molecules. In addition, this material may be useful as an element of a sensor which detects a gas leak or increased concentration of harmful substances in the air.

With companies like Google, Microsoft, and IBM all racing to create the world’s first practical quantum computer, scientists worldwide are exploring the potential materials that could be used to build them.

Now, Associate Professor Yang Hyunsoo and his team from the Department of Electrical and Computer Engineering at the National University of Singapore (NUS) Faculty of Engineering have demonstrated a new method which could be used to bring quantum computing closer to reality.

“The NUS team, together with our collaborators from Rutgers, The State University of New Jersey in the United States and RMIT University in Australia, showed a practical way to observe and examine the quantum effects of electrons in topological insulators and heavy metals which could later pave the way for the development of advanced quantum computing components and devices,” explained Assoc Prof Yang.

The findings of the study were published in the scientific journal Nature Communications in June 2018.

The advantage of quantum computers

Quantum computers are still in the early stages of development but are already displaying computing speeds millions of times faster than traditional technologies. As such, it is predicted that when quantum computing becomes more readily available, it will be able to answer some of the world’s toughest questions in everything from finance to physics. This remarkable processing power is made possible by the radical way that quantum computers operate – using light rather than electricity.

Classical computers push electrons through devices which code information into binary states of ones and zeros. In contrast, quantum computers use laser light to interact with electrons in materials to measure the phenomenon of electron “spin”. These spinning electron states replace the ones and zeros used as the basis for traditional computers, and because they can exist in many spin states simultaneously, this allows for much more complex computing to be performed.

However, harnessing information based on the interactions of light and electrons is easier said than done. These interactions are incredibly complex and like anything in the quantum world there is a degree of uncertainty when trying to predict behaviour. As such, a reliable and practical way to observe these quantum effects has been sought-after in recent research to help in the discovery of more advanced quantum computing devices.

Visualising quantum spin effects

The real breakthrough from the scientists at NUS was the ability to “see” for the first time particular spin phenomena in topological insulators and metals using a scanning photovoltage microscope.

Topological insulators are electronic materials that are insulating in their interior but support conducting states on their surface, thus enabling electrons to flow along the surface of the material.

Assoc Prof Yang and his team examined platinum metal as well as topological insulators Bi2Se3 and BiSbTeSe2. An applied electrical current influenced the electron spin at the quantum level for all of these materials and the scientists were able to directly visualise this change using polarised light from the microscope.

Additionally, unlike other observational techniques, the innovative experimental setup meant that the results could be gathered at room temperature, making this a practical method of visualisation which is applicable to many other materials.

Mr Liu Yang, who is a PhD student with the Department and first author of the study, said, “Our method can be used as a powerful and universal tool to detect the spin accumulations in various materials systems. This means that developing better devices for quantum computers will become easier now that these phenomena can be directly observed in this way.”

Next steps

Moving forward, Assoc Prof Yang and his team are planning to test their new method on more novel materials with novel spin properties. The team hopes to work with industry partners to further explore the various applications of this unique technique, with a focus on developing the devices used in future quantum computers.

By Pete Singer

Nitrous oxide (N2O) has a variety of uses in the semiconductor manufacturing industry. It is the oxygen source for chemical vapor deposition of silicon oxy-nitride (doped or undoped) or silicon dioxide, where it is used in conjunction with deposition gases such as silane. It’s also used in diffusion (oxidation, nitridation, etc.), rapid thermal processing (RTP) and for chamber seasoning.

Why these uses – and more importantly what happens to the gas afterward — may soon becoming under more scrutiny because it is being included for the first time in the IPPC (Intergovernmental Panel on Climate Change) GHG (Greenhouse Gas) guidelines. The IPCC has refined guidelines released in 2006 and expect to have a new revision in 2019. “Refined guidelines are actually up and coming and the inclusion of nitrous oxide in them is a major revision from the 2006 document,” said Mike Czerniak, Environmental Solutions Business development Manager, Edwards. Czerniak is on the IPPC committee and lead author of the semiconductor section.

Although the semiconductor industry uses a very small amount of N2O compared to other applications (dentistry, whip cream, drag racing, scuba diving), it is a concern because after CO2and CH4, N2O is the 3rd most prevalent man-induced GHG, accounting for 7% of emissions. According to the U.S. Environmental Protection Agency, 5% of U.S. N2O originates from industrial manufacturing, including semiconductor manufacturing.

Czerniak said the semiconductor industry been very proactive about trying to offset and reduce its carbon dioxide footprint. “The aspiration set by the world’s semiconductor council to reduce the carbon footprint of a chip to 30 percent of what it was in 2010, which itself was a massive reduction of what it used to be back in the last millennium,” he said. Unfortunately, although that trend had been going down for the first half of the decade, it started going up again in 2016. “although each individual processing step has a much lower carbon footprint than it used to have, the number of processing steps is much higher than they used to be,” Czerniak explain. “In the 1990s, it might take 300-400 processing steps to make a chip. Nowadays you’re looking at 2,000-4,000 steps.”

There are two ways of abating N20 so that it does not pollute the atmosphere: reduce it or oxidize it.  Oxidizing it – which creates NO2and NO (and other oxides know as NOx) — is not the way to go, according to Czerniak. “These oxides have their own problems. NOx is a gas that most countries are trying to reduce emissions of. It’s usually found as a byproduct of fuel combustion, particularly in things like automobiles and it adds to things like acid rain,” he said.

Edwards’ view is that it’s much better to minimize the formation of the NOx in the first place. “The good news is that it is possible inside a combustion abatement system where the gas comes in at the top, we burn a fuel gas and air on a combustor pad and basically the main reactant gas then is water vapor, which we use to remove the fluorine effluent, which is the one we normally try to get rid of from chamber cleans,” Czerniak said.

The tricky part is that information from the tool is required. “We can — when there is nitrous oxide present on a signal from the processing tool — add additional methane fuel into the incoming gas specifically to act as a reducing agent to reduce the nitrous oxide to nitrogen and water vapor,” he explained. “We inject it at just the right flow rate to effectively get rid of the nitrous oxide without forming the undesirable NOx byproducts.”

Figure 1 showshowcareful control of combustion conditions make them reduce rather than oxidizing during the N2O step by the addition of CH4. 30 slm N2O represents two typical process chambers.

“It’s not complicated technology,” Czerniak concluded. “You just have to do it right.”

Leti, a research institute of CEA Tech, and Soitec, a designer and manufacturer of innovative semiconductor materials, today announced a new collaboration and five-year partnership agreement to drive the R&D of advanced engineered substrates, including SOI and beyond. This agreement brings the traditional Leti-Soitec partnership to a whole new dimension and includes the launch of a world-class prototyping hub associating equipment partners to pioneer with new materials, The Substrate Innovation Center will feature access to shared Leti-Soitec expertise around a focused pilot line. Key benefits for partners include access to early exploratory sampling and prototyping, collaborative analysis, and early learning at the substrate level, eventually leading to streamlined product viability and roadmap planning at the system level.

Leading chip makers and foundries worldwide use Soitec products to manufacture chips for consumer applications targeting performance, connectivity, and efficiency with extremely low energy consumption. Applications include smart phones, data centers, automotive, imagers, and medical and industrial equipment, but this list is always growing, along with the need for flexibility to explore new applications starting at the substrate level. At the Substrate Innovation Center, located on Leti’s campus, Leti and Soitec engineers will explore and develop innovative substrate features, expanding to new fields and applications with a special focus on 4G/5G connectivity, artificial intelligence, sensors and display, automotive, photonics, and edge computing.

“Material innovation and substrate engineering make entire new horizons possible. The Substrate Innovation Center will unleash the power of substrate R&D collaboration beyond the typical product road maps, beyond the typical constraints,” said Paul Boudre, Soitec CEO. “The Substrate Innovation Center is a one-of-a-kind opportunity open to all industry partners within the semiconductor value chain.”

Whereas a typical manufacturing facility has limited flexibility to try new solutions and cannot afford to take risks with prototyping, the mission of the Substrate Innovation Center is to become the world’s preferred hub for evaluating and designing engineered substrate solutions to address the future needs of the industry, inclusive of all the key players, from compound suppliers to product designers. Using state of the art, quality-controlled clean room facilities, and the latest industry-grade equipment and materials, Leti and Soitec engineers will conduct testing and evaluation at all levels of advanced substrate R&D.

“Leti and Soitec’s collaboration on SOI and differentiated materials, which extends back to Soitec’s launch in 1992, has produced innovative technologies that are vital to a wide range of consumer and industrial products and components,” said Emmanuel Sabonnadière, Leti CEO. “This new common hub at Leti’s campus marks the next step in this ongoing partnership. By jointly working with foundries, fabless, and system companies, we provide our partners with a strong edge for their future products.”

Intel has won SEMI’s 2018 Award for the Americas. SEMI honored the celebrated chipmaker for pioneering process and integration breakthroughs that enabled the first high-volume Integrated Silicon Photonics Transceiver. The award was presented yesterday at SEMICON West 2018.

SEMI’s Americas Awards recognize technology developments with a major impact on the semiconductor industry and the world.

The Intel® Silicon Photonics 100G CWDM4 (Coarse Wavelength Division Multiplexing 4-lane) QSFP28 optical transceiver, a highly integrated optical connectivity solution, combines the power of optics and the scalability of silicon. The small form-factor, high-speed, low-power consumption 100G optical transceivers are used in optical interconnects for data communications applications, including large-scale cloud and data centers, and in Ethernet switch, router, and client telecommunications interfaces.

Dr. Thomas Liljeberg, senior director of R&D for Intel Silicon Photonics, accepted the award on behalf of Intel. Dr. Liljeberg is one of the technologists responsible for bringing Intel’s silicon photonics 100G transceivers to high-volume production.

“Every year SEMI honors key technological contributions and industry leadership through the SEMI Award,” said David Anderson, president, SEMI Americas. “Intel was instrumental in delivering technologies that will influence product design and system architecture for many years to come. Congratulations to Intel for this significant accomplishment.”

“The 2018 Award recognizes the enablement of high-volume manufacturing through technology leadership and collaboration with key vendors in the supply chain,” said Bill Bottoms, chairman of the SEMI Awards Advisory Committee. “Intel’s collaboration is a model for how the industry can accelerate innovation in the future.”

SEMI established the SEMI Award in 1979 to recognize outstanding technical achievement and meritorious contributions in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The SEMI Americas award is the highest honor conferred by the SEMI Americas region. It is open to individuals or teams from industry or academia whose specific accomplishments have a broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/semiaward.

SEMI yesterday honored two industry leaders at SEMICON West 2018 for their outstanding accomplishments in developing Standards for the electronics and related industries. The SEMI Standards awards were announced at the SEMI International Standards reception.

The Technical Editor Award recognizes the efforts of a member to ensure the technical excellence of a committee’s Standards. This year’s recipient is Sean Larsen of Lam Research. Mr. Larsen has led the North America EHS Committee and multiple EHS task forces for over a decade. His knowledge of the Regulations, Procedure Manual, and Style Manual, combined with his vast experience in the industry, ensures that complex safety matters are explained in a clear, consistent manner, and ballot authors frequently rely on him for his technical skills in preparing ballots.

In addition to co-chairing the North America EHS Committee, Mr. Larsen is currently the co-leader of the SEMI S22 (Electrical Design) Revision TF, the SEMI S2 Non-Ionizing Radiation TF, the SEMI S2 Korean High Pressure Gas Safety TF, and the Control of Hazardous Energy TF.

The Corporate Device Member Award recognizes the participation of the user community and is presented to individuals from device manufacturers. This year’s recipient is Don Hadder of Intel. Mr. Hadder has been actively involved in the Standards Program for several years, and currently leads the Chemical Analytical Methods Task Force and chairs the North America Liquid Chemicals Committee. He has successfully re-energized the committee, which is now focused on enabling continued process control improvements for advanced nodes. He recently drove the development of a critical new standard: SEMI C96, Test Method for Determining Density of Chemical Mechanical Polish Slurries, the first document in a series of SEMI Standards that will be devoted specifically to CMP slurry users, IDMs, slurry suppliers, metrology manufacturers and OEM equipment suppliers.

Mr. Hadder has worked at Intel for 23 years, where his experience and system ownership has been in Diffusion, Wet Etch, Planar-CMP, Ultra-Pure Water, Waste Treatment Systems, Abatement and Vacuum Systems, Bulk and Specialty Gas, Bulk Chemical Delivery and Planar Chemical Delivery.