Category Archives: Process Materials

Scientists at the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) reported significant advances in the thermoelectric performance of organic semiconductors based on carbon nanotube thin films that could be integrated into fabrics to convert waste heat into electricity or serve as a small power source.

The research demonstrates significant potential for semiconducting single-walled carbon nanotubes (SWCNTs) as the primary material for efficient thermoelectric generators, rather than being used as a component in a “composite” thermoelectric material containing, for example, carbon nanotubes and a polymer. The discovery is outlined in the new Energy & Environmental Science paper, Large n- and p-type thermoelectric power factors from doped semiconducting single-walled carbon nanotube thin films.

“There are some inherent advantages to doing things this way,” said Jeffrey Blackburn, a senior scientist in NREL’s Chemical and Materials Science and Technology center and co-lead author of the paper with Andrew Ferguson. These advantages include the promise of solution-processed semiconductors that are lightweight and flexible and inexpensive to manufacture. Other NREL authors are Bradley MacLeod, Rachelle Ihly, Zbyslaw Owczarczyk, and Katherine Hurst. The NREL authors also teamed with collaborators from the University of Denver and partners at International Thermodyne, Inc., based in Charlotte, N.C.

Ferguson, also a senior scientist in the Chemical and Materials Science and Technology center, said the introduction of SWCNT into fabrics could serve an important function for “wearable” personal electronics. By capturing body heat and converting it into electricity, the semiconductor could power portable electronics or sensors embedded in clothing.

Blackburn and Ferguson published two papers last year on SWCNTs, and the new research builds on their earlier work. The first paper, in Nature Energy, showed the potential that SWCNTs have for thermoelectric applications, but the films prepared in this study retained a large amount of insulating polymer. The second paper, in ACS Energy Letters, demonstrated that removing this “sorting” polymer from an exemplary SWNCT thin film improved thermoelectric properties.

The newest paper revealed that removing polymers from all SWCNT starting materials served to boost the thermoelectric performance and lead to improvements in how charge carriers move through the semiconductor. The paper also demonstrated that the same SWCNT thin film achieved identical performance when doped with either positive or negative charge carriers. These two types of material–called the p-type and the n-type legs, respectively–are needed to generate sufficient power in a thermoelectric device. Semiconducting polymers, another heavily studied organic thermoelectric material, typically produce n-type materials that perform much worse than their p-type counterparts. The fact that SWCNT thin films can make p-type and n-type legs out of the same material with identical performance means that the electrical current in each leg is inherently balanced, which should simplify the fabrication of a device. The highest performing materials had performance metrics that exceed current state-of-the-art solution-processed semiconducting polymer organic thermoelectrics materials.

“We could actually fabricate the device from a single material,” Ferguson said. “In traditional thermoelectric materials you have to take one piece that’s p-type and one piece that’s n-type and then assemble those into a device.”

Veeco Instruments Inc. (Nasdaq: VECO) announced today the completion of a strategic initiative with ALLOS Semiconductors (ALLOS) to demonstrate 200mm GaN-on-Si wafers for Blue/Green micro-LED production. Veeco teamed up with ALLOS to transfer their proprietary epitaxy technology onto the Propel Single-Wafer MOCVD System to enable micro-LED production on existing silicon production lines.

“With the Propel reactor, we have an MOCVD technology that is capable of high yielding GaN Epitaxy that meets all the requirements for processing micro-LED devices in 200 millimeter silicon production lines,” said Burkhard Slischka, CEO of ALLOS Semiconductors. “Within one month we established our technology on Propel and have achieved crack-free, meltback-free wafers with less than 30 micrometers bow, high crystal quality, superior thickness uniformity and wavelength uniformity of less than one nanometer.  Together with Veeco, ALLOS is looking forward to making this technology more widely available to the micro-LED ecosystem.”

Micro-LED display technology consists of <30×30 square micron red, green, blue (RGB) inorganic LEDs that are transferred to the display backplane to form sub-pixels. Direct emission from these high efficiency LEDs offers lower power consumption compared with OLED and LCD while providing superior brightness and contrast for mobile displays, TV and wearables. The manufacturing of micro-LEDs requires high quality, uniform epitaxial wafers to meet the display yield and cost targets.

“In contrast to competing MOCVD platforms, Propel offers leading-edge uniformity and simultaneously achieves excellent film quality as a result of the wide process window afforded by Veeco’s TurboDisc® technology,” said Peo Hansson, Ph.D., Senior Vice President and General Manager of Veeco MOCVD Operations. “Combining Veeco’s leading MOCVD expertise with ALLOS’ GaN-on-Silicon epi-wafer technology enables our customers to develop micro-LEDs cost effectively for new applications in new markets.”

Research by scientists at Swansea University has shown that improvements in nanowire structures will allow for the manufacture of more stable and durable nanotechnology for use in semiconductor devices in the future.

Dr. Alex Lord and Professor Steve Wilks from the Centre for NanoHealth led the collaborative research published in Nano Letters. The research team defined the limits of electrical contact technology to nanowires at atomic scales with world-leading instrumentation and global collaborations that can be used to develop enhanced devices based on the nanomaterials. Well-defined, stable and predictable electrical contacts are essential for any electrical circuit and electronic device because they control the flow of electricity that is fundamental to the operational capability.

Their experiments found for the first time, that atomic changes to the metal catalyst particle edge can entirely alter electrical conduction and most importantly reveal physical evidence of the effects of a long standing problem for electrical contacts known as barrier inhomogeneity. The study revealed the electrical and physical limits of the materials that will allow nanoengineers to select the properties of manufacturable nanowire devices.

One-of-a-kind multi-probe LT Nanoprobe at Swansea University used to obtain the electrical measurements of nanowires that were correlated to atomic resolution imaging. Credit: Swansea University

One-of-a-kind multi-probe LT Nanoprobe at Swansea University used to obtain the electrical measurements of nanowires that were correlated to atomic resolution imaging. Credit: Swansea University

Dr Lord, recently appointed as a Senior Sêr Cymru II Fellow part-funded by the European Regional Development Fund through the Welsh Government, said: “The experiments had a simple premise but were challenging to optimise and allow atomic-scale imaging of the interfaces. However, it was essential to this study and will allow many more materials to be investigated in a similar way.

“This research now gives us an understanding of these new effects and will allow engineers in the future to reliably produce electrical contacts to these nanomaterials which is essential for the materials to be used in the technologies of tomorrow.

“The new concepts shown here provide interesting possibilities for bridged nanowire devices such as transient electronics and reactive circuit breakers that respond to changes in electrical signals or environmental factors and provide instantaneous reactions to electrical overload.”

The Swansea research team used specialist experimental equipment at the Centre for NanoHealth and collaborated with Professor Quentin Ramasse of the SuperSTEM Laboratory, Science and Facilities Technology Council1-3 and Dr Frances Ross of the IBM Thomas J. Watson Research Center, USA.3 The scientists were able to physically interact with the nanostructures and measure how atomic changes in the materials affected the electrical performance.

Dr. Frances Ross, IBM, USA, added: “”This research shows the importance of global collaboration, particularly in allowing unique instrumentation to be used to obtain fundamental results that allow nanoscience to deliver the next generation of technologies.”

Nanotechnology is the scaling down of everyday materials by scientists to the size of nanometres (one million times smaller than a millimetre on a standard ruler) and is seen as the future of electronic devices. Progressions in scientific and engineering advances are resulting in new technologies such as computer components for smart devices and sensors to monitor our health and the surrounding environment.

Nanotechnology is having a major influence on the Internet of Things which connects everything from our homes to our cars into a web of communication. All of these new technologies require similar advances in electrical circuits and especially electrical contacts that allow the devices to work correctly with electricity.

Silicon has provided enormous benefits to the power electronics industry. But performance of silicon-based power electronics is nearing maximum capacity.

Enter wide bandgap (WBG) semiconductors. Seen as significantly more energy-efficient, they have emerged as leading contenders in developing field-effect transistors (FETs) for next-generation power electronics. Such FET technology would benefit everything from power-grid distribution of renewable-energy sources to car and train engines.

Diamond is largely recognized as the most ideal material in WBG development, owing to its superior physical properties, which allow devices to operate at much higher temperatures, voltages and frequencies, with reduced semiconductor losses.

A main challenge, however, in realizing the full potential of diamond in an important type of FET — namely, metal-oxide-semiconductor field-effect transistors (MOSFETs) — is the ability to increase the hole channel carrier mobility. This mobility, related to the ease with which current flows, is essential for the on-state current of MOSFETs.

Researchers from France, the United Kingdom and Japan incorporate a new approach to solve this problem by using the deep-depletion regime of bulk-boron-doped diamond MOSFETs. The new proof of concept enables the production of simple diamond MOSFET structures from single boron-doped epilayer stacks. This new method, specific to WBG semiconductors, increases the mobility by an order of magnitude. The results are published this week in Applied Physics Letters, from AIP Publishing.

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

In a typical MOSFET structure, an oxide layer and then a metal gate are formed on top of a semiconductor, which in this case is diamond. By applying a voltage to the metal gate, the carrier density, and hence the conductivity, of the diamond region just under the gate, the channel, can be changed dramatically. The ability to use this electric “field-effect” to control the channel conductivity and switch MOSFETS from conducting (on-state) to highly insulating (off-state) drives their use in power control applications. Many of the diamond MOSFETs demonstrated to date rely on a hydrogen-terminated diamond surface to transfer positively charged carriers, known as holes, into the channel. More recently, operation of oxygen terminated diamond MOS structures in an inversion regime, similar to the common mode of operation of silicon MOSFETS, has been demonstrated. The on-state current of a MOSFET is strongly dependent on the channel mobility and in many of these MOSFET designs, the mobility is sensitive to roughness and defect states at the oxide diamond interface where unwanted carrier scattering occurs.

To address this issue, the researchers explored a different mode of operation, the deep-depletion concept. To build their MOSFET, the researchers deposited a layer of aluminum oxide (Al2O3) at 380 degrees Celsius over an oxygen-terminated thick diamond epitaxial layer. They created holes in the diamond layer by incorporating boron atoms into the layer. Boron has one less valence electron than carbon, so including it leaves a missing electron which acts like the addition of a positive charge, or hole. The bulk epilayer functioned as a thick conducting hole channel. The transistor was switched from the on-state to the off-state by application of a voltage which repelled and depleted the holes — the deep depletion region. In silicon-based transistors, this voltage would have also resulted in formation of an inversion layer and the transistor would not have turned off. The authors were able to demonstrate that the unique properties of diamond, and in particular the large band gap, suppressed formation of the inversion layer allowing operation in the deep depletion regime.

“We fabricated a transistor in which the on-state is ensured by the bulk channel conduction through the boron-doped diamond epilayer,” said Julien Pernot, a researcher at the NEEL Institute in France and an author of the paper. “The off-state is ensured by the thick insulating layer induced by the deep-depletion regime. Our proof of concept paves the way in fully exploiting the potential of diamond for MOSFET applications.” The researchers plan to produce these structures through their new startup called DiamFab.

Pernot observed that similar principles of this work could apply to other WBG semiconductors. “Boron is the doping solution for diamond,” Pernot said, “but other dopant impurities would likely be suitable to enable other wide bandgap semiconductors to reach a stable deep-depletion regime.”

Fibers made of carbon nanotubes configured as wireless antennas can be as good as copper antennas but 20 times lighter, according to Rice University researchers. The antennas may offer practical advantages for aerospace applications and wearable electronics where weight and flexibility are factors.

The research appears in Applied Physics Letters.

The discovery offers more potential applications for the strong, lightweight nanotube fibers developed by the Rice lab of chemist and chemical engineer Matteo Pasquali. The lab introduced the first practical method for making high-conductivity carbon nanotube fibers in 2013 and has since tested them for use as brain implants and in heart surgeries, among other applications.

The research could help engineers who seek to streamline materials for airplanes and spacecraft where weight equals cost. Increased interest in wearables like wrist-worn health monitors and clothing with embedded electronics could benefit from strong, flexible and conductive fiber antennas that send and receive signals, Pasquali said.

The Rice team and colleagues at the National Institute of Standards and Technology (NIST) developed a metric they called “specific radiation efficiency” to judge how well nanotube fibers radiated signals at the common wireless communication frequencies of 1 and 2.4 gigahertz and compared their results with standard copper antennas. They made thread comprising from eight to 128 fibers that are about as thin as a human hair and cut to the same length to test on a custom rig that made straightforward comparisons with copper practical.

“Antennas typically have a specific shape, and you have to design them very carefully,” said Rice graduate student Amram Bengio, the paper’s lead author. “Once they’re in that shape, you want them to stay that way. So one of the first experimental challenges was getting our flexible material to stay put.”

Contrary to earlier results by other labs (which used different carbon nanotube fiber sources), the Rice researchers found the fiber antennas matched copper for radiation efficiency at the same frequencies and diameters. Their results support theories that predicted the performance of nanotube antennas would scale with the density and conductivity of the fiber.

“Not only did we find that we got the same performance as copper for the same diameter and cross-sectional area, but once we took the weight into account, we found we’re basically doing this for 1/20th the weight of copper wire,” Bengio said.

“Applications for this material are a big selling point, but from a scientific perspective, at these frequencies carbon nanotube macro-materials behave like a typical conductor,” he said. Even fibers considered “moderately conductive” showed superior performance, he said. Although manufacturers could simply use thinner copper wires instead of the 30-gauge wires they currently use, those wires would be very fragile and difficult to handle, Pasquali said.

“Amram showed that if you do three things right — make the right fibers, fabricate the antenna correctly and design the antenna according to telecommunication protocols — then you get antennas that work fine,” he said. “As you go to very thin antennas at high frequencies, you get less of a disadvantage compared with copper because copper becomes difficult to handle at thin gauges, whereas nanotubes, with their textile-like behavior, hold up pretty well.”

The huge increase in computing performance in recent decades has been achieved by squeezing ever more transistors into a tighter space on microchips.

However, this downsizing has also meant packing the wiring within microprocessors ever more tightly together, leading to effects such as signal leakage between components, which can slow down communication between different parts of the chip. This delay, known as the “interconnect bottleneck,” is becoming an increasing problem in high-speed computing systems.

One way to tackle the interconnect bottleneck is to use light rather than wires to communicate between different parts of a microchip. This is no easy task, however, as silicon, the material used to build chips, does not emit light easily, according to Pablo Jarillo-Herrero, an associate professor of physics at MIT.

Now, in a paper published today in the journal Nature Nanotechnology, researchers describe a light emitter and detector that can be integrated into silicon CMOS chips. The paper’s first author is MIT postdoc Ya-Qing Bie, who is joined by Jarillo-Herrero and an interdisciplinary team including Dirk Englund, an associate professor of electrical engineering and computer science at MIT.

The device is built from a semiconductor material called molybdenum ditelluride. This ultrathin semiconductor belongs to an emerging group of materials known as two-dimensional transition-metal dichalcogenides.

Unlike conventional semiconductors, the material can be stacked on top of silicon wafers, Jarillo-Herrero says.

“Researchers have been trying to find materials that are compatible with silicon, in order to bring optoelectronics and optical communication on-chip, but so far this has proven very difficult,” Jarillo-Herrero says. “For example, gallium arsenide is very good for optics, but it cannot be grown on silicon very easily because the two semiconductors are incompatible.”

In contrast, the 2-D molybdenum ditelluride can be mechanically attached to any material, Jarillo-Herrero says.

Another difficulty with integrating other semiconductors with silicon is that the materials typically emit light in the visible range, but light at these wavelengths is simply absorbed by silicon.

Molybdenum ditelluride emits light in the infrared range, which is not absorbed by silicon, meaning it can be used for on-chip communication.

To use the material as a light emitter, the researchers first had to convert it into a P-N junction diode, a device in which one side, the P side, is positively charged, while the other, N side, is negatively charged.

In conventional semiconductors, this is typically done by introducing chemical impurities into the material. With the new class of 2-D materials, however, it can be done by simply applying a voltage across metallic gate electrodes placed side-by-side on top of the material.

“That is a significant breakthrough, because it means we do not need to introduce chemical impurities into the material [to create the diode]. We can do it electrically,” Jarillo-Herrero says.

Once the diode is produced, the researchers run a current through the device, causing it to emit light.

“So by using diodes made of molybdenum ditelluride, we are able to fabricate light-emitting diodes (LEDs) compatible with silicon chips,” Jarillo-Herrero says.

The device can also be switched to operate as a photodetector, by reversing the polarity of the voltage applied to the device. This causes it to stop conducting electricity until a light shines on it, when the current restarts.

In this way, the devices are able to both transmit and receive optical signals.

The device is a proof of concept, and a great deal of work still needs to be done before the technology can be developed into a commercial product, Jarillo-Herrero says.

The researchers are now investigating other materials that could be used for on-chip optical communication.

Most telecommunication systems, for example, operate using light with a wavelength of 1.3 or 1.5 micrometers, Jarillo-Herrero says.

However, molybdenum ditelluride emits light at 1.1 micrometers. This makes it suitable for use in the silicon chips found in computers, but unsuitable for telecommunications systems.

“It would be highly desirable if we could develop a similar material, which could emit and detect light at 1.3 or 1.5 micrometers in wavelength, where telecommunication through optical fiber operates,” he says.

To this end, the researchers are exploring another ultrathin material called black phosphorus, which can be tuned to emit light at different wavelengths by altering the number of layers used. They hope to develop devices with the necessary number of layers to allow them to emit light at the two wavelengths while remaining compatible with silicon.

“The hope is that if we are able to communicate on-chip via optical signals instead of electronic signals, we will be able to do so more quickly, and while consuming less power,” Jarillo-Herrero says.

Graphene – a one-atom-thick layer of the stuff in pencils – is a better conductor than copper and is very promising for electronic devices, but with one catch: Electrons that move through it can’t be stopped.

Until now, that is. Scientists at Rutgers University-New Brunswick have learned how to tame the unruly electrons in graphene, paving the way for the ultra-fast transport of electrons with low loss of energy in novel systems. Their study was published online in Nature Nanotechnology.

“This shows we can electrically control the electrons in graphene,” said Eva Y. Andrei, Board of Governors professor in Rutgers’ Department of Physics and Astronomy in the School of Arts and Sciences and the study’s senior author. “In the past, we couldn’t do it. This is the reason people thought that one could not make devices like transistors that require switching with graphene, because their electrons run wild.”

Now it may become possible to realize a graphene nano-scale transistor, Andrei said. Thus far, graphene electronics components include ultra-fast amplifiers, supercapacitors and ultra-low resistivity wires. The addition of a graphene transistor would be an important step towards an all-graphene electronics platform. Other graphene-based applications include ultra-sensitive chemical and biological sensors, filters for desalination and water purification. Graphene is also being developed in flat flexible screens, and paintable and printable electronic circuits.

Graphene is a nano-thin layer of the carbon-based graphite that pencils write with. It is far stronger than steel and a great conductor. But when electrons move through it, they do so in straight lines and their high velocity does not change. “If they hit a barrier, they can’t turn back, so they have to go through it,” Andrei said. “People have been looking at how to control or tame these electrons.”

Her team managed to tame these wild electrons by sending voltage through a high-tech microscope with an extremely sharp tip, also the size of one atom. They created what resembles an optical system by sending voltage through a scanning tunneling microscope, which offers 3-D views of surfaces at the atomic scale. The microscope’s sharp tip creates a force field that traps electrons in graphene or modifies their trajectories, similar to the effect a lens has on light rays. Electrons can easily be trapped and released, providing an efficient on-off switching mechanism, according to Andrei.

“You can trap electrons without making holes in the graphene,” she said. “If you change the voltage, you can release the electrons. So you can catch them and let them go at will.”

The next step would be to scale up by putting extremely thin wires, called nanowires, on top of graphene and controlling the electrons with voltages, she said.

An oversupply of polysilicon will double in 2018 despite strong demand in solar and semiconductor markets, according to a report Opportunities in The Solar Cell Market For Thin Film Technology, recently published by The Information Network (www.theinformationnet.com), a New Tripoli, PA-based market research company.

Consumption of polysilicon is booming as the semiconductor industry, particularly DRAM and NAND, is reaching record revenue and shipment growth. Solar installations are also growing strongly, increasing 35.5% in 2016.

Nevertheless, increased capacity put in place by polysilicon incumbents and capacity growth of Chinese manufactures pegged to increase 35% in 2017 is giving rise to an oversupply that will grow from 7.1% in 2016 to 15.0% in 2018.

As shown in the Table below, the industry will see an oversupply of 76,000 metric tonnes in 2018.

  2016 2018 2020
       
New PV (MW) 78,260 86,909 101,361
Inventory Requirement (MW) 3,913 4,345 5,068
Inventory % of demand 5% 5% 5%
Total PV Module Shipments (MW) 82,173 91,254 106,429
Efficiency loss 3% 3% 3%
Total PV Cell Shipments (MW) 84,638 93,992 109,622
Thin Film Supply (MW) 4,696 4,606 4,460
Polysilicon Consumed (Tonne/MW) 5 5 5
Total Solar Poly Required (MT) 423,696 464,804 546,845
Poly demand from Semis (MT) 34,180 40,119 39,044
Total Poly Demand (MT) 457,876 504,923 585,889
Poly Supply (MT) 490,250 580,910 640,453
Over Supply (MT) 32,374 75,987 54,564
% Over Supply 7.1% 15.0% 9.3%
Source: The Information Network (www.theinformationnet.com)

“In addition to polysilicon capacity increases, the transition from slurry wire slicing to diamond wire is creating more silicon wafers by reducing kerf loss, adding to the oversupply noted Dr. Robert Castellano, President of The Information Network.

The Information Network is a consulting and market research company addressing the semiconductor, LCD, HDD, and solar industries.

To make continuous, strong and conductive carbon nanotube fibers, it’s best to start with long nanotubes, according to scientists at Rice University.

The Rice lab of chemist and chemical engineer Matteo Pasquali, which demonstrated its pioneering method to spin carbon nanotube into fibers in 2013, has advanced the art of making nanotube-based materials with two new papers in the American Chemical Society’s ACS Applied Materials and Interfaces.

The first paper characterized 19 batches of nanotubes produced by as many manufacturers to determine which nanotube characteristics yield the most conductive and strongest fibers for use in large-scale aerospace, consumer electronics and textile applications.

The researchers determined the nanotubes’ aspect ratio — length versus width — is a critical factor, as is the overall purity of the batch. They found the tubes’ diameters, number of walls and crystalline quality are not as important to the product properties.

Pasquali said that while the aspect ratio of nanotubes was known to have an influence on fiber properties, this is the first systematic work to establish the relationship across a broad range of nanotube samples. Researchers found that longer nanotubes could be processed as well as shorter ones, and that mechanical strength and electrical conductivity increased in lockstep.

The best fibers had an average tensile strength of 2.4 gigapascals (GPa) and electrical conductivity of 8.5 megasiemens per meter, about 15 percent of the conductivity of copper. Increasing nanotube length during synthesis will provide a path toward further property improvements, Pasquali said.

The second paper focused on purifying fibers produced by the floating catalyst method for use in films and aerogels. This process is fast, efficient and cost-effective on a medium scale and can yield the direct spinning of high-quality nanotube fibers; however, it leaves behind impurities, including metallic catalyst particles and bits of leftover carbon, allows less control of fiber structure and limits opportunities to scale up, Pasquali said.

“That’s where these two papers converge,” he said. “There are basically two ways to make nanotube fibers. In one, you make the nanotubes and then you spin them into fibers, which is what we’ve developed at Rice. In the other, developed at the University of Cambridge, you make nanotubes in a reactor and tune the reactor such that, at the end, you can pull the nanotubes out directly as fibers.

“It’s clear those direct-spun fibers include longer nanotubes, so there’s an interest in getting the tubes included in those fibers as a source of material for our spinning method,” Pasquali said. “This work is a first step toward that goal.”

The reactor process developed a decade ago by materials scientist Alan Windle at the University of Cambridge produces the requisite long nanotubes and fibers in one step, but the fibers must be purified, Pasquali said. Researchers at Rice and the National University of Singapore (NUS) have developed a simple oxidative method to clean the fibers and make them usable for a broader range of applications.

The labs purified fiber samples in an oven, first burning out carbon impurities in air at 500 degrees Celsius (932 degrees Fahrenheit) and then immersing them in hydrochloric acid to dissolve iron catalyst impurities.

Impurities in the resulting fibers were reduced to 5 percent of the material, which made them soluble in acids. The researchers then used the nanotube solution to make conductive, transparent thin films.

“There is great potential for these disparate techniques to be combined to produce superior fibers and the technology scaled up for industrial use,” said co-author Hai Minh Duong, an NUS assistant professor of mechanical engineering. “The floating catalyst method can produce various types of nanotubes with good morphology control fairly quickly. The nanotube filaments can be collected directly from their aerogel formed in the reactor. These nanotube filaments can then be purified and twisted into fibers using the wetting technique developed by the Pasquali group.”

Pasquali noted the collaboration between Rice and Singapore represents convergence of another kind. “This may well be the first time someone from the Cambridge fiber spinning line (Duong was a postdoctoral researcher in Windle’s lab) and the Rice fiber spinning line have converged,” he said. “We’re working together to try out materials made in the Cambridge process and adapting them to the Rice process.”

The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel, may go down as one of the most memorable editions for the sheer variety and depth of its talks, sessions, courses and events.

Among the most-anticipated talks are presentations by Intel and Globalfoundries, which will each detail their forthcoming competing FinFET transistor technology platforms in a session on Wednesday morning. FinFET transistors are a major driver of the continuing progress of the electronics industry, and these platforms are as important for their commercial potential as they are for their technical innovations.*

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations, along with other events.

“Those who attend IEDM 2017 will find much that is familiar, beginning with a technical program describing breakthroughs in areas ranging from mainstream CMOS technology to innovative nanoelectronics to medical devices. The Sunday Short Courses are also a perennial favorite because they are not only comprehensive but are also taught by accomplished world experts,” said Dr. Barbara De Salvo, Scientific Director at Leti. “But we have added some new features this year. One is a fourth Plenary session, on Wednesday morning, featuring Nobel winner Hiroshi Amano. Another is a revamped Tuesday evening panel. Not only will it focus on a topic of great interest to many people, it is designed to be more open and less formal.”

Other features of the IEDM 2017 include:

  • Focus Sessions on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current Status and Perspectives.
  • A vendor exhibition will be held, based on the success of last year’s event at the IEDM.
  • The IEEE Magnetics Society will again host a joint poster session on MRAM (magnetic RAM) in the exhibit area. New for this year, though, is that the Society will also hold its annual MRAM Global Innovation Forum on Thursday, Dec. 7 at the same hotel, enabling IEDM attendees to participate. (Refer to the IEEE Magnetics Society website.) The forum consists of invited talks by leading experts and a panel discussion.

Here are details of some of the events that will take place at this year’s IEDM:

90-Minute Tutorials – Saturday, Dec. 2
These tutorials on emerging technologies will be presented by leading technical experts in each area, with the goal of bridging the gap between textbook-level knowledge and cutting-edge current research.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec

Short Courses – Sunday, Dec. 3
The day-long Short Courses provide the opportunity to learn about important developments in key areas, and they enable attendees to network with the industry’s leading technologists.

Boosting Performance, Ensuring Reliability, Managing Variability in Sub-5nm CMOS, organized by Sandy Liao of Intel, will feature the following sections:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS,Cathyrn Christiansen, Globalfoundries
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights

Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang of TSMC, will feature the following sections:

  • Embedded Non Volatile Memory for Automotive Applications, Alfonso Maurelli, STMicroelectronics
  • 3D ReRAM: Crosspoint Memory Technologies, Nirmal Ramaswamy, Micron
  • Ferroelectric Memory in CMOS Processes, Thomas Mikolajick, Namlab
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive, Danny P. Shum, Globalfoundries
  • Embedded Memories for Energy-Efficient Computing, Jonathan Chang, TSMC
  • Abundant-Data Computing: The N3XT 1,000X, Subhasish Mitra, Stanford University

Plenary Presentations – Monday, Dec. 4

  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL
  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University. Dr. Amano received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting. His talk will be preceded by the Focus Session on silicon photonics.

Evening Panel Session – Tuesday evening, Dec. 5

  • Where will the Next Intel be Headquartered?  Moderator: Prof. Philip Wong, Stanford

Entrepreneurs Lunch
Jointly sponsored by IEDM and IEEE EDS Women in Engineering, this year’s Entrepreneurs Lunch will feature Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in Ohio. The moderator will be Prof. Leda Lunardi from North Carolina State University. Gras is an engineer by training and an entrepreneur by nature. After leaving her job as a NASA power systems engineer to work for on own startup company, she discovered a passion for building startup communities and helping technology-focused companies meet their goals. Named to the Forbes ’30 Under 30′ list in 2016, among many other recognitions and awards, Gras enjoys sharing her stories of founding a cleantech company with young entrepreneurs. She speaks on entrepreneurship, women in technology and clean energy at venues such as TEDx Budapest, the Pioneers Festival, and the IEEE WIE International Women’s Leadership Conference.