Category Archives: Process Materials

Epitaxy, or growing crystalline film layers that are templated by a crystalline substrate, is a mainstay of manufacturing transistors and semiconductors. If the material in one deposited layer is the same as the material in the next layer, it can be energetically favorable for strong bonds to form between the highly ordered, perfectly matched layers. In contrast, trying to layer dissimilar materials is a great challenge if the crystal lattices don’t match up easily. Then, weak van der Waals forces create attraction but don’t form strong bonds between unlike layers.

In a study led by the Department of Energy’s Oak Ridge National Laboratory, scientists synthesized a stack of atomically thin monolayers of two lattice-mismatched semiconductors. One, gallium selenide, is a “p-type” semiconductor, rich in charge carriers called “holes.” The other, molybdenum diselenide, is an “n-type” semiconductor, rich in electron charge carriers. Where the two semiconductor layers met, they formed an atomically sharp heterostructure called a p-n junction, which generated a photovoltaic response by separating electron-hole pairs that were generated by light. The achievement of creating this atomically thin solar cell, published in Science Advances, shows the promise of synthesizing mismatched layers to enable new families of functional two-dimensional (2D) materials.

The idea of stacking different materials on top of each other isn’t new by itself. In fact, it is the basis for most electronic devices in use today. But such stacking usually only works when the individual materials have crystal lattices that are very similar, i.e., they have a good “lattice match.” This is where this research breaks new ground by growing high-quality layers of very different 2D materials, broadening the number of materials that can be combined and thus creating a wider range of potential atomically thin electronic devices.

“Because the two layers had such a large lattice mismatch between them, it’s very unexpected that they would grow on each other in an orderly way,” said ORNL’s Xufan Li, lead author of the study. “But it worked.”

The group was the first to show that monolayers of two different types of metal chalcogenides–binary compounds of sulfur, selenium or tellurium with a more electropositive element or radical–having such different lattice constants can be grown together to form a perfectly aligned stacking bilayer. “It’s a new, potential building block for energy-efficient optoelectronics,” Li said.

Upon characterizing their new bilayer building block, the researchers found that the two mismatched layers had self-assembled into a repeating long-range atomic order that could be directly visualized by the Moiré patterns they showed in the electron microscope. “We were surprised that these patterns aligned perfectly,” Li said.

Researchers in ORNL’s Functional Hybrid Nanomaterials group, led by David Geohegan, conducted the study with partners at Vanderbilt University, the University of Utah and Beijing Computational Science Research Center.

“These new 2D mismatched layered heterostructures open the door to novel building blocks for optoelectronic applications,” said senior author Kai Xiao of ORNL. “They can allow us to study new physics properties which cannot be discovered with other 2D heterostructures with matched lattices. They offer potential for a wide range of physical phenomena ranging from interfacial magnetism, superconductivity and Hofstadter’s butterfly effect.”

Li first grew a monolayer of molybdenum diselenide, and then grew a layer of gallium selenide on top. This technique, called “van der Waals epitaxy,” is named for the weak attractive forces that hold dissimilar layers together. “With van der Waals epitaxy, despite big lattice mismatches, you can still grow another layer on the first,” Li said. Using scanning transmission electron microscopy, the team characterized the atomic structure of the materials and revealed the formation of Moiré patterns.

The scientists plan to conduct future studies to explore how the material aligns during the growth process and how material composition influences properties beyond the photovoltaic response. The research advances efforts to incorporate 2D materials into devices.

For many years, layering different compounds with similar lattice cell sizes has been widely studied. Different elements have been incorporated into the compounds to produce a wide range of physical properties related to superconductivity, magnetism and thermoelectrics. But layering 2D compounds having dissimilar lattice cell sizes is virtually unexplored territory.

“We’ve opened the door to exploring all types of mismatched heterostructures,” Li said.

The title of the paper is “Two-dimensional GaSe/MoSe2 misfit bilayer heterojunctions by van der Waals epitaxy.”

Harnessing the power of the sun and creating light-harvesting or light-sensing devices requires a material that both absorbs light efficiently and converts the energy to highly mobile electrical current. Finding the ideal mix of properties in a single material is a challenge, so scientists have been experimenting with ways to combine different materials to create “hybrids” with enhanced features.

In two just-published papers, scientists from the U.S. Department of Energy’s Brookhaven National Laboratory, Stony Brook University, and the University of Nebraska describe one such approach that combines the excellent light-harvesting properties of quantum dots with the tunable electrical conductivity of a layered tin disulfide semiconductor. The hybrid material exhibited enhanced light-harvesting properties through the absorption of light by the quantum dots and their energy transfer to tin disulfide, both in laboratory tests and when incorporated into electronic devices. The research paves the way for using these materials in optoelectronic applications such as energy-harvesting photovoltaics, light sensors, and light emitting diodes (LEDs).

According to Mircea Cotlet, the physical chemist who led this work at Brookhaven Lab’s Center for Functional Nanomaterials (CFN), a DOE Office of Science User Facility, “Two-dimensional metal dichalcogenides like tin disulfide have some promising properties for solar energy conversion and photodetector applications, including a high surface-to-volume aspect ratio. But no semiconducting material has it all. These materials are very thin and they are poor light absorbers. So we were trying to mix them with other nanomaterials like light-absorbing quantum dots to improve their performance through energy transfer.”

One paper, just published in the journal ACS Nano, describes a fundamental study of the hybrid quantum dot/tin disulfide material by itself. The work analyzes how light excites the quantum dots (made of a cadmium selenide core surrounded by a zinc sulfide shell), which then transfer the absorbed energy to layers of nearby tin disulfide.

“We have come up with an interesting approach to discriminate energy transfer from charge transfer, two common types of interactions promoted by light in such hybrids,” said Prahlad Routh, a graduate student from Stony Brook University working with Cotlet and co-first author of the ACS Nano paper. “We do this using single nanocrystal spectroscopy to look at how individual quantum dots blink when interacting with sheet-like tin disulfide. This straightforward method can assess whether components in such semiconducting hybrids interact either by energy or by charge transfer.”

The researchers found that the rate for non-radiative energy transfer from individual quantum dots to tin disulfide increases with an increasing number of tin disulfide layers. But performance in laboratory tests isn’t enough to prove the merits of potential new materials. So the scientists incorporated the hybrid material into an electronic device, a photo-field-effect-transistor, a type of photon detector commonly used for light sensing applications.

As described in a paper published online March 24 in Applied Physics Letters, the hybrid material dramatically enhanced the performance of the photo-field-effect transistors-resulting in a photocurrent response (conversion of light to electric current) that was 500 percent better than transistors made with the tin disulfide material alone.

“This kind of energy transfer is a key process that enables photosynthesis in nature,” said Chang-Yong Nam, a materials scientist at Center for Functional Nanomaterials and co-corresponding author of the APL paper. “Researchers have been trying to emulate this principle in light-harvesting electrical devices, but it has been difficult particularly for new material systems such as the tin disulfide we studied. Our device demonstrates the performance benefits realized by using both energy transfer processes and new low-dimensional materials.”

Cotlet concludes, “The idea of ‘doping’ two-dimensional layered materials with quantum dots to enhance their light absorbing properties shows promise for designing better solar cells and photodetectors.”

The 2016 International Group IV Photonics Conference, sponsored by the IEEE Photonics Society, has announced the Call for Papers seeking original research on the Novel Materials & Nanophotonics; Photonic Devices; and Silicon Photonics Applications & Systems. The conference is scheduled for 24 – 26 August, 2016, at the Grand Kempinski Hotel Shanghai in Shanghai, China.

The Group IV Photonics Conference (GFP 2016), now in its 13th year, delivers insights on current and future innovations in Group IV element-based photonic materials and devices, including silicon photonics, as well as other integration and fabrication technologies. Scheduled as a single-track conference, GFP 2016 facilitates personal interaction between colleagues, including oral and poster sessions of contributed and invited papers, as well as a plenary session with overviews of important Group IV element photonics topics.

Paper submission is now open, and the final deadline is 24 April, 2016. Authors will be notified in late July of their paper status. The complete Call for Papers can be found at http://www.gfp-ieee.org/call-for-papers.

Papers are invited in the following areas:

• Novel Materials & Nanophotonics – covering advanced materials, structures, phenomena, and devices still in the investigative stages. Novel materials and material combinations that enable new applications and new nanophotonic structures will be presented, including graphene, complex oxides, amorphous materials, photonic crystals, subwavelength structures, gratings, and plasmonics.

• Silicon Photonic Applications & Systems – includes demonstrations of complete system architectures and integration schemes that demonstrate the future application potential of silicon photonics, including chip-level subsystem integration, as well as integration with other electronics technologies such as microfluidics.

• Photonic Devices – covering new developments in device design, fabrication and testing to address a wide range of photonic functions based on Group IV integration, including on-chip light sources, high-speed modulation, photo detection, optical coupling WDM, filtering and routing. Other topics sought include biomedical and environmental sensing devices, devices to facilitate wafer-scale testing and cost-effective packaging technologies.

For registration and other information about GFP 2016, visit http://www.gfp-ieee.org/

Finding a short term solution to the neon gas shortage problem will be challenging.

BY HITOMI FUKUDA, Gigaphoton, Inc., Oyama, Japan

When many people think of neon, they think of brightly lighted signs used in restaurants and other retail environments. The element neon (Ne) gives a distinct reddish-orange glow when used in either low-voltage neon glow lamps or in high-voltage discharge tubes or neon advertising signs. The red emission line from neon is also responsible for the well known red light of helium–neon lasers. Neon is commercially extracted by the fractional distillation of liquid air. It is considerably more expensive than helium, since air is its only source.

What those outside the chip industry likely don’t know is that neon has been employed for semiconductor manufacturing for more than a decade, since deep ultraviolet (DUV) lithography came into widespread use starting with 248nm exposure systems. Why is neon important in lithography? Excimer lasers use gases like krypton fluoride (KrF) and argon fluoride (ArF) to generate light, and those gases are regularly changed out during use. However, a charge of excimer laser gas is actually about 98 percent neon, making this carrier gas essential to the laser’s operation. Three main steps are involved in producing gas suitable for excimer laser use: (1) bulk neon production, (2) purification, and (3) final mix.

Today, the semiconductor industry is experiencing severe neon shortages, leading to price increases that are impacting end-users’ bottom line. As a result, fab owners are rushing to secure enough neon to keep their facilities in operation, including buying the critical gas on the cash market and then having it purified and mixed to allow them to put it into use as quickly as possible.

Neon is a byproduct of steel production, but because it is a rare component of the waste gases, it must be recovered at very large steel plants. The former Soviet Union manufactured all of its oxygen plants for steel mills with neon, krypton and xenon capabilities and formerly worked on high-powered lasers as weapons, giving rise to significant neon capacity. Ukraine and Russia still operate the old-style massive manufacturing plants that have long since disappeared from Western countries, and have thus historically enabled the gas to be in over-supply.

From 1990 to 2012, many of these eastern European plants simply sent the crude neon into the atmosphere as no one would buy it. This over-supply began to tighten in 2014, as many old oxygen plants in Eastern Europe were either replaced by newer units without neon capability or shutdown altogether, especially with the contraction of the steel industry.

Why the shortage?

The neon crisis was triggered in part by conflict in the Ukraine, resulting in slowed production and escalating costs on the part of gas suppliers. Because neon is used for the majority of lithography light sources, the shortage caused many chip factories to face potential slowdown or even shutdown. In addition to gas prices increasing as much as 10 times over previous rates, chipmakers faced the prospect of a 15-percent or greater reduction in available supply of neon gas.

In China, old oxygen plants are being privatized or de-activated, or are being replaced by newer plants that lack the additional rare gas recovery investment. Even though there is a strong market for rare gases, the new plants are being put in without the rare gas capability due to a minimal ROI impact. Thus, while China has increased its market share in neon gas, the country’s purification facilities are few and far between, so the country currently lacks production capacity for high-grade purification of neon gas. Regional specialty gas suppliers have also reported diminished supplies, all of which has had severe implications for the future of lithography and global chip manufacturing.

Between 2012 and 2014, the net effect of the neon supply shortage was around 125 million liters of lost annual production. In 2015, neon production, at 400 million liters, was falling short of demand by roughly 75 million liters.

A deeper look at the problem

Semiconductor-related lithography accounts for about 70 percent of worldwide neon demand. As mentioned earlier, an excimer laser uses a multi-gas mixture. The term “excimer” refers to the rare gas / halide molecule. Each fill is dedicated to the generation of a single wavelength. Four wavelengths can be generated from fluorine laser gas mixtures: 157 nm (F2), 193 nm (ArF), 248 nm (KrF) and 351 nm (XeF).

According to some reports, the price of neon gas skyrocketed in 2014, from roughly $1,000 for a 6,000-liter bottle of the gas, to approximately $6,000 for the same quantity as of late 2015. This is evident as seen in FIGURE 1, where the different colors represent the various global chipmakers. Neon gas, minerals, and the industry workhorse—silicon — are among the critical materials vital to semiconductor industry operations. The industry has had to deal with shortages in helium and rare earths in recent years, but was able to find at least temporary solutions.

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Neon gas, on the other hand, appears to be a shortage for which finding a solution in the short term will be far more challenging. This problem is expected to continue for several years until a) sufficient new capacity comes on line, b) recycling can be implemented, or c) reprogramming of lasers can be accomplished, in order to allow for more efficient usage. In all likelihood, it will be a combination of all three of these factors that will alleviate the industry’s neon supply challenges, although getting prices back down to a more affordable level is likely to take longer.

Neon conservation

In the meantime, the industry is looking at ways to conserve neon gas to help stretch its usage until such as time as the larger issues begin to be addressed in a more long-term fashion. Important developments in neon conservation include recent excimer laser gas usage optimization efforts that have been put in place by lithographic tool and laser equipment vendors to help end-customers reduce consumption. Optimization can be achieved via software updates for current systems and may result in up to 40 percent more efficient neon usage. In addition, recovery and recycling of neon may be relatively straight-forward with few technical challenges, so several suppliers are proposing recycling and recovery plans.

With that said, the potential impact of these conservation efforts should be carefully considered, as some have the potential to put on hold, or even cancel, capital investment plans to produce more neon. This could mean the neon shortage would become exacerbated or prolonged beyond its current, already critical level.

To combat this crisis, Gigaphoton developed its unique Neon Gas Rescue Program, which expands on its previously announced program offering its eTGM technology for all new and existing GT series ArF immersion lasers.

The new program provides a more comprehensive package that includes the following:

1. A program for rapid qualification of new gas suppliers requested by customers. Previously, testing and qualification of a new gas supplier required anywhere from six to 12 months, but the new program will enable customers to begin using new gas suppliers much more quickly – cutting the qualification time down to as little as one month.

2. A limited, free-of-charge offer of the company’s eTGM technology will also be extended to the G41K series KrF lasers and GT40A series ArF lasers. This extended offer will commence in November 2015. By introducing eTGM, customers can reduce the laser’s neon usage by 25 percent on KrF and ArF lasers, and up to 50 percent on ArF immersion lasers.

3. The accelerated introduction of Gigaphoton’s newest gas recycling technology, hTGM, which can be applied to all types of lasers. hTGM is expected to begin roll-out later this year. By implementing the hTGM technology, customers will be able to recycle up to 50 percent of their gas consumption.

Conclusion

While the semiconductor industry is facing a unique challenge with the current neon gas supply shortage, it has history on its side in terms of innovative solutions. The lithography sector, in particular, has repeatedly found ways to extend and revitalize technology applications.

HITOMI FUKUDA is from the marketing team at Gigaphoton, 400 Yokokurashinden, Oyama-shi, Tochigi-ken 323-8558, Japan; email: [email protected]; www.gigaphoton.com.

A look into how the silicide process has evolved over the years, trying to cope with the progress in scaling technology and why it could no longer be of service to finFET devices.

BY ARABINDA DAS, TechInsights. Ottawa, Canada

Samsung and TSMC introduced their finFET devices in 2015 and joined Intel as the semiconductor industry’s three major manufacturers possessing the most advanced technology. Intel’s 14nm finFET 5Y70 processor was commercialized in 2014 and within six months Samsung mass produced their 14nm finFET Exynos 7 7420 SoC. Later that same year, TSMC started supplying their 16nm finFET based devices to Apple. Today Samsung and TSMC both supply their finFET based processors to Apple, which are being used for the iPhone6’s A9 processor.

Since the release of the iPhone6 several blogs and articles have been written about the cost of fabrication, the perfor- mance of tri-gates, the type of work-function materials used by the manufacturers, the dominant supplier for Apple and speculation about the future of finFET devices. TechInsights has performed detailed structural analyses of these three devices and has also tried to understand some of these questions. While comparing these structural reports on finFET devices, one small detail stands out is that a major pillar of semiconductor processing is missing. The silicide process is not being used. Intel stopped using the silicide process in their 22nm finFET “Ivy Bridge” Processor. Samsung and TSMC at 20nm used the existing planar structure and employed NiSi on top of their source and drain regions. But as soon as these two device makers adopted finFET structure in 14 and 16nm nodes they abandoned the thirty year old silicide process. It is interesting to look into how the silicide process has evolved over the years, trying to cope with the progress in scaling technology and finally also why it could not anymore be of service to finFET devices.

The silicide process has been an integral part of semicon- ductor manufacturing since the early 1980s. The first patents were filed by Motorola, Fairchild and IBM. This process is used as an interface between semiconductor material and metals to reduce the contact resistance between tungsten contacts and the source-drain regions or the gate electrode. This parasitic resistance should be minimized to enable higher drive currents in transistors. Silicides have metal-like properties and are made by reacting Si to refractory or near-noble metals. A large number of metals in the periodic table can form silicides. The most common silicides in the semiconductor industry are titanium silicide, tungsten silicide, cobalt silicide, nickel silicide and nickel-platinum silicide. Platinium was used to stabilize the NiSi phase at a specific temperature.

These compositions can exist in various phases and have unique phase diagrams. One particular integration process of silicides, known as self-aligned silicides (also termed ‘salicide’), has played a significant role in bipolar devices, passives and in CMOS devices. In this scheme, no additional mask is needed; the silicide is grown on exposed silicon or polysilicon surfaces and not at all on neighboring dielectric surfaces.

The main steps of growing the silicide are depositing a refractory metal or a near-noble metal on the exposed Si and then annealing in a non-oxidizing atmosphere at a suitable temperature to react the metal with Si. The duration of the thermal cycle should be long enough to convert the majority of the metal to a silicide composition. Several stages of annealing may be completed to stabilize the phase. Thereafter the unreacted metal is removed by wet-etching. For a detailed understanding of silicide process please refer to the book “Silicide technology for integrated circuits” by L.J. Chen or to the lecture notes from Professor Sarsawat from Stanford University [1].

The earliest image of the silicide process in TechInsights’ database is from Intel’s 166 Mhz Pentium microprocessor A80502166 based on a 0.35 μm CMOS process. The die markings of this device suggest that it was made in 1992-93. FIGURE 1 shows a TEM cross-section of a gate employing titanium silicide. The transistors in this device have 0.40 μm thick titanium silicide on top of the gates and silicided diffusions formed using a salicide process.

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The industry realized very quickly that TiSi2 was not easily scalable. It has two phases C49-TiSi2 and C54-TiSi2. The first is formed at temperatures between 350 to 700o C and has a resistivity of 60-80 μΩcm; while the other is formed around 750 ̊ C and has a resistivity lower than C49-TiSi2 (~20 μΩcm). As devices scaled down it became necessary to reduce the thermal budget which had the consequence of forming C49-TiSi2 instead of C54-TiSi2, which resulted in higher contact resistance. Since this was counter-productive, it was time to switch to a new silicide. Intel’s Pentium III “Tualatin” used Co-silicide in a 0.13 μm CMOS process (FIGURE 2).

The next major milestone for silicide processes came at the 90nm node when Intel introduced the concept of raised source and drain for the PMOS transistor in their “Prescott” processor. The raised source and drain regions were formed by etching out portions of the Si substrate at the source and drain regions and then depositing epitaxial layers of Si1-xGex, where x is between 0 and 1. The etching out used both dry and wet chemistry. This concept was an innovative use of the growth rate variability on the bottom surface and on the side walls of the cavity due to the different crystal plane orientations of the silicon substrate. SiGe has a lattice constant that is slightly larger than that of silicon so this epitaxial film induces a large uniaxial compressive strain in the PMOS channel region, resulting in significant hole mobility improvement. But SiGe surfaces were not very suitable for Co-Silicide. Most silicides have much lower free energy than germanides so when the silicide is formed on a Si-Ge alloy the Ge is expelled. This expelled Ge undergoes agglom- eration and increases the contact resistance thus negating the effect of the enhanced mobility. The use of Ni instead of Co was especially beneficial for salici- dation of both Si and SiGe source drain regions because Ni provides a more uniform contact resistance. Moreover, NiSi has the same resistivity as CoSi2 but has smaller Si consumption. FIGURE 3 shows Intel’s 90nm “Prescott” transistor along with NiSi on top of SiGe regions.

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NiSi was the mainstream process for two process nodes (90nm and 65nm) and was employed on top of polysilicon gate as well as on top of the source-drain regions. Around the year 2000, there were even discussions about a fully silicided (FuSi) gate. Then in 2008 Intel introduced the high-k dielectric and metal gate-last (HKMG) process at the 45nm node in their “Penryn” processor. This device did not require any more silicide on top of the gate but only at the source-drain regions. FIGURE 4 shows a TEM cross-section of Intel’s 45nm “Penryn” processor. In these devices, silicide is formed only on top of source and drain regions. The silicide is self-aligned to the sidewall spacer. The surface of the SiGe source-drain regions that is in contact with the silicide has enriched Si concentration to facilitate the silicide process. The nickel silicide depth from the silicon surface is about 65nm.

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Finally, in 2012 Intel commercialized the first finFET device at 22nm in their “Ivy Bridge” (Intel core i5-3550) processor, in this device the silicide process was abandoned. To understand why the silicide process was not employed, it is important to grasp the differences between a tri-gate device and a planar device. Tri-gate brought in several advantages. For example, the effective gate width is proportional to the fin height and can be increased without increasing the device footprint. Additionally, because the gate wraps around the fin, there is better control of the channel. Another benefit is that the walls of the fin offer a different crystallographic plane than the top of the fin. Here, in this integration schemethe PMOS transistors benefit from higher mobility along the fin sidewalls.

The tri-gate integration scheme also brought in several process challenges. Epitaxial SiGe for PMOS and epitaxial Si islands for NMOS must be grown in a recess in a narrow Si fin rather than in the Si substrate. One constraint is due to double patterning, which requires that all the fins be of the same width and pitch; so if a larger gate width is required then multiple fins have to be employed. That means that the gate width is dependent on integer units of fins. This concept of integer units of fins is well illustrated in FIGURE 5, where the I/O transistor of TSMC finFET is shown having several fins connected in parallel.

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Multiple fins connected in parallel imply that the contact to the source-drain regions must have exactly the same contact resistance on multiple fins and this was indeed difficult to guarantee with the silicide process due to the vagaries of the diffusion process. In the Ni silicide process, it is believed that Ni atoms are the dominant diffusing species in Ni monosilicide formation; this property can lead to excessive silicidation on narrow lines. Ni-silicide is sensitive to temperature and often at low temperature a NiSi2 is formed. This phase is usually seen on strained PMOS structures and can create an increase of contact resistance. Non uniform distribution of silicide process was the biggest show-stopper for this old process.

In addition to the silicide process there was also the problem of dopants in the source and drain regions. The thermal process causes undesirable dopant diffusion and leads to the loss of the junction abruptness. Also, thermal processes create thermal budget issues in the integration’s process flow. There could be also other reasons for avoiding the silicide process in finFET devices, like leakage and stress because it is well known that the silicide process has an impact on device properties. Luckily, the technology of in-situ doping was already mature and used for DRAM devices as these volatile memories do not require a silicide process due to leakage concerns. Intel in its 22 nm process flow, most likely used in-situ doping of epitaxial regions along with trench contacts to eliminate the silicide process. This does not mean that other doping techniques like implants and thin film doping were not employed; they were probably used during different parts of the process flow. Intel did mention at IEDM 2014 that thin film doping method was used for 14nm finFET devices.

The introduction of trench contact, which ensure equal and low contact resistance to multiple fins was the ultimate reason not to use the silicide process in FinFETs. The integration flow is described in FIGURE 6. First, multiple parallel fins are formed. Each fin is separated from its neighbors by the STI-oxide. On these fins a sacrificial poly-silicon gate structure is made that runs perpendicular to the fins. On portions of the fin not covered by the gate, cavities are etched by using a line mask or a self-aligned process. Recesses in the fins are made by selectively etching the silicon. In-situ doped epitaxial layers are then grown to form source-drain regions. These epitaxial layers extend beyond the fin width and may even merge to form a continuous layer. The epitaxial layers do not extend above the surface of the fin. Subsequently, the poly-silicon gate is removed and the high-k-metal-gate (HKMG) formed in its place. A dielectric layer is deposited on top of the gates and the fins. The dielectric layer is patterned to form trenches running parallel to the gate. The integration scheme further includes etching a trench in the epitaxial layers and then filling the trench with tungsten to form trench contacts.

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FIGURE 7 shows the cross-sectional schematic diagram of how the trench contacts are embedded or well anchored in the epitaxial layers.

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Cross-sectional images parallel to the fins of the three 1x node finFETs from Intel, Samsung and TSMC are collected in FIGURES 8a, 8b and 8c, respectively. The cross-section is made along one of the fins. The important point to note is that the trench contact at the surface of the source and drain regions is surrounded on three sides. It is more pronounced in the case of Samsung’s device. The tungsten metal lines that run parallel to the gate, form the contacts for source-drain regions and are well anchored in the epitaxial layers. This increases the surface area of the contact and reduces the contact resistance.

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FIGURE 9 shows the cross-section of the 16nm finFETs from TSMC in the direction perpendicular to the fins. In this direction the epitaxial regions could be designed to merge or extend beyond the fin width and thus increase the contact region with the metal contact. This increased contact region reduces the contact resistance.

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The silicide process has a long history in the semicon- ductor industry; it has evolved through many phases from tungsten silicide to titanium silicide to cobalt-silicide to nickel silicide. But it could not be used for finFET devices. As for these devices, multiple fins may be used to form a single transistor, which implies that the contacts to all these fins have the exact same contact resistance. This is difficult to control in a process that is purely based on diffusion like the silicide process. So after 30 or more years of service it is time that the silicide process takes retirement and leaves the future to trench contacts and in-situ doping; however, there is always a possibility its use may be prolonged especially if the silicidation can be localized only inside the trench contact and not over the entire surface of the source-drain regions. Trench contacts will most likely be used in the next 10nm node but sub 10nm node, if new concepts like nanowire or new materials are introduced, the semiconductor industry is likely to innovate some other designs.

ARABINDA DAS is a Senior Process Analyst in the Technical Services division of TechInsights, Ottawa, Canada, [email protected]

Light and electrons interact in a complex dance within fiber optic devices. A new study by University of Illinois engineers found that in the transistor laser, a device for next-generation high-speed computing, the light and electrons spur one another on to faster switching speeds than any devices available.

Milton Feng, the Nick Holonyak Jr. Emeritus Chair in electrical and computer engineering, found the speed-stimulating effects with graduate students Junyi Qiu and Curtis Wang and Holonyak, the Bardeen Emeritus Chair in electrical and computer engineering and physics. The team published its results in the Journal of Applied Physics.

As big data become bigger and cloud computing becomes more commonplace, the infrastructure for transferring the ever-increasing amounts of data needs to speed up, Feng said. Traditional technologies used for fiber optic cables and high-speed data transmission, such as diode lasers, are reaching the upper end of their switching speeds, Feng said.

“You can compute all you want in a data center. However, you need to take that data in and out of the system for the user to use,” Feng said. “You need to transfer the information for it to be useful, and that goes through these fiber optic interconnects. But there is a fundamental switching limitation of the diode laser used. This technology, the transistor laser, is the next-generation technology, and could be a hundred times faster.”

Diode lasers have two ports: an electrical input and a light output. By contrast, the transistor laser has three ports: an electrical input, and both electrical and light outputs.

The three-port design allows the researchers to harness the intricate physics between electrons and light. For example, the fastest way for current to switch in a semiconductor material is for the electrons to jump between bands in the material in a process called tunneling. Light photons help shuttle the electrons across, a process called photon-assisted tunneling, making the device much faster.

In the latest study, Feng’s group found that not only does photon-assisted tunneling occur in the transistor laser, but that it in turn stimulates the photon absorption process within the laser cavity, making the optical switching in the device even faster and allowing for ultra-high-speed signal modulation.

“The collector can absorb the photon from the laser for very quick tunneling, so that becomes a direct-voltage-modulation scheme, much faster than using current modulation,” Feng said. “We also proved that the stimulated photon-assisted tunneling process is much faster than regular photon-assisted tunneling. Previous engineers could not find this because they did not have the transistor laser. With just a diode laser, you cannot discover this.

“This is not only proving the scientific point, but it’s very useful for high-speed device modulation. We can directly modulate the laser into the femtosecond range. That allows a tremendous amount of energy-efficient data transfer,” Feng said.

The researchers plan to continue to develop the transistor laser and explore its unique physics while also forming industry partnerships to commercialize the technology for energy-efficient big data transfer.

A group of researchers from the UK, including academics from Cardiff University, has demonstrated the first practical laser that has been grown directly on a silicon substrate.

It is believed the breakthrough could lead to ultra-fast communication between computer chips and electronic systems and therefore transform a wide variety of sectors, from communications and healthcare to energy generation.

The EPSRC-funded UK group, led by Cardiff University and including researchers from UCL and the University of Sheffield, have presented their findings in the journal Nature Photonics.

Silicon is the most widely used material for the fabrication of electronic devices and is used to fabricate semiconductors, which are embedded into nearly every device and piece of technology that we use in our everyday lives, from smartphones and computers to satellite communications and GPS.

Electronic devices have continued to get quicker, more efficient and more complex, and have therefore placed an added demand on the underlining technology.

Researchers have found it increasingly difficult to meet these demands using conventional electrical interconnects between computer chips and systems, and have therefore turned to light as a potential ultra-fast connector.

Whilst it has been difficult to combine a semiconductor laser – the ideal source of light – with silicon, the UK group have now overcome these difficulties and successfully integrated a laser directly grown onto a silicon substrate for the very first time.

Professor Huiyun Liu, who led the growth activity, explained that the 1300nm wavelength laser has been shown to operate at temperatures of up to 120°C and for up to 100,000 hours.

Professor Peter Smowton, from Cardiff University’s School of Physics and Astronomy, said: “Realising electrically-pumped lasers based on Si substrates is a fundamental step towards silicon photonics.

“The precise outcomes of such a step are impossible to predict in their entirety, but it will clearly transform computing and the digital economy, revolutionise healthcare through patient monitoring, and provide a step-change in energy efficiency.

“Our breakthrough is perfectly timed as it forms the basis of one of the major strands of activity in Cardiff University’s Institute for Compound Semiconductors and the University’s joint venture with compound semiconductor specialists IQE.”

Professor Alwyn Seeds, Head of the Photonics Group at University College London, said: “The techniques that we have developed permit us to realise the Holy Grail of silicon photonics – an efficient and reliable electrically driven semiconductor laser directly integrated on a silicon substrate. Our future work will be aimed at integrating these lasers with waveguides and drive electronics leading to a comprehensive technology for the integration of photonics with silicon electronics.”

For most of human history, the discovery of new materials has been a crapshoot. But now, UConn researchers have systematized the search with machine learning that can scan millions of theoretical compounds for qualities that would make better solar cells, fibers, and computer chips. The search for new materials may never be the same.

No one knows why an early metallurgist decided to smelt a hunk of tin into some copper, but the resulting bronze alloy was harder and more durable than any material previously known. Most materials experimentation over the ensuing 7,000 years has been similarly random, guided largely by philosophy and chemical intuition.

But in a world that contains at least 95 stable elements – the basic building blocks of matter – the number of possible combinations is enormous, and experimentation is an awfully inefficient way to find what you’re looking for.

Enter UConn materials scientist Ramamurthy ‘Rampi’ Ramprasad. Instead of randomly mixing chemicals to see what they do, Ramprasad designs them rationally, using machine learning to figure out which atomic configurations make a polymer a good electrical conductor or insulator.

This is a schematic diagram of machine learning for materials discovery. Credit: Chiho Kim, Ramprasad Lab, UConn

This is a schematic diagram of machine learning for materials discovery. Credit:
Chiho Kim, Ramprasad Lab, UConn

A polymer is a large molecule made of many repeating building blocks. Polymers are very common in both living and man-made materials. Probably the most familiar example is plastics, and the wide variation in plastics – which can be hard, soft, stretchy, brittle, spongy, clear, opaque or translucent – gives an inkling of how diverse polymers in general can be.

Polymers can also have diverse electronic properties. For example, they can be very good insulators – preventing electrons, and thus electric current, from traveling through them – or good conductors, allowing electricity to pass through them freely. And what controls all these properties is mainly how the atoms in the polymer connect to each other. But until recently, no one had systematically related properties to atomic configurations.

So Ramprasad and his colleagues decided to do just that. First, they would analyze known polymers, using laborious but accurate quantum mechanics-based calculations to figure out which arrangements of atoms confer which properties, and quantify those atomic-level relationships via a string of numbers that fingerprint each polymer. Once they had those, they could have a computer search through any number of theoretical polymers to figure out which ones might have which properties. Then anyone looking for a polymer with a certain property could quickly scan the list and decide which theoretical polymers might be worth trying.

Many polymers are made of building blocks containing just a few atoms. For instance, polyurea, a common plastic, has as the basic structure a repeating sequence of nitrogen (N), hydrogen (H) and oxygen (O): NH-O-NH-O. Most polymers look like that, made of carbon (C), H, N and O, with a few other elements thrown in occasionally.

For their project, Ramprasad’s group looked at polymers made of just seven building blocks: CH2, C6H4, CO, O, NH, CS, and C4H2S (the S is sulfur). These are found in common plastics such as polyethylene, polyesters, and polyureas. An enormous variety of polymers could theoretically be constructed using just these building blocks; Ramprasad’s group decided at first to analyze just 283, each composed of a repeated four-block unit.

They started from basic quantum mechanics, and calculated the three-dimensional atomic and electronic structures of each of those 283 four-block polymers. This is not trivial: calculating the position of every electron and atom in a molecule with more than two atoms takes a powerful computer a significant chunk of time, which is why they did it for only 283 molecules.

Once they had the three-dimensional structures, they could calculate what they really wanted to know: each polymer’s properties. They calculated the band gap, which is the amount of energy it takes for an electron in the polymer to break free of its home atom and travel around the material, and the dielectric constant, which is a measure of the effect an electric field can have on the polymer. These properties translate to how much electric energy each polymer can store in itself. The researchers used established techniques that have long been known. They take a prohibitive amount of computing time, which is why it’s so hard to evaluate materials this way.

Ramprasad’s group then went one step further. They wanted a shorthand system that a computer could use to look at the building blocks of a polymer and how they connect to each other, and make educated guesses about its properties.

Computers deal with numbers, so first they had to define each polymer as a string of numbers, a sort of numerical fingerprint. Since there are seven possible building blocks, there are seven possible numbers, each indicating how many of each block type are contained in that polymer. But a simple number string like that doesn’t give enough information about the polymer’s structure, so they added a second string of numbers that tell how many pairs there are of each combination of building blocks, such as NH-O or C6H4-CS. Still not quite enough information, so they added a third string that described how many triples, like NH-O-CH2, there were. They arranged these strings as a three-dimensional matrix, which is a convenient way to describe such strings of numbers in a computer.

Then they let the computer go to work. Using the library of 283 polymers they had laboriously calculated using quantum mechanics, the machine compared each polymer’s numerical fingerprint to its band gap and dielectric constant, and gradually ‘learned’ which building block combinations were associated with which properties. It could even map those properties onto a two-dimensional matrix of the polymer building blocks.

Once the machine learned which atomic building block combinations gave which properties, it no longer needed the quantum mechanics calculations of atomic structure. It could accurately evaluate the band gap and dielectric constant for any polymer made of any combination of those seven building blocks, using just the numerical fingerprint of its structure.

Many of the predictions of quantum mechanics and the machine learning scheme have been validated by Ramprasad’s UConn collaborators, chemistry professor Greg Sotzing and electrical engineering professor Yang Cao. Sotzing actually made several of the novel polymers, and Cao tested their properties; they came out just as Ramprasad’s computations had predicted.

“What’s most surprising is the level of accuracy with which we can make predictions of the dielectric constant and band gap of a material using machine learning. These properties are generally computed using quantum mechanical methods such as density functional theory, which are six to eight orders of magnitude slower,” says Ramprasad. The group published a paper on their polymer work in Scientific Reports on Feb. 15; and another paper that utilizes machine learning in a different manner, namely, to discover laws that govern dielectric breakdown of insulators, will be published in a forthcoming issue of Chemistry of Materials.

But even if you don’t have access to those academic journals, you can see the predicted properties of every polymer Ramprasad’s group has evaluated in their online data vault, Khazana (khazana.uconn.edu), which also provides their machine learning apps to predict polymer properties on the fly. They are also uploading data and the machine learning tools from their Chemistry of Materials work, and from an additional recent article published in Scientific Reports on Jan. 19 on predicting the band gap of perovskites, inorganic compounds used in solar cells, lasers, and light-emitting diodes.

As a theoretical materials scientist, what Ramprasad wants to know is why materials behave the way they do. What about a polymer makes its dielectric constant just so? Or what makes an insulator withstand enormous electric fields without breaking down? But he also wants this understanding to be put to work to design new useful materials rationally. So he makes the results of his calculations freely available in the hope that someone else might look through them, see one, and go, “Wow. I’m looking for a material with exactly those properties!” and then make it. If it works as predicted, they’re both happy.

His work is aligned with a larger U.S. White House initiative called the Materials Genome Initiative. Much of Ramprasad’s work described here was funded by grants from the Office of Naval Research, as well as from the U.S. Department of Energy.

Stacking layers of nanometer-thin semiconducting materials at different angles is a new approach to designing the next generation of energy-efficient transistors and solar cells. The atoms in each layer are arranged in hexagonal arrays. When two layers are stacked and rotated, atoms from one layer overlap with those in the other layer and can form an infinite number of overlapping patterns, like the Moiré patterns that result when two screens are overlaid and one is rotated on top of the other. Theoretical calculations predict excellent electronic and optical properties for some stacking patterns, but practically, how can these patterns be made and characterized?

Recently a team led by researchers from the Department of Energy’s Oak Ridge National Laboratory used the vibrations between two layers to decipher their stacking patterns. The team employed a method called low-frequency Raman spectroscopy to measure how the layers vibrate with respect to each other and compared the frequencies of the measured vibrations with their theoretically predicted values. Their study provides a platform for engineering two-dimensional (2D) materials with optical and electronic properties that strongly depend on stacking configurations. The findings are published in ACS Nano, a journal of the American Chemical Society.

“Low-frequency Raman spectroscopy, in combination with first-principles modeling, offers a quick and easy approach to reveal complex stacking configurations in the twisted bilayers of a promising semiconductor, without relying on other expensive and time-consuming experimental techniques,” said co-lead author Liangbo Liang, a Wigner Fellow at ORNL. “We are the first to show that low-frequency Raman spectra can be used as fingerprints to characterize the relative layer stacking in semiconducting 2D materials.”

In Raman scattering, an optical method for probing atomic vibrations, a material scatters monochromatic light from a laser. Whereas conventional Raman spectroscopy may probe more than approximately 3 trillion atomic vibrations per second, low-frequency Raman spectroscopy detects vibrations that are an order of magnitude slower. The low-frequency technique is sensitive to weak attractive forces between layers, called van der Waals coupling. It can provide crucial insight about layer thickness and stacking–aspects that govern fundamental properties of 2D materials.

“This work combines state-of-the art synthesis and processing of 2D materials, their unique spectroscopic characterization, and data interpretation using first-principles theory,” said co-lead author Alex Puretzky. “High-resolution Raman spectroscopy that can probe low-frequency modes requires specialized instrumentation, and only a few places around the world have such a capability together with advanced synthesis and characterization tools, and theory and computational modeling expertise. The Center for Nanophase Materials Sciences at ORNL is among them.”

Chemical vapor deposition, widely employed to synthesize 2D materials like graphene, was used to make perfectly triangular crystal monolayers of molybdenum diselenide just three atoms thick. Feedstock molecules of molybdenum oxide and sulfur were reacted in a flowing gas within a high-temperature furnace to form the triangular crystals on silicon substrates.

“Numerous parameters need to be properly adjusted to synthesize large, triangular 2D crystals successfully,” Puretzky said. “Then, carefully removing the crystals and stacking them precisely in different orientations is a big challenge.”

He continued, “The precise, equilateral triangular shape of the synthesized and transferred crystals allowed us to measure the twist angles with a high precision using standard optical and atomic force microscopy images, which was a key factor in our experiments.”

Theoretical and computational aspects were challenging too. “Raman spectroscopy is heavily based on theory for interpretation and assignment of the observed Raman spectra, especially for new materials that have never before been measured,” Puretzky said.

The study revealed patterns in the stacked bilayers that strongly depend on the twist angle. Some specific twist angles, though, showed periodically repeating patches with the same stacking orientation. “These unique patterns may provide a new platform for optoelectronic applications of these materials,” Puretzky said.

The team’s findings also showed fascinating effects of the vibrations between the layers. As different stacking patterns appeared when layers were displaced, variable spacings occurred between the layers at some specific twist angles. The researchers plan further measurements and modeling for different stacking configurations to better understand how these vibrational decays might alter the thermal properties of these materials–knowledge that could affect applications in heat dissipation and thermoelectric energy conversion.

A critical milestone has been reached in cadmium telluride (CdTe) solar cell technology, helping pave the way for solar energy to directly compete with electricity generated by conventional energy sources.

Scientists at the Energy Department’s National Renewable Energy Laboratory (NREL) collaborated with researchers at Washington State University and the University of Tennessee to improve the maximum voltage available from a CdTe solar cell, which is a key factor in improving solar cell efficiency.

The research appears in the Nature Energy journal article, “CdTe solar cells with open-circuit voltage breaking the 1 V barrier,” authored by James Burst, Joel Duenow, David Albin, Eric Colegrove, Matthew Reese, Jeffery Aguiar, Chun-Sheng Jiang, Maulik Patel, Mowafak Al-Jassim, Darius Kuciauskas, Santosh Swain, Tursunjun Ablekim, Kelvin Lynn, and Wyatt Metzger.

Silicon solar cells currently represent 90% of the solar cell market, but it will be difficult to significantly reduce their manufacturing costs. CdTe solar cells offer a low-cost alternative. These cells also have the lowest carbon footprint and adapt better than silicon in real-world conditions including hot, humid weather and low light. However, CdTe solar cells have not been as efficient as multicrystalline silicon solar cells until recently.

One key area where CdTe has underperformed is in the maximum voltage available from the solar cell, a measure called open-circuit voltage. The quality of CdTe materials has prevented industry, universities, and national laboratories for the past 60 years from obtaining open-circuit voltage exceeding 900 millivolts on billions of solar cells; the vast majority have been limited to 750 to 850 millivolts.

The research team improved cell voltage by shifting away from a standard processing step using cadmium chloride. Instead, they placed a small number of phosphorus atoms on tellurium lattice sites and then carefully formed ideal interfaces between materials with different atomic spacing to complete the solar cell. This approach improved the CdTe conductivity and carrier lifetime each by orders of magnitude, thereby enabling the fabrication of CdTe solar cells with an open-circuit voltage breaking the 1-volt barrier for the first time. The innovation establishes new research paths for solar cells to become more efficient and provide electricity at lower cost.